1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for lg131x SoCs 4 * 5 * Copyright (C) 2016, LG Electronics 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 interrupt-parent = <&gic>; 16 17 cpus { 18 #address-cells = <2>; 19 #size-cells = <0>; 20 21 cpu0: cpu@0 { 22 device_type = "cpu"; 23 compatible = "arm,cortex-a53"; 24 reg = <0x0 0x0>; 25 next-level-cache = <&L2_0>; 26 }; 27 cpu1: cpu@1 { 28 device_type = "cpu"; 29 compatible = "arm,cortex-a53"; 30 reg = <0x0 0x1>; 31 enable-method = "psci"; 32 next-level-cache = <&L2_0>; 33 }; 34 cpu2: cpu@2 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-a53"; 37 reg = <0x0 0x2>; 38 enable-method = "psci"; 39 next-level-cache = <&L2_0>; 40 }; 41 cpu3: cpu@3 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a53"; 44 reg = <0x0 0x3>; 45 enable-method = "psci"; 46 next-level-cache = <&L2_0>; 47 }; 48 L2_0: l2-cache0 { 49 compatible = "cache"; 50 cache-level = <2>; 51 cache-unified; 52 }; 53 }; 54 55 psci { 56 compatible = "arm,psci-0.2", "arm,psci"; 57 method = "smc"; 58 cpu_suspend = <0x84000001>; 59 cpu_off = <0x84000002>; 60 cpu_on = <0x84000003>; 61 }; 62 63 gic: interrupt-controller@c0001000 { 64 #interrupt-cells = <3>; 65 compatible = "arm,gic-400"; 66 interrupt-controller; 67 reg = <0x0 0xc0001000 0x1000>, 68 <0x0 0xc0002000 0x2000>, 69 <0x0 0xc0004000 0x2000>, 70 <0x0 0xc0006000 0x2000>; 71 }; 72 73 pmu { 74 compatible = "arm,cortex-a53-pmu"; 75 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 79 interrupt-affinity = <&cpu0>, 80 <&cpu1>, 81 <&cpu2>, 82 <&cpu3>; 83 }; 84 85 timer { 86 compatible = "arm,armv8-timer"; 87 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) | 88 IRQ_TYPE_LEVEL_LOW)>, 89 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) | 90 IRQ_TYPE_LEVEL_LOW)>, 91 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) | 92 IRQ_TYPE_LEVEL_LOW)>, 93 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) | 94 IRQ_TYPE_LEVEL_LOW)>; 95 }; 96 97 clk_bus: clk_bus { 98 #clock-cells = <0>; 99 100 compatible = "fixed-clock"; 101 clock-frequency = <198000000>; 102 clock-output-names = "BUSCLK"; 103 }; 104 105 amba { 106 #address-cells = <2>; 107 #size-cells = <1>; 108 109 compatible = "simple-bus"; 110 interrupt-parent = <&gic>; 111 ranges; 112 113 timers: timer@fd100000 { 114 compatible = "arm,sp804", "arm,primecell"; 115 reg = <0x0 0xfd100000 0x1000>; 116 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 117 clocks = <&clk_bus>, <&clk_bus>, <&clk_bus>; 118 clock-names = "timer0clk", "timer1clk", "apb_pclk"; 119 }; 120 wdog: watchdog@fd200000 { 121 compatible = "arm,sp805", "arm,primecell"; 122 reg = <0x0 0xfd200000 0x1000>; 123 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 124 clocks = <&clk_bus>, <&clk_bus>; 125 clock-names = "wdog_clk", "apb_pclk"; 126 }; 127 uart0: serial@fe000000 { 128 compatible = "arm,pl011", "arm,primecell"; 129 reg = <0x0 0xfe000000 0x1000>; 130 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&clk_bus>, <&clk_bus>; 132 clock-names = "uartclk", "apb_pclk"; 133 status = "disabled"; 134 }; 135 uart1: serial@fe100000 { 136 compatible = "arm,pl011", "arm,primecell"; 137 reg = <0x0 0xfe100000 0x1000>; 138 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 139 clocks = <&clk_bus>, <&clk_bus>; 140 clock-names = "uartclk", "apb_pclk"; 141 status = "disabled"; 142 }; 143 uart2: serial@fe200000 { 144 compatible = "arm,pl011", "arm,primecell"; 145 reg = <0x0 0xfe200000 0x1000>; 146 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 147 clocks = <&clk_bus>, <&clk_bus>; 148 clock-names = "uartclk", "apb_pclk"; 149 status = "disabled"; 150 }; 151 spi0: spi@fe800000 { 152 compatible = "arm,pl022", "arm,primecell"; 153 reg = <0x0 0xfe800000 0x1000>; 154 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 155 clocks = <&clk_bus>, <&clk_bus>; 156 clock-names = "sspclk", "apb_pclk"; 157 }; 158 spi1: spi@fe900000 { 159 compatible = "arm,pl022", "arm,primecell"; 160 reg = <0x0 0xfe900000 0x1000>; 161 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 162 clocks = <&clk_bus>, <&clk_bus>; 163 clock-names = "sspclk", "apb_pclk"; 164 }; 165 dmac0: dma-controller@c1128000 { 166 compatible = "arm,pl330", "arm,primecell"; 167 reg = <0x0 0xc1128000 0x1000>; 168 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 169 clocks = <&clk_bus>; 170 clock-names = "apb_pclk"; 171 #dma-cells = <1>; 172 }; 173 gpio0: gpio@fd400000 { 174 #gpio-cells = <2>; 175 compatible = "arm,pl061", "arm,primecell"; 176 gpio-controller; 177 reg = <0x0 0xfd400000 0x1000>; 178 clocks = <&clk_bus>; 179 clock-names = "apb_pclk"; 180 status = "disabled"; 181 }; 182 gpio1: gpio@fd410000 { 183 #gpio-cells = <2>; 184 compatible = "arm,pl061", "arm,primecell"; 185 gpio-controller; 186 reg = <0x0 0xfd410000 0x1000>; 187 clocks = <&clk_bus>; 188 clock-names = "apb_pclk"; 189 status = "disabled"; 190 }; 191 gpio2: gpio@fd420000 { 192 #gpio-cells = <2>; 193 compatible = "arm,pl061", "arm,primecell"; 194 gpio-controller; 195 reg = <0x0 0xfd420000 0x1000>; 196 clocks = <&clk_bus>; 197 clock-names = "apb_pclk"; 198 status = "disabled"; 199 }; 200 gpio3: gpio@fd430000 { 201 #gpio-cells = <2>; 202 compatible = "arm,pl061", "arm,primecell"; 203 gpio-controller; 204 reg = <0x0 0xfd430000 0x1000>; 205 clocks = <&clk_bus>; 206 clock-names = "apb_pclk"; 207 }; 208 gpio4: gpio@fd440000 { 209 #gpio-cells = <2>; 210 compatible = "arm,pl061", "arm,primecell"; 211 gpio-controller; 212 reg = <0x0 0xfd440000 0x1000>; 213 clocks = <&clk_bus>; 214 clock-names = "apb_pclk"; 215 status = "disabled"; 216 }; 217 gpio5: gpio@fd450000 { 218 #gpio-cells = <2>; 219 compatible = "arm,pl061", "arm,primecell"; 220 gpio-controller; 221 reg = <0x0 0xfd450000 0x1000>; 222 clocks = <&clk_bus>; 223 clock-names = "apb_pclk"; 224 status = "disabled"; 225 }; 226 gpio6: gpio@fd460000 { 227 #gpio-cells = <2>; 228 compatible = "arm,pl061", "arm,primecell"; 229 gpio-controller; 230 reg = <0x0 0xfd460000 0x1000>; 231 clocks = <&clk_bus>; 232 clock-names = "apb_pclk"; 233 status = "disabled"; 234 }; 235 gpio7: gpio@fd470000 { 236 #gpio-cells = <2>; 237 compatible = "arm,pl061", "arm,primecell"; 238 gpio-controller; 239 reg = <0x0 0xfd470000 0x1000>; 240 clocks = <&clk_bus>; 241 clock-names = "apb_pclk"; 242 status = "disabled"; 243 }; 244 gpio8: gpio@fd480000 { 245 #gpio-cells = <2>; 246 compatible = "arm,pl061", "arm,primecell"; 247 gpio-controller; 248 reg = <0x0 0xfd480000 0x1000>; 249 clocks = <&clk_bus>; 250 clock-names = "apb_pclk"; 251 status = "disabled"; 252 }; 253 gpio9: gpio@fd490000 { 254 #gpio-cells = <2>; 255 compatible = "arm,pl061", "arm,primecell"; 256 gpio-controller; 257 reg = <0x0 0xfd490000 0x1000>; 258 clocks = <&clk_bus>; 259 clock-names = "apb_pclk"; 260 status = "disabled"; 261 }; 262 gpio10: gpio@fd4a0000 { 263 #gpio-cells = <2>; 264 compatible = "arm,pl061", "arm,primecell"; 265 gpio-controller; 266 reg = <0x0 0xfd4a0000 0x1000>; 267 clocks = <&clk_bus>; 268 clock-names = "apb_pclk"; 269 status = "disabled"; 270 }; 271 gpio11: gpio@fd4b0000 { 272 #gpio-cells = <2>; 273 compatible = "arm,pl061", "arm,primecell"; 274 gpio-controller; 275 reg = <0x0 0xfd4b0000 0x1000>; 276 clocks = <&clk_bus>; 277 clock-names = "apb_pclk"; 278 }; 279 gpio12: gpio@fd4c0000 { 280 #gpio-cells = <2>; 281 compatible = "arm,pl061", "arm,primecell"; 282 gpio-controller; 283 reg = <0x0 0xfd4c0000 0x1000>; 284 clocks = <&clk_bus>; 285 clock-names = "apb_pclk"; 286 status = "disabled"; 287 }; 288 gpio13: gpio@fd4d0000 { 289 #gpio-cells = <2>; 290 compatible = "arm,pl061", "arm,primecell"; 291 gpio-controller; 292 reg = <0x0 0xfd4d0000 0x1000>; 293 clocks = <&clk_bus>; 294 clock-names = "apb_pclk"; 295 status = "disabled"; 296 }; 297 gpio14: gpio@fd4e0000 { 298 #gpio-cells = <2>; 299 compatible = "arm,pl061", "arm,primecell"; 300 gpio-controller; 301 reg = <0x0 0xfd4e0000 0x1000>; 302 clocks = <&clk_bus>; 303 clock-names = "apb_pclk"; 304 status = "disabled"; 305 }; 306 gpio15: gpio@fd4f0000 { 307 #gpio-cells = <2>; 308 compatible = "arm,pl061", "arm,primecell"; 309 gpio-controller; 310 reg = <0x0 0xfd4f0000 0x1000>; 311 clocks = <&clk_bus>; 312 clock-names = "apb_pclk"; 313 status = "disabled"; 314 }; 315 gpio16: gpio@fd500000 { 316 #gpio-cells = <2>; 317 compatible = "arm,pl061", "arm,primecell"; 318 gpio-controller; 319 reg = <0x0 0xfd500000 0x1000>; 320 clocks = <&clk_bus>; 321 clock-names = "apb_pclk"; 322 status = "disabled"; 323 }; 324 gpio17: gpio@fd510000 { 325 #gpio-cells = <2>; 326 compatible = "arm,pl061", "arm,primecell"; 327 gpio-controller; 328 reg = <0x0 0xfd510000 0x1000>; 329 clocks = <&clk_bus>; 330 clock-names = "apb_pclk"; 331 }; 332 }; 333}; 334