1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2026, Altera Corporation 4 */ 5#include "socfpga_agilex.dtsi" 6 7/ { 8 model = "SoCFPGA Agilex SoCDK eMMC daughter board"; 9 compatible = "intel,socfpga-agilex-socdk-emmc", "intel,socfpga-agilex"; 10 11 aliases { 12 serial0 = &uart0; 13 ethernet0 = &gmac0; 14 ethernet1 = &gmac1; 15 ethernet2 = &gmac2; 16 }; 17 18 chosen { 19 stdout-path = "serial0:115200n8"; 20 }; 21 22 leds { 23 compatible = "gpio-leds"; 24 led0 { 25 label = "hps_led0"; 26 gpios = <&portb 20 GPIO_ACTIVE_HIGH>; 27 }; 28 29 led1 { 30 label = "hps_led1"; 31 gpios = <&portb 19 GPIO_ACTIVE_HIGH>; 32 }; 33 34 led2 { 35 label = "hps_led2"; 36 gpios = <&portb 21 GPIO_ACTIVE_HIGH>; 37 }; 38 }; 39 40 memory@80000000 { 41 device_type = "memory"; 42 /* We expect the bootloader to fill in the reg */ 43 reg = <0 0x80000000 0 0>; 44 }; 45}; 46 47&gpio1 { 48 status = "okay"; 49}; 50 51&gmac2 { 52 status = "okay"; 53 /* PHY delays is configured via skew properties */ 54 phy-mode = "rgmii"; 55 phy-handle = <&phy0>; 56 57 max-frame-size = <9000>; 58 59 mdio0 { 60 #address-cells = <1>; 61 #size-cells = <0>; 62 compatible = "snps,dwmac-mdio"; 63 phy0: ethernet-phy@4 { 64 reg = <4>; 65 66 txd0-skew-ps = <0>; /* -420ps */ 67 txd1-skew-ps = <0>; /* -420ps */ 68 txd2-skew-ps = <0>; /* -420ps */ 69 txd3-skew-ps = <0>; /* -420ps */ 70 rxd0-skew-ps = <420>; /* 0ps */ 71 rxd1-skew-ps = <420>; /* 0ps */ 72 rxd2-skew-ps = <420>; /* 0ps */ 73 rxd3-skew-ps = <420>; /* 0ps */ 74 txen-skew-ps = <0>; /* -420ps */ 75 txc-skew-ps = <900>; /* 0ps */ 76 rxdv-skew-ps = <420>; /* 0ps */ 77 rxc-skew-ps = <1680>; /* 780ps */ 78 }; 79 }; 80}; 81 82&mmc { 83 status = "okay"; 84 cap-mmc-highspeed; 85 broken-cd; 86 bus-width = <4>; 87 clk-phase-sd-hs = <0>, <135>; 88}; 89 90&osc1 { 91 clock-frequency = <25000000>; 92}; 93 94&uart0 { 95 status = "okay"; 96}; 97 98&usb0 { 99 status = "okay"; 100 disable-over-current; 101}; 102 103&watchdog0 { 104 status = "okay"; 105}; 106