1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2026, Altera Corporation 4 */ 5/dts-v1/; 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/interrupt-controller/irq.h> 8 9/ { 10 compatible = "intel,socfpga-agilex72"; 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 reserved-memory { 15 #address-cells = <2>; 16 #size-cells = <2>; 17 ranges; 18 19 atf_reserved: atf@80000000 { 20 compatible = "shared-dma-pool"; 21 reg = <0x0 0x80000000 0x0 0x100000>; 22 alignment = <0x1000>; 23 no-map; 24 }; 25 26 service_reserved: svcbuffer@80100000 { 27 compatible = "shared-dma-pool"; 28 reg = <0x0 0x80100000 0x0 0xf00000>; 29 alignment = <0x1000>; 30 no-map; 31 }; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 cpu0: cpu@0 { 39 compatible = "arm,cortex-a520"; 40 device_type = "cpu"; 41 enable-method = "psci"; 42 reg = <0x0>; 43 }; 44 45 cpu1: cpu@100 { 46 compatible = "arm,cortex-a520"; 47 device_type = "cpu"; 48 enable-method = "psci"; 49 reg = <0x100>; 50 }; 51 52 cpu2: cpu@200 { 53 compatible = "arm,cortex-a720"; 54 device_type = "cpu"; 55 enable-method = "psci"; 56 reg = <0x200>; 57 }; 58 59 cpu3: cpu@300 { 60 compatible = "arm,cortex-a720"; 61 device_type = "cpu"; 62 enable-method = "psci"; 63 reg = <0x300>; 64 }; 65 }; 66 67 clocks { 68 uart_clk: uart-clk { 69 compatible = "fixed-clock"; 70 #clock-cells = <0>; 71 clock-frequency = <125000000>; 72 }; 73 }; 74 75 psci { 76 compatible = "arm,psci-0.2"; 77 method = "smc"; 78 }; 79 80 timer { 81 compatible = "arm,armv8-timer"; 82 interrupt-parent = <&intc>; 83 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 84 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 85 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 86 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 87 }; 88 89 intc: interrupt-controller@7000000 { 90 compatible = "arm,gic-v3"; 91 reg = <0x0 0x7000000 0x0 0x10000>, 92 <0x0 0x7080000 0x0 0x100000>; 93 ranges; 94 #interrupt-cells = <3>; 95 #address-cells = <2>; 96 #size-cells = <2>; 97 interrupt-controller; 98 #redistributor-regions = <1>; 99 redistributor-stride = <0x0 0x40000>; 100 101 its: msi-controller@7040000 { 102 compatible = "arm,gic-v3-its"; 103 reg = <0x0 0x7040000 0x0 0x20000>; 104 msi-controller; 105 #msi-cells = <1>; 106 }; 107 }; 108 109 soc: soc@0 { 110 compatible = "simple-bus"; 111 ranges = <0 0 0 0xffffffff>; 112 #address-cells = <1>; 113 #size-cells = <1>; 114 device_type = "soc"; 115 interrupt-parent = <&intc>; 116 117 smmu: iommu@c100000 { 118 compatible = "arm,smmu-v3"; 119 reg = <0x0c100000 0x30000>; 120 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 121 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, 122 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>; 123 interrupt-names = "eventq", "gerror", "priq"; 124 dma-coherent; 125 #iommu-cells = <1>; 126 }; 127 128 ocram: sram@0 { 129 compatible = "mmio-sram"; 130 reg = <0x00000000 0x80000>; 131 ranges = <0 0 0x80000>; 132 #address-cells = <1>; 133 #size-cells = <1>; 134 }; 135 136 uart0: serial@9038000 { 137 compatible = "snps,dw-apb-uart"; 138 reg = <0x9038000 0x100>; 139 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 140 reg-shift = <2>; 141 reg-io-width = <4>; 142 clocks = <&uart_clk>; 143 status = "disabled"; 144 }; 145 146 uart1: serial@9039000 { 147 compatible = "snps,dw-apb-uart"; 148 reg = <0x9039000 0x100>; 149 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 150 reg-shift = <2>; 151 reg-io-width = <4>; 152 clocks = <&uart_clk>; 153 status = "disabled"; 154 }; 155 }; 156}; 157