1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * NXP S32N79 SoC 4 * 5 * Copyright 2026 NXP 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9 10/ { 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cis-bus { 16 compatible = "simple-bus"; 17 ranges = <0x4f200000 0x0 0x4f200000 0xc00000>; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 21 gic: interrupt-controller@4f200000 { 22 compatible = "arm,gic-v3"; 23 reg = <0x4f200000 0x10000>, /* GIC Dist */ 24 <0x4f260000 0x100000>; 25 #interrupt-cells = <3>; 26 interrupt-controller; 27 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 28 #address-cells = <1>; 29 #size-cells = <1>; 30 /* GICR (RD_base + SGI_base) */ 31 ranges; 32 33 its: msi-controller@4f240000 { 34 compatible = "arm,gic-v3-its"; 35 reg = <0x4f240000 0x20000>; 36 #msi-cells = <1>; 37 msi-controller; 38 }; 39 }; 40 41 smmu: iommu@4fc00000 { 42 compatible = "arm,smmu-v3"; 43 reg = <0x4fc00000 0x200000>; 44 interrupt-parent = <&gic>; 45 interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>, 46 <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>, 47 <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>, 48 <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>; 49 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 50 #iommu-cells = <1>; 51 dma-coherent; 52 status = "disabled"; 53 }; 54 }; 55 56 coss-bus { 57 compatible = "simple-bus"; 58 ranges = <0x4a000000 0x0 0x4a000000 0xff0000>, 59 <0x4e000000 0x0 0x4e000000 0x1000000>; 60 #address-cells = <1>; 61 #size-cells = <1>; 62 63 uart0: serial@4a030000 { 64 compatible = "arm,pl011", "arm,primecell"; 65 reg = <0x4a030000 0x1000>; 66 interrupt-parent = <&irqsteer_coss>; 67 interrupts = <264>; 68 clocks = <&clks 0x9a>, <&clks 0x9a>; 69 clock-names = "uartclk", "apb_pclk"; 70 status = "disabled"; 71 }; 72 73 uart5: serial@4a060000 { 74 compatible = "arm,pl011", "arm,primecell"; 75 reg = <0x4a060000 0x1000>; 76 interrupt-parent = <&irqsteer_coss>; 77 interrupts = <269>; 78 clocks = <&clks 0x9a>, <&clks 0x9a>; 79 clock-names = "uartclk", "apb_pclk"; 80 status = "disabled"; 81 }; 82 83 uart6: serial@4aa30000 { 84 compatible = "arm,pl011", "arm,primecell"; 85 reg = <0x4aa30000 0x1000>; 86 interrupt-parent = <&irqsteer_coss>; 87 interrupts = <270>; 88 clocks = <&clks 0x9a>, <&clks 0x9a>; 89 clock-names = "uartclk", "apb_pclk"; 90 status = "disabled"; 91 }; 92 93 uart7: serial@4aa40000 { 94 compatible = "arm,pl011", "arm,primecell"; 95 reg = <0x4aa40000 0x1000>; 96 interrupt-parent = <&irqsteer_coss>; 97 interrupts = <271>; 98 clocks = <&clks 0x9a>, <&clks 0x9a>; 99 clock-names = "uartclk", "apb_pclk"; 100 status = "disabled"; 101 }; 102 103 irqsteer_coss: interrupt-controller@4ed00000 { 104 compatible = "nxp,s32n79-irqsteer"; 105 reg = <0x4ed00000 0x10000>; 106 #interrupt-cells = <1>; 107 interrupt-controller; 108 interrupt-parent = <&gic>; 109 interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>; 117 clocks = <&clks 0x9a>; 118 clock-names = "ipg"; 119 fsl,channel = <0>; 120 fsl,num-irqs = <512>; 121 status = "disabled"; 122 }; 123 }; 124 125 cpus { 126 #address-cells = <1>; 127 #size-cells = <0>; 128 129 cpu-map { 130 cluster0 { 131 core0 { 132 cpu = <&cpu0>; 133 }; 134 135 core1 { 136 cpu = <&cpu1>; 137 }; 138 }; 139 140 cluster1 { 141 core0 { 142 cpu = <&cpu2>; 143 }; 144 145 core1 { 146 cpu = <&cpu3>; 147 }; 148 }; 149 150 cluster2 { 151 core0 { 152 cpu = <&cpu4>; 153 }; 154 155 core1 { 156 cpu = <&cpu5>; 157 }; 158 }; 159 160 cluster3 { 161 core0 { 162 cpu = <&cpu6>; 163 }; 164 165 core1 { 166 cpu = <&cpu7>; 167 }; 168 }; 169 }; 170 171 l2_0: l2-cache0 { 172 compatible = "cache"; 173 cache-level = <2>; 174 cache-line-size = <64>; 175 cache-sets = <512>; 176 cache-size = <524288>; 177 cache-unified; 178 next-level-cache = <&l3_0>; 179 }; 180 181 l2_1: l2-cache1 { 182 compatible = "cache"; 183 cache-level = <2>; 184 cache-line-size = <64>; 185 cache-sets = <512>; 186 cache-size = <524288>; 187 cache-unified; 188 next-level-cache = <&l3_1>; 189 }; 190 191 l2_2: l2-cache2 { 192 compatible = "cache"; 193 cache-level = <2>; 194 cache-line-size = <64>; 195 cache-sets = <512>; 196 cache-size = <524288>; 197 cache-unified; 198 next-level-cache = <&l3_2>; 199 }; 200 201 l2_3: l2-cache3 { 202 compatible = "cache"; 203 cache-level = <2>; 204 cache-line-size = <64>; 205 cache-sets = <512>; 206 cache-size = <524288>; 207 cache-unified; 208 next-level-cache = <&l3_3>; 209 }; 210 211 l3_0: l3-cache0 { 212 compatible = "cache"; 213 cache-level = <3>; 214 cache-line-size = <64>; 215 cache-sets = <1024>; 216 cache-size = <1048576>; 217 cache-unified; 218 }; 219 220 l3_1: l3-cache1 { 221 compatible = "cache"; 222 cache-level = <3>; 223 cache-line-size = <64>; 224 cache-sets = <1024>; 225 cache-size = <1048576>; 226 cache-unified; 227 }; 228 229 l3_2: l3-cache2 { 230 compatible = "cache"; 231 cache-level = <3>; 232 cache-line-size = <64>; 233 cache-sets = <1024>; 234 cache-size = <1048576>; 235 cache-unified; 236 }; 237 238 l3_3: l3-cache3 { 239 compatible = "cache"; 240 cache-level = <3>; 241 cache-line-size = <64>; 242 cache-sets = <1024>; 243 cache-size = <1048576>; 244 cache-unified; 245 }; 246 247 cpu0: cpu@0 { 248 compatible = "arm,cortex-a78ae"; 249 reg = <0x0>; 250 device_type = "cpu"; 251 enable-method = "psci"; 252 next-level-cache = <&l2_0>; 253 }; 254 255 cpu1: cpu@100 { 256 compatible = "arm,cortex-a78ae"; 257 reg = <0x100>; 258 device_type = "cpu"; 259 enable-method = "psci"; 260 next-level-cache = <&l2_0>; 261 }; 262 263 cpu2: cpu@10000 { 264 compatible = "arm,cortex-a78ae"; 265 reg = <0x10000>; 266 device_type = "cpu"; 267 enable-method = "psci"; 268 next-level-cache = <&l2_1>; 269 }; 270 271 cpu3: cpu@10100 { 272 compatible = "arm,cortex-a78ae"; 273 reg = <0x10100>; 274 device_type = "cpu"; 275 enable-method = "psci"; 276 next-level-cache = <&l2_1>; 277 }; 278 279 cpu4: cpu@20000 { 280 compatible = "arm,cortex-a78ae"; 281 reg = <0x20000>; 282 device_type = "cpu"; 283 enable-method = "psci"; 284 next-level-cache = <&l2_2>; 285 }; 286 287 cpu5: cpu@20100 { 288 compatible = "arm,cortex-a78ae"; 289 reg = <0x20100>; 290 device_type = "cpu"; 291 enable-method = "psci"; 292 next-level-cache = <&l2_2>; 293 }; 294 295 cpu6: cpu@30000 { 296 compatible = "arm,cortex-a78ae"; 297 reg = <0x30000>; 298 device_type = "cpu"; 299 enable-method = "psci"; 300 next-level-cache = <&l2_3>; 301 }; 302 303 cpu7: cpu@30100 { 304 compatible = "arm,cortex-a78ae"; 305 reg = <0x30100>; 306 device_type = "cpu"; 307 enable-method = "psci"; 308 next-level-cache = <&l2_3>; 309 }; 310 }; 311 312 firmware { 313 psci { 314 compatible = "arm,psci-1.0"; 315 method = "smc"; 316 }; 317 318 scmi: scmi { 319 compatible = "arm,scmi-smc"; 320 #address-cells = <1>; 321 #size-cells = <0>; 322 shmem = <&scmi_shbuf>; 323 arm,smc-id = <0xc20000fe>; 324 status = "okay"; 325 326 clks: protocol@14 { 327 reg = <0x14>; 328 #clock-cells = <1>; 329 }; 330 }; 331 }; 332 333 fss-bus { 334 compatible = "simple-bus"; 335 ranges = <0x5b490000 0x0 0x5b490000 0x1000>; 336 #address-cells = <1>; 337 #size-cells = <1>; 338 339 usdhc0: mmc@5b490000 { 340 compatible = "nxp,s32n79-usdhc"; 341 reg = <0x5b490000 0x1000>; 342 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&clks 0x58>, <&clks 0x50>, <&clks 0x5f>; 344 clock-names = "ipg", "ahb", "per"; 345 bus-width = <8>; 346 status = "disabled"; 347 }; 348 }; 349 350 pmu: pmu { 351 compatible = "arm,armv8-pmuv3"; 352 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 353 }; 354 355 timer: timer { 356 compatible = "arm,armv8-timer"; 357 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 358 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 359 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 360 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 361 }; 362}; 363