1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2/* 3 * Copyright 2025-2026 NXP 4 */ 5 6#include <dt-bindings/dma/fsl-edma.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9 10#include "imx952-clock.h" 11#include "imx952-pinfunc.h" 12#include "imx952-power.h" 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 clk_ext1: clock-ext1 { 20 compatible = "fixed-clock"; 21 #clock-cells = <0>; 22 clock-frequency = <133000000>; 23 clock-output-names = "clk_ext1"; 24 }; 25 26 clk_dummy: clock-dummy { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <0>; 30 clock-output-names = "dummy"; 31 }; 32 33 clk_ldb_pll_pixel: clock-ldb-pll-div7 { 34 compatible = "fixed-factor-clock"; 35 clocks = <&scmi_clk IMX952_CLK_LDBPLL>; 36 #clock-cells = <0>; 37 clock-div = <7>; 38 clock-mult = <1>; 39 clock-output-names = "ldb_pll_div7"; 40 }; 41 42 clk_osc_24m: clock-osc-24m { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <24000000>; 46 clock-output-names = "osc_24m"; 47 }; 48 49 cpus { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 idle-states { 54 entry-method = "psci"; 55 56 cpu_pd_wait: cpu-pd-wait { 57 compatible = "arm,idle-state"; 58 arm,psci-suspend-param = <0x0010033>; 59 local-timer-stop; 60 entry-latency-us = <1000>; 61 exit-latency-us = <700>; 62 min-residency-us = <2700>; 63 wakeup-latency-us = <1500>; 64 }; 65 }; 66 67 A55_0: cpu@0 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a55"; 70 reg = <0x0>; 71 enable-method = "psci"; 72 #cooling-cells = <2>; 73 cpu-idle-states = <&cpu_pd_wait>; 74 power-domains = <&scmi_perf IMX952_PERF_A55>; 75 power-domain-names = "perf"; 76 i-cache-size = <32768>; 77 i-cache-line-size = <64>; 78 i-cache-sets = <128>; 79 d-cache-size = <32768>; 80 d-cache-line-size = <64>; 81 d-cache-sets = <128>; 82 next-level-cache = <&l2_cache_l0>; 83 }; 84 85 A55_1: cpu@100 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a55"; 88 reg = <0x100>; 89 enable-method = "psci"; 90 #cooling-cells = <2>; 91 cpu-idle-states = <&cpu_pd_wait>; 92 power-domains = <&scmi_perf IMX952_PERF_A55>; 93 power-domain-names = "perf"; 94 i-cache-size = <32768>; 95 i-cache-line-size = <64>; 96 i-cache-sets = <128>; 97 d-cache-size = <32768>; 98 d-cache-line-size = <64>; 99 d-cache-sets = <128>; 100 next-level-cache = <&l2_cache_l1>; 101 }; 102 103 A55_2: cpu@200 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a55"; 106 reg = <0x200>; 107 enable-method = "psci"; 108 #cooling-cells = <2>; 109 cpu-idle-states = <&cpu_pd_wait>; 110 power-domains = <&scmi_perf IMX952_PERF_A55>; 111 power-domain-names = "perf"; 112 i-cache-size = <32768>; 113 i-cache-line-size = <64>; 114 i-cache-sets = <128>; 115 d-cache-size = <32768>; 116 d-cache-line-size = <64>; 117 d-cache-sets = <128>; 118 next-level-cache = <&l2_cache_l2>; 119 }; 120 121 A55_3: cpu@300 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a55"; 124 reg = <0x300>; 125 enable-method = "psci"; 126 #cooling-cells = <2>; 127 cpu-idle-states = <&cpu_pd_wait>; 128 power-domains = <&scmi_perf IMX952_PERF_A55>; 129 power-domain-names = "perf"; 130 i-cache-size = <32768>; 131 i-cache-line-size = <64>; 132 i-cache-sets = <128>; 133 d-cache-size = <32768>; 134 d-cache-line-size = <64>; 135 d-cache-sets = <128>; 136 next-level-cache = <&l2_cache_l3>; 137 }; 138 139 l2_cache_l0: l2-cache-l0 { 140 compatible = "cache"; 141 cache-size = <65536>; 142 cache-line-size = <64>; 143 cache-sets = <256>; 144 cache-level = <2>; 145 cache-unified; 146 next-level-cache = <&l3_cache>; 147 }; 148 149 l2_cache_l1: l2-cache-l1 { 150 compatible = "cache"; 151 cache-size = <65536>; 152 cache-line-size = <64>; 153 cache-sets = <256>; 154 cache-level = <2>; 155 cache-unified; 156 next-level-cache = <&l3_cache>; 157 }; 158 159 l2_cache_l2: l2-cache-l2 { 160 compatible = "cache"; 161 cache-size = <65536>; 162 cache-line-size = <64>; 163 cache-sets = <256>; 164 cache-level = <2>; 165 cache-unified; 166 next-level-cache = <&l3_cache>; 167 }; 168 169 l2_cache_l3: l2-cache-l3 { 170 compatible = "cache"; 171 cache-size = <65536>; 172 cache-line-size = <64>; 173 cache-sets = <256>; 174 cache-level = <2>; 175 cache-unified; 176 next-level-cache = <&l3_cache>; 177 }; 178 179 l3_cache: l3-cache { 180 compatible = "cache"; 181 cache-size = <524288>; 182 cache-line-size = <64>; 183 cache-sets = <512>; 184 cache-level = <3>; 185 cache-unified; 186 }; 187 188 cpu-map { 189 cluster0 { 190 core0 { 191 cpu = <&A55_0>; 192 }; 193 194 core1 { 195 cpu = <&A55_1>; 196 }; 197 198 core2 { 199 cpu = <&A55_2>; 200 }; 201 202 core3 { 203 cpu = <&A55_3>; 204 }; 205 }; 206 }; 207 }; 208 209 firmware { 210 scmi { 211 compatible = "arm,scmi"; 212 mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>, <&mu2 5 1>; 213 shmem = <&scmi_buf0>, <&scmi_buf1>; 214 #address-cells = <1>; 215 #size-cells = <0>; 216 arm,max-rx-timeout-ms = <5000>; 217 218 scmi_devpd: protocol@11 { 219 reg = <0x11>; 220 #power-domain-cells = <1>; 221 }; 222 223 scmi_sys_power: protocol@12 { 224 reg = <0x12>; 225 }; 226 227 scmi_perf: protocol@13 { 228 reg = <0x13>; 229 #power-domain-cells = <1>; 230 }; 231 232 scmi_clk: protocol@14 { 233 reg = <0x14>; 234 #clock-cells = <1>; 235 }; 236 237 scmi_sensor: protocol@15 { 238 reg = <0x15>; 239 #thermal-sensor-cells = <1>; 240 }; 241 242 scmi_iomuxc: protocol@19 { 243 reg = <0x19>; 244 }; 245 246 scmi_lmm: protocol@80 { 247 reg = <0x80>; 248 }; 249 250 scmi_bbm: protocol@81 { 251 reg = <0x81>; 252 }; 253 254 scmi_cpu: protocol@82 { 255 reg = <0x82>; 256 }; 257 258 scmi_misc: protocol@84 { 259 reg = <0x84>; 260 }; 261 }; 262 }; 263 264 gic: interrupt-controller@48000000 { 265 compatible = "arm,gic-v3"; 266 reg = <0 0x48000000 0 0x10000>, 267 <0 0x48060000 0 0xc0000>; 268 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 269 interrupt-parent = <&gic>; 270 interrupt-controller; 271 #interrupt-cells = <3>; 272 dma-noncoherent; 273 #address-cells = <2>; 274 #size-cells = <2>; 275 ranges; 276 277 its: msi-controller@48040000 { 278 compatible = "arm,gic-v3-its"; 279 reg = <0 0x48040000 0 0x20000>; 280 msi-controller; 281 #msi-cells = <1>; 282 dma-noncoherent; 283 }; 284 }; 285 286 pmu { 287 compatible = "arm,cortex-a55-pmu"; 288 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 289 }; 290 291 psci { 292 compatible = "arm,psci-1.0"; 293 method = "smc"; 294 }; 295 296 timer { 297 compatible = "arm,armv8-timer"; 298 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 299 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 300 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 301 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 302 clock-frequency = <24000000>; 303 arm,no-tick-in-suspend; 304 interrupt-parent = <&gic>; 305 }; 306 307 usbphynop1: usbphynop1 { 308 compatible = "usb-nop-xceiv"; 309 #phy-cells = <0>; 310 clocks = <&clk_dummy>; 311 clock-names = "main_clk"; 312 }; 313 314 usbphynop2: usbphynop2 { 315 compatible = "usb-nop-xceiv"; 316 #phy-cells = <0>; 317 clocks = <&clk_dummy>; 318 clock-names = "main_clk"; 319 }; 320 321 soc { 322 compatible = "simple-bus"; 323 #address-cells = <2>; 324 #size-cells = <2>; 325 ranges = <0x0 0x0 0x0 0x0 0x0 0x80000000>, 326 <0x0 0x28000000 0x0 0x28000000 0x0 0x10000000>; 327 328 aips2: bus@42000000 { 329 compatible = "fsl,aips-bus", "simple-bus"; 330 reg = <0x0 0x42000000 0x0 0x800000>; 331 ranges = <0x42000000 0x0 0x42000000 0x8000000>, 332 <0x28000000 0x0 0x28000000 0x10000000>; 333 #address-cells = <1>; 334 #size-cells = <1>; 335 336 mu7: mailbox@42050000 { 337 compatible = "fsl,imx95-mu"; 338 reg = <0x42050000 0x10000>; 339 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; 341 #mbox-cells = <2>; 342 status = "disabled"; 343 }; 344 345 wdog3: watchdog@420b0000 { 346 compatible = "fsl,imx93-wdt"; 347 reg = <0x420b0000 0x10000>; 348 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; 350 timeout-sec = <40>; 351 status = "disabled"; 352 }; 353 354 tpm3: pwm@42100000 { 355 compatible = "fsl,imx7ulp-pwm"; 356 reg = <0x42100000 0x1000>; 357 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; 358 #pwm-cells = <3>; 359 status = "disabled"; 360 }; 361 362 tpm4: pwm@42110000 { 363 compatible = "fsl,imx7ulp-pwm"; 364 reg = <0x42110000 0x1000>; 365 clocks = <&scmi_clk IMX952_CLK_TPM4>; 366 #pwm-cells = <3>; 367 status = "disabled"; 368 }; 369 370 tpm5: pwm@42120000 { 371 compatible = "fsl,imx7ulp-pwm"; 372 reg = <0x42120000 0x1000>; 373 clocks = <&scmi_clk IMX952_CLK_TPM5>; 374 #pwm-cells = <3>; 375 status = "disabled"; 376 }; 377 378 tpm6: pwm@42130000 { 379 compatible = "fsl,imx7ulp-pwm"; 380 reg = <0x42130000 0x1000>; 381 clocks = <&scmi_clk IMX952_CLK_TPM6>; 382 #pwm-cells = <3>; 383 status = "disabled"; 384 }; 385 386 i3c2: i3c@42140000 { 387 compatible = "silvaco,i3c-master-v1"; 388 reg = <0x42140000 0x10000>; 389 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 390 #address-cells = <3>; 391 #size-cells = <0>; 392 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, 393 <&scmi_clk IMX952_CLK_I3C2SLOW>, 394 <&clk_dummy>; 395 clock-names = "pclk", "fast_clk", "slow_clk"; 396 status = "disabled"; 397 }; 398 399 lpi2c3: i2c@42150000 { 400 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 401 reg = <0x42150000 0x10000>; 402 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&scmi_clk IMX952_CLK_LPI2C3>, 404 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 405 clock-names = "per", "ipg"; 406 #address-cells = <1>; 407 #size-cells = <0>; 408 dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>; 409 dma-names = "tx", "rx"; 410 status = "disabled"; 411 }; 412 413 lpi2c4: i2c@42160000 { 414 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 415 reg = <0x42160000 0x10000>; 416 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 417 clocks = <&scmi_clk IMX952_CLK_LPI2C4>, 418 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 419 clock-names = "per", "ipg"; 420 #address-cells = <1>; 421 #size-cells = <0>; 422 dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>; 423 dma-names = "tx", "rx"; 424 status = "disabled"; 425 }; 426 427 lpspi3: spi@42170000 { 428 #address-cells = <1>; 429 #size-cells = <0>; 430 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 431 reg = <0x42170000 0x10000>; 432 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 433 clocks = <&scmi_clk IMX952_CLK_LPSPI3>, 434 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 435 clock-names = "per", "ipg"; 436 dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>; 437 dma-names = "tx", "rx"; 438 status = "disabled"; 439 }; 440 441 lpspi4: spi@42180000 { 442 #address-cells = <1>; 443 #size-cells = <0>; 444 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 445 reg = <0x42180000 0x10000>; 446 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 447 clocks = <&scmi_clk IMX952_CLK_LPSPI4>, 448 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 449 clock-names = "per", "ipg"; 450 dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>; 451 dma-names = "tx", "rx"; 452 status = "disabled"; 453 }; 454 455 lpuart3: serial@42190000 { 456 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 457 "fsl,imx7ulp-lpuart"; 458 reg = <0x42190000 0x1000>; 459 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&scmi_clk IMX952_CLK_LPUART3>; 461 clock-names = "ipg"; 462 dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>; 463 dma-names = "rx", "tx"; 464 status = "disabled"; 465 }; 466 467 lpuart4: serial@421a0000 { 468 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 469 "fsl,imx7ulp-lpuart"; 470 reg = <0x421a0000 0x1000>; 471 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&scmi_clk IMX952_CLK_LPUART4>; 473 clock-names = "ipg"; 474 dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>; 475 dma-names = "rx", "tx"; 476 status = "disabled"; 477 }; 478 479 lpuart5: serial@421b0000 { 480 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 481 "fsl,imx7ulp-lpuart"; 482 reg = <0x421b0000 0x1000>; 483 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 484 clocks = <&scmi_clk IMX952_CLK_LPUART5>; 485 clock-names = "ipg"; 486 dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>; 487 dma-names = "rx", "tx"; 488 status = "disabled"; 489 }; 490 491 lpuart6: serial@421c0000 { 492 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 493 "fsl,imx7ulp-lpuart"; 494 reg = <0x421c0000 0x1000>; 495 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&scmi_clk IMX952_CLK_LPUART6>; 497 clock-names = "ipg"; 498 dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>; 499 dma-names = "rx", "tx"; 500 status = "disabled"; 501 }; 502 503 flexcan2: can@421d0000 { 504 compatible = "fsl,imx95-flexcan"; 505 reg = <0x421d0000 0x10000>; 506 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, 508 <&scmi_clk IMX952_CLK_CAN2>; 509 clock-names = "ipg", "per"; 510 assigned-clocks = <&scmi_clk IMX952_CLK_CAN2>; 511 assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1_DIV2>; 512 assigned-clock-rates = <40000000>; 513 fsl,clk-source = /bits/ 8 <0>; 514 status = "disabled"; 515 }; 516 517 flexcan3: can@42220000 { 518 compatible = "fsl,imx95-flexcan"; 519 reg = <0x42220000 0x10000>; 520 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, 522 <&scmi_clk IMX952_CLK_CAN3>; 523 clock-names = "ipg", "per"; 524 assigned-clocks = <&scmi_clk IMX952_CLK_CAN3>; 525 assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1_DIV2>; 526 assigned-clock-rates = <40000000>; 527 fsl,clk-source = /bits/ 8 <0>; 528 status = "disabled"; 529 }; 530 531 lpuart7: serial@422b0000 { 532 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 533 "fsl,imx7ulp-lpuart"; 534 reg = <0x422b0000 0x1000>; 535 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&scmi_clk IMX952_CLK_LPUART7>; 537 clock-names = "ipg"; 538 dmas = <&edma2 88 0 FSL_EDMA_RX>, <&edma2 87 0 0>; 539 dma-names = "rx", "tx"; 540 status = "disabled"; 541 }; 542 543 lpuart8: serial@422c0000 { 544 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 545 "fsl,imx7ulp-lpuart"; 546 reg = <0x422c0000 0x1000>; 547 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&scmi_clk IMX952_CLK_LPUART8>; 549 clock-names = "ipg"; 550 dmas = <&edma2 90 0 FSL_EDMA_RX>, <&edma2 89 0 0>; 551 dma-names = "rx", "tx"; 552 status = "disabled"; 553 }; 554 555 lpi2c5: i2c@422d0000 { 556 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 557 reg = <0x422d0000 0x10000>; 558 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&scmi_clk IMX952_CLK_LPI2C5>, 560 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 561 clock-names = "per", "ipg"; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>; 565 dma-names = "tx", "rx"; 566 status = "disabled"; 567 }; 568 569 lpi2c6: i2c@422e0000 { 570 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 571 reg = <0x422e0000 0x10000>; 572 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&scmi_clk IMX952_CLK_LPI2C6>, 574 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 575 clock-names = "per", "ipg"; 576 #address-cells = <1>; 577 #size-cells = <0>; 578 dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>; 579 dma-names = "tx", "rx"; 580 status = "disabled"; 581 }; 582 583 lpi2c7: i2c@422f0000 { 584 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 585 reg = <0x422f0000 0x10000>; 586 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 587 clocks = <&scmi_clk IMX952_CLK_LPI2C7>, 588 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 589 clock-names = "per", "ipg"; 590 #address-cells = <1>; 591 #size-cells = <0>; 592 dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>; 593 dma-names = "tx", "rx"; 594 status = "disabled"; 595 }; 596 597 lpi2c8: i2c@42300000 { 598 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 599 reg = <0x42300000 0x10000>; 600 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 601 clocks = <&scmi_clk IMX952_CLK_LPI2C8>, 602 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 603 clock-names = "per", "ipg"; 604 #address-cells = <1>; 605 #size-cells = <0>; 606 dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>; 607 dma-names = "tx", "rx"; 608 status = "disabled"; 609 }; 610 611 lpspi5: spi@42310000 { 612 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 613 reg = <0x42310000 0x10000>; 614 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 615 #address-cells = <1>; 616 #size-cells = <0>; 617 clocks = <&scmi_clk IMX952_CLK_LPSPI5>, 618 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 619 clock-names = "per", "ipg"; 620 dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>; 621 dma-names = "tx", "rx"; 622 status = "disabled"; 623 }; 624 625 lpspi6: spi@42320000 { 626 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 627 reg = <0x42320000 0x10000>; 628 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 629 #address-cells = <1>; 630 #size-cells = <0>; 631 clocks = <&scmi_clk IMX952_CLK_LPSPI6>, 632 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 633 clock-names = "per", "ipg"; 634 dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>; 635 dma-names = "tx", "rx"; 636 status = "disabled"; 637 }; 638 639 lpspi7: spi@42330000 { 640 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 641 reg = <0x42330000 0x10000>; 642 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 643 #address-cells = <1>; 644 #size-cells = <0>; 645 clocks = <&scmi_clk IMX952_CLK_LPSPI7>, 646 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 647 clock-names = "per", "ipg"; 648 dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>; 649 dma-names = "tx", "rx"; 650 status = "disabled"; 651 }; 652 653 lpspi8: spi@42340000 { 654 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 655 reg = <0x42340000 0x10000>; 656 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 clocks = <&scmi_clk IMX952_CLK_LPSPI8>, 660 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 661 clock-names = "per", "ipg"; 662 dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>; 663 dma-names = "tx", "rx"; 664 status = "disabled"; 665 }; 666 667 mu8: mailbox@42350000 { 668 compatible = "fsl,imx95-mu"; 669 reg = <0x42350000 0x10000>; 670 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 671 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; 672 #mbox-cells = <2>; 673 status = "disabled"; 674 }; 675 }; 676 677 aips3: bus@42800000 { 678 compatible = "fsl,aips-bus", "simple-bus"; 679 reg = <0 0x42800000 0 0x800000>; 680 #address-cells = <1>; 681 #size-cells = <1>; 682 ranges = <0x42800000 0x0 0x42800000 0x800000>; 683 684 edma2: dma-controller@42800000 { 685 compatible = "fsl,imx95-edma5"; 686 reg = <0x42800000 0x210000>; 687 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; 688 clock-names = "dma"; 689 #dma-cells = <3>; 690 dma-channels = <64>; 691 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; //error irq 756 }; 757 758 usdhc1: mmc@42c20000 { 759 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 760 reg = <0x42c20000 0x10000>; 761 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 762 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, 763 <&scmi_clk IMX952_CLK_WAKEUPAXI>, 764 <&scmi_clk IMX952_CLK_USDHC1>; 765 clock-names = "ipg", "ahb", "per"; 766 assigned-clocks = <&scmi_clk IMX952_CLK_USDHC1>; 767 assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1>; 768 assigned-clock-rates = <400000000>; 769 bus-width = <8>; 770 fsl,tuning-start-tap = <1>; 771 fsl,tuning-step= <2>; 772 status = "disabled"; 773 }; 774 775 usdhc2: mmc@42c30000 { 776 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 777 reg = <0x42c30000 0x10000>; 778 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, 780 <&scmi_clk IMX952_CLK_WAKEUPAXI>, 781 <&scmi_clk IMX952_CLK_USDHC2>; 782 clock-names = "ipg", "ahb", "per"; 783 assigned-clocks = <&scmi_clk IMX952_CLK_USDHC2>; 784 assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1>; 785 assigned-clock-rates = <200000000>; 786 bus-width = <4>; 787 fsl,tuning-start-tap = <1>; 788 fsl,tuning-step= <2>; 789 status = "disabled"; 790 }; 791 792 usdhc3: mmc@42c40000 { 793 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 794 reg = <0x42c40000 0x10000>; 795 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, 797 <&scmi_clk IMX952_CLK_WAKEUPAXI>, 798 <&scmi_clk IMX952_CLK_USDHC3>; 799 clock-names = "ipg", "ahb", "per"; 800 bus-width = <4>; 801 fsl,tuning-start-tap = <1>; 802 fsl,tuning-step = <2>; 803 status = "disabled"; 804 }; 805 }; 806 807 gpio2: gpio@43810000 { 808 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 809 reg = <0x0 0x43810000 0x0 0x1000>; 810 gpio-controller; 811 #gpio-cells = <2>; 812 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 814 interrupt-controller; 815 #interrupt-cells = <2>; 816 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, 817 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 818 clock-names = "gpio", "port"; 819 gpio-ranges = <&scmi_iomuxc 0 4 32>; 820 ngpios = <32>; 821 }; 822 823 gpio3: gpio@43820000 { 824 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 825 reg = <0x0 0x43820000 0x0 0x1000>; 826 gpio-controller; 827 #gpio-cells = <2>; 828 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 830 interrupt-controller; 831 #interrupt-cells = <2>; 832 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, 833 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 834 clock-names = "gpio", "port"; 835 gpio-ranges = <&scmi_iomuxc 0 115 8>, <&scmi_iomuxc 8 85 18>, 836 <&scmi_iomuxc 26 53 2>, <&scmi_iomuxc 28 0 4>; 837 ngpios = <32>; 838 }; 839 840 gpio4: gpio@43840000 { 841 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 842 reg = <0x0 0x43840000 0x0 0x1000>; 843 gpio-controller; 844 #gpio-cells = <2>; 845 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 846 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 847 interrupt-controller; 848 #interrupt-cells = <2>; 849 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, 850 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 851 clock-names = "gpio", "port"; 852 gpio-ranges = <&scmi_iomuxc 0 57 28>, <&scmi_iomuxc 28 55 2>; 853 ngpios = <30>; 854 }; 855 856 gpio5: gpio@43850000 { 857 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 858 reg = <0x0 0x43850000 0x0 0x1000>; 859 gpio-controller; 860 #gpio-cells = <2>; 861 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 863 interrupt-controller; 864 #interrupt-cells = <2>; 865 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, 866 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 867 clock-names = "gpio", "port"; 868 gpio-ranges = <&scmi_iomuxc 0 103 12>, <&scmi_iomuxc 12 36 6>; 869 ngpios = <18>; 870 }; 871 872 aips1: bus@44000000 { 873 compatible = "fsl,aips-bus", "simple-bus"; 874 reg = <0x0 0x44000000 0x0 0x800000>; 875 ranges = <0x44000000 0x0 0x44000000 0x800000>; 876 #address-cells = <1>; 877 #size-cells = <1>; 878 879 edma1: dma-controller@44000000 { 880 compatible = "fsl,imx93-edma3"; 881 reg = <0x44000000 0x210000>; 882 clocks = <&scmi_clk IMX952_CLK_BUSAON>; 883 clock-names = "dma"; 884 #dma-cells = <3>; 885 dma-channels = <32>; 886 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 892 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 893 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 894 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 895 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 917 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 918 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; //error irq 919 }; 920 921 mu1: mailbox@44220000 { 922 compatible = "fsl,imx95-mu"; 923 reg = <0x44220000 0x10000>; 924 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 925 clocks = <&scmi_clk IMX952_CLK_BUSAON>; 926 #mbox-cells = <2>; 927 status = "disabled"; 928 }; 929 930 system_counter: timer@44290000 { 931 compatible = "nxp,imx95-sysctr-timer"; 932 reg = <0x44290000 0x30000>; 933 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 934 clocks = <&clk_osc_24m>; 935 clock-names = "per"; 936 nxp,no-divider; 937 }; 938 939 i3c1: i3c@44330000 { 940 compatible = "silvaco,i3c-master-v1"; 941 reg = <0x44330000 0x10000>; 942 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 943 #address-cells = <3>; 944 #size-cells = <0>; 945 clocks = <&scmi_clk IMX952_CLK_BUSAON>, 946 <&scmi_clk IMX952_CLK_I3C1SLOW>, 947 <&clk_dummy>; 948 clock-names = "pclk", "fast_clk", "slow_clk"; 949 status = "disabled"; 950 }; 951 952 lpi2c1: i2c@44340000 { 953 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 954 reg = <0x44340000 0x10000>; 955 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 956 clocks = <&scmi_clk IMX952_CLK_LPI2C1>, 957 <&scmi_clk IMX952_CLK_BUSAON>; 958 clock-names = "per", "ipg"; 959 #address-cells = <1>; 960 #size-cells = <0>; 961 dmas = <&edma1 12 0 0>, <&edma1 13 0 FSL_EDMA_RX> ; 962 dma-names = "tx", "rx"; 963 status = "disabled"; 964 }; 965 966 lpi2c2: i2c@44350000 { 967 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 968 reg = <0x44350000 0x10000>; 969 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 970 clocks = <&scmi_clk IMX952_CLK_LPI2C2>, 971 <&scmi_clk IMX952_CLK_BUSAON>; 972 clock-names = "per", "ipg"; 973 #address-cells = <1>; 974 #size-cells = <0>; 975 dmas = <&edma1 14 0 0>, <&edma1 15 0 FSL_EDMA_RX> ; 976 dma-names = "tx", "rx"; 977 status = "disabled"; 978 }; 979 980 lpspi1: spi@44360000 { 981 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 982 reg = <0x44360000 0x10000>; 983 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 984 clocks = <&scmi_clk IMX952_CLK_LPSPI1>, 985 <&scmi_clk IMX952_CLK_BUSAON>; 986 clock-names = "per", "ipg"; 987 #address-cells = <1>; 988 #size-cells = <0>; 989 dmas = <&edma1 16 0 FSL_EDMA_RX>, <&edma1 17 0 0> ; 990 dma-names = "tx", "rx"; 991 status = "disabled"; 992 }; 993 994 lpspi2: spi@44370000 { 995 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 996 reg = <0x44370000 0x10000>; 997 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 998 clocks = <&scmi_clk IMX952_CLK_LPSPI2>, 999 <&scmi_clk IMX952_CLK_BUSAON>; 1000 clock-names = "per", "ipg"; 1001 #address-cells = <1>; 1002 #size-cells = <0>; 1003 dmas = <&edma1 18 0 FSL_EDMA_RX>, <&edma1 19 0 0> ; 1004 dma-names = "tx", "rx"; 1005 status = "disabled"; 1006 }; 1007 1008 lpuart1: serial@44380000 { 1009 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 1010 "fsl,imx7ulp-lpuart"; 1011 reg = <0x44380000 0x1000>; 1012 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1013 clocks = <&scmi_clk IMX952_CLK_LPUART1>; 1014 clock-names = "ipg"; 1015 dmas = <&edma1 21 0 FSL_EDMA_RX>, <&edma1 20 0 0>; 1016 dma-names = "rx", "tx"; 1017 status = "disabled"; 1018 }; 1019 1020 lpuart2: serial@44390000 { 1021 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 1022 "fsl,imx7ulp-lpuart"; 1023 reg = <0x44390000 0x1000>; 1024 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1025 clocks = <&scmi_clk IMX952_CLK_LPUART2>; 1026 clock-names = "ipg"; 1027 dmas = <&edma1 23 0 FSL_EDMA_RX>, <&edma1 22 0 0>; 1028 dma-names = "rx", "tx"; 1029 status = "disabled"; 1030 }; 1031 1032 flexcan1: can@443a0000 { 1033 compatible = "fsl,imx95-flexcan"; 1034 reg = <0x443a0000 0x10000>; 1035 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1036 clocks = <&scmi_clk IMX952_CLK_BUSAON>, 1037 <&scmi_clk IMX952_CLK_CAN1>; 1038 clock-names = "ipg", "per"; 1039 assigned-clocks = <&scmi_clk IMX952_CLK_CAN1>; 1040 assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1_DIV2>; 1041 assigned-clock-rates = <40000000>; 1042 fsl,clk-source = /bits/ 8 <0>; 1043 status = "disabled"; 1044 }; 1045 1046 adc1: adc@44530000 { 1047 compatible = "nxp,imx93-adc"; 1048 reg = <0x44530000 0x10000>; 1049 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1050 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1051 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 1052 clocks = <&scmi_clk IMX952_CLK_ADC>; 1053 clock-names = "ipg"; 1054 #io-channel-cells = <1>; 1055 status = "disabled"; 1056 }; 1057 1058 mu2: mailbox@445b0000 { 1059 compatible = "fsl,imx95-mu"; 1060 reg = <0x445b0000 0x1000>; 1061 ranges; 1062 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1063 #address-cells = <1>; 1064 #size-cells = <1>; 1065 #mbox-cells = <2>; 1066 1067 sram0: sram@445b1000 { 1068 compatible = "mmio-sram"; 1069 reg = <0x445b1000 0x400>; 1070 ranges = <0x0 0x445b1000 0x400>; 1071 #address-cells = <1>; 1072 #size-cells = <1>; 1073 1074 scmi_buf0: scmi-sram-section@0 { 1075 compatible = "arm,scmi-shmem"; 1076 reg = <0x0 0x80>; 1077 }; 1078 1079 scmi_buf1: scmi-sram-section@80 { 1080 compatible = "arm,scmi-shmem"; 1081 reg = <0x80 0x80>; 1082 }; 1083 }; 1084 1085 }; 1086 1087 mu3: mailbox@445d0000 { 1088 compatible = "fsl,imx95-mu"; 1089 reg = <0x445d0000 0x10000>; 1090 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 1091 clocks = <&scmi_clk IMX952_CLK_BUSAON>; 1092 #mbox-cells = <2>; 1093 status = "disabled"; 1094 }; 1095 1096 mu4: mailbox@445f0000 { 1097 compatible = "fsl,imx95-mu"; 1098 reg = <0x445f0000 0x10000>; 1099 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 1100 clocks = <&scmi_clk IMX952_CLK_BUSAON>; 1101 #mbox-cells = <2>; 1102 status = "disabled"; 1103 }; 1104 1105 mu5: mailbox@44610000 { 1106 compatible = "fsl,imx95-mu"; 1107 reg = <0x44610000 0x10000>; 1108 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 1109 clocks = <&scmi_clk IMX952_CLK_BUSAON>; 1110 #mbox-cells = <2>; 1111 status = "disabled"; 1112 }; 1113 1114 mu6: mailbox@44630000 { 1115 compatible = "fsl,imx95-mu"; 1116 reg = <0x44630000 0x10000>; 1117 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1118 clocks = <&scmi_clk IMX952_CLK_BUSAON>; 1119 #mbox-cells = <2>; 1120 status = "disabled"; 1121 }; 1122 }; 1123 1124 v2x_mu0: mailbox@47300000 { 1125 compatible = "fsl,imx95-mu-v2x"; 1126 reg = <0x0 0x47300000 0x0 0x10000>; 1127 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1128 #mbox-cells = <2>; 1129 }; 1130 1131 v2x_mu2: mailbox@47320000 { 1132 compatible = "fsl,imx95-mu-v2x"; 1133 reg = <0x0 0x47320000 0x0 0x10000>; 1134 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 1135 #mbox-cells = <2>; 1136 }; 1137 1138 v2x_mu3: mailbox@47330000 { 1139 compatible = "fsl,imx95-mu-v2x"; 1140 reg = <0x0 0x47330000 0x0 0x10000>; 1141 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1142 #mbox-cells = <2>; 1143 }; 1144 1145 v2x_mu4: mailbox@47340000 { 1146 compatible = "fsl,imx95-mu-v2x"; 1147 reg = <0x0 0x47340000 0x0 0x10000>; 1148 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1149 #mbox-cells = <2>; 1150 }; 1151 1152 v2x_mu: mailbox@47350000 { 1153 compatible = "fsl,imx95-mu-v2x"; 1154 reg = <0x0 0x47350000 0x0 0x10000>; 1155 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1156 #mbox-cells = <2>; 1157 }; 1158 1159 /* GPIO1 is under exclusive control of System Manager */ 1160 gpio1: gpio@47400000 { 1161 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1162 reg = <0x0 0x47400000 0x0 0x1000>; 1163 gpio-controller; 1164 #gpio-cells = <2>; 1165 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1167 interrupt-controller; 1168 #interrupt-cells = <2>; 1169 clocks = <&scmi_clk IMX952_CLK_M33>, 1170 <&scmi_clk IMX952_CLK_M33>; 1171 clock-names = "gpio", "port"; 1172 gpio-ranges = <&scmi_iomuxc 0 123 16>; 1173 ngpios = <16>; 1174 status = "disabled"; 1175 }; 1176 1177 elemu0: mailbox@47520000 { 1178 compatible = "fsl,imx95-mu-ele"; 1179 reg = <0x0 0x47520000 0x0 0x10000>; 1180 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1181 #mbox-cells = <2>; 1182 status = "disabled"; 1183 }; 1184 1185 elemu1: mailbox@47530000 { 1186 compatible = "fsl,imx95-mu-ele"; 1187 reg = <0x0 0x47530000 0x0 0x10000>; 1188 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1189 #mbox-cells = <2>; 1190 status = "disabled"; 1191 }; 1192 1193 elemu2: mailbox@47540000 { 1194 compatible = "fsl,imx95-mu-ele"; 1195 reg = <0x0 0x47540000 0x0 0x10000>; 1196 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1197 #mbox-cells = <2>; 1198 status = "disabled"; 1199 }; 1200 1201 elemu3: mailbox@47550000 { 1202 compatible = "fsl,imx95-mu-ele"; 1203 reg = <0x0 0x47550000 0x0 0x10000>; 1204 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1205 #mbox-cells = <2>; 1206 }; 1207 1208 elemu4: mailbox@47560000 { 1209 compatible = "fsl,imx95-mu-ele"; 1210 reg = <0x0 0x47560000 0x0 0x10000>; 1211 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1212 #mbox-cells = <2>; 1213 status = "disabled"; 1214 }; 1215 1216 elemu5: mailbox@47570000 { 1217 compatible = "fsl,imx95-mu-ele"; 1218 reg = <0x0 0x47570000 0x0 0x10000>; 1219 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1220 #mbox-cells = <2>; 1221 status = "disabled"; 1222 }; 1223 1224 usb1: usb@4c100000 { 1225 compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; 1226 reg = <0x0 0x4c100000 0x0 0x200>; 1227 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1229 clocks = <&scmi_clk IMX952_CLK_CGC_HSIOUSB>, 1230 <&scmi_clk IMX952_CLK_OSC32K>; 1231 clock-names = "usb_ctrl_root", "usb_wakeup"; 1232 power-domains = <&scmi_devpd IMX952_PD_HSIO_TOP>; 1233 phys = <&usbphynop1>; 1234 fsl,usbmisc = <&usbmisc1 0>; 1235 status = "disabled"; 1236 }; 1237 1238 usbmisc1: usbmisc@4c100200 { 1239 compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 1240 #index-cells = <1>; 1241 reg = <0x0 0x4c100200 0x0 0x200>, 1242 <0x0 0x4c010010 0x0 0x4>; 1243 }; 1244 1245 usb2: usb@4c200000 { 1246 compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; 1247 reg = <0x0 0x4c200000 0x0 0x200>; 1248 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1250 clocks = <&scmi_clk IMX952_CLK_CGC_HSIOUSB>, 1251 <&scmi_clk IMX952_CLK_OSC32K>; 1252 clock-names = "usb_ctrl_root", "usb_wakeup"; 1253 power-domains = <&scmi_devpd IMX952_PD_HSIO_TOP>; 1254 phys = <&usbphynop2>; 1255 fsl,usbmisc = <&usbmisc2 0>; 1256 status = "disabled"; 1257 }; 1258 1259 usbmisc2: usbmisc@4c200200 { 1260 compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 1261 #index-cells = <1>; 1262 reg = <0x0 0x4c200200 0x0 0x200>, 1263 <0x0 0x4c010014 0x0 0x4>; 1264 }; 1265 }; 1266}; 1267