1 /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ 2 /* 3 * Copyright 2025 NXP 4 */ 5 6 #ifndef __IMX952_POWER_H__ 7 #define __IMX952_POWER_H__ 8 9 #define IMX952_PD_ANA 0 10 #define IMX952_PD_AON 1 11 #define IMX952_PD_BBSM 2 12 #define IMX952_PD_CAMERA 3 13 #define IMX952_PD_CCMSRCGPC 4 14 #define IMX952_PD_A55C0 5 15 #define IMX952_PD_A55C1 6 16 #define IMX952_PD_A55C2 7 17 #define IMX952_PD_A55C3 8 18 #define IMX952_PD_A55P 9 19 #define IMX952_PD_DDR 10 20 #define IMX952_PD_DISPLAY 11 21 #define IMX952_PD_GPU 12 22 #define IMX952_PD_HSIO_TOP 13 23 #define IMX952_PD_HSIO_WAON 14 24 #define IMX952_PD_M7 15 25 #define IMX952_PD_NETC 16 26 #define IMX952_PD_NOC 17 27 #define IMX952_PD_NPU 18 28 #define IMX952_PD_VPU 19 29 #define IMX952_PD_WAKEUP 20 30 31 #define IMX952_PERF_M33 0 32 #define IMX952_PERF_WAKEUP 1 33 #define IMX952_PERF_M7 2 34 #define IMX952_PERF_DRAM 3 35 #define IMX952_PERF_HSIO 4 36 #define IMX952_PERF_NPU 5 37 #define IMX952_PERF_NOC 6 38 #define IMX952_PERF_A55 7 39 #define IMX952_PERF_GPU 8 40 #define IMX952_PERF_VPU 9 41 #define IMX952_PERF_CAM 10 42 #define IMX952_PERF_DISP 11 43 44 #endif 45