1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2025-2026 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/pwm/pwm.h> 9#include <dt-bindings/usb/pd.h> 10#include "imx952.dtsi" 11 12#define FALLING_EDGE BIT(0) 13#define RISING_EDGE BIT(1) 14 15#define BRD_SM_CTRL_SD3_WAKE 0x8000U /*!< PCAL6408A-0 */ 16#define BRD_SM_CTRL_M2E_WAKE 0x8001U /*!< PCAL6408A-4 */ 17#define BRD_SM_CTRL_BT_WAKE 0x8002U /*!< PCAL6408A-5 */ 18#define BRD_SM_CTRL_M2M_WAKE 0x8003U /*!< PCAL6408A-6 */ 19#define BRD_SM_CTRL_BUTTON 0x8004U /*!< PCAL6408A-7 */ 20 21/ { 22 model = "NXP i.MX952 EVK board"; 23 compatible = "fsl,imx952-evk", "fsl,imx952"; 24 25 aliases { 26 gpio0 = &gpio1; 27 gpio1 = &gpio2; 28 gpio2 = &gpio3; 29 gpio3 = &gpio4; 30 gpio4 = &gpio5; 31 i2c0 = &lpi2c1; 32 i2c1 = &lpi2c2; 33 i2c2 = &lpi2c3; 34 i2c3 = &lpi2c4; 35 i2c4 = &lpi2c5; 36 i2c5 = &lpi2c6; 37 i2c6 = &lpi2c7; 38 i2c7 = &lpi2c8; 39 mmc0 = &usdhc1; 40 mmc1 = &usdhc2; 41 serial0 = &lpuart1; 42 serial4 = &lpuart5; 43 spi6 = &lpspi7; 44 }; 45 46 chosen { 47 stdout-path = &lpuart1; 48 }; 49 50 memory@80000000 { 51 device_type = "memory"; 52 reg = <0x0 0x80000000 0 0x80000000>; 53 }; 54 55 fan0: pwm-fan { 56 compatible = "pwm-fan"; 57 #cooling-cells = <2>; 58 pwms = <&tpm6 2 4000000 PWM_POLARITY_INVERTED>; 59 cooling-levels = <64 128 192 255>; 60 }; 61 62 reserved-memory { 63 #address-cells = <2>; 64 #size-cells = <2>; 65 ranges; 66 67 linux_cma: linux,cma { 68 compatible = "shared-dma-pool"; 69 alloc-ranges = <0 0x80000000 0 0x7f000000>; 70 size = <0 0x3c000000>; 71 linux,cma-default; 72 reusable; 73 }; 74 }; 75 76 flexcan1_phy: can-phy0 { 77 compatible = "nxp,tjr1443"; 78 #phy-cells = <0>; 79 max-bitrate = <8000000>; 80 enable-gpios = <&pcal6416 6 GPIO_ACTIVE_HIGH>; 81 standby-gpios = <&pcal6416 5 GPIO_ACTIVE_LOW>; 82 }; 83 84 flexcan2_phy: can-phy1 { 85 compatible = "nxp,tjr1443"; 86 #phy-cells = <0>; 87 max-bitrate = <8000000>; 88 enable-gpios = <&i2c4_pcal6408 4 GPIO_ACTIVE_HIGH>; 89 standby-gpios = <&i2c4_pcal6408 3 GPIO_ACTIVE_LOW>; 90 }; 91 92 reg_3p3v: regulator-3p3v { 93 compatible = "regulator-fixed"; 94 regulator-max-microvolt = <3300000>; 95 regulator-min-microvolt = <3300000>; 96 regulator-name = "+V3.3_SW"; 97 }; 98 99 reg_1p8v: regulator-1p8v { 100 compatible = "regulator-fixed"; 101 regulator-max-microvolt = <1800000>; 102 regulator-min-microvolt = <1800000>; 103 regulator-name = "+V1.8_SW"; 104 }; 105 106 reg_vref_1v8: regulator-adc-vref { 107 compatible = "regulator-fixed"; 108 regulator-name = "vref_1v8"; 109 regulator-min-microvolt = <1800000>; 110 regulator-max-microvolt = <1800000>; 111 }; 112 113 reg_usdhc2_vmmc: regulator-usdhc2 { 114 compatible = "regulator-fixed"; 115 pinctrl-names = "default"; 116 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 117 regulator-name = "VDD_SD2_3V3"; 118 regulator-min-microvolt = <3300000>; 119 regulator-max-microvolt = <3300000>; 120 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 121 enable-active-high; 122 off-on-delay-us = <12000>; 123 }; 124 125 reg_usb_vbus: regulator-vbus { 126 compatible = "regulator-fixed"; 127 regulator-name = "USB_VBUS"; 128 regulator-min-microvolt = <5000000>; 129 regulator-max-microvolt = <5000000>; 130 gpio = <&pcal6524 3 GPIO_ACTIVE_HIGH>; 131 enable-active-high; 132 }; 133 134}; 135 136/* pin conflict with PDM */ 137&flexcan1 { 138 pinctrl-names = "default"; 139 pinctrl-0 = <&pinctrl_flexcan1>; 140 phys = <&flexcan1_phy>; 141 status = "disabled"; 142}; 143 144&flexcan2 { 145 pinctrl-names = "default"; 146 pinctrl-0 = <&pinctrl_flexcan2>; 147 phys = <&flexcan2_phy>; 148 status = "okay"; 149}; 150 151&lpi2c2 { 152 clock-frequency = <400000>; 153 pinctrl-names = "default"; 154 pinctrl-0 = <&pinctrl_lpi2c2>; 155 status = "okay"; 156 157 adp5585: io-expander@34 { 158 compatible = "adi,adp5585-00", "adi,adp5585"; 159 reg = <0x34>; 160 gpio-controller; 161 #gpio-cells = <2>; 162 gpio-reserved-ranges = <5 1>; 163 #pwm-cells = <3>; 164 }; 165}; 166 167&lpi2c3 { 168 clock-frequency = <400000>; 169 pinctrl-names = "default"; 170 pinctrl-0 = <&pinctrl_lpi2c3>; 171 status = "okay"; 172 173 i2c3_pcal6408: gpio@20 { 174 compatible = "nxp,pcal6408"; 175 reg = <0x20>; 176 #gpio-cells = <2>; 177 gpio-controller; 178 vcc-supply = <®_3p3v>; 179 }; 180}; 181 182&lpi2c4 { 183 clock-frequency = <400000>; 184 pinctrl-names = "default"; 185 pinctrl-0 = <&pinctrl_lpi2c4>; 186 status = "okay"; 187 188 i2c4_pcal6408: gpio@21 { 189 compatible = "nxp,pcal6408"; 190 reg = <0x21>; 191 #gpio-cells = <2>; 192 gpio-controller; 193 interrupt-controller; 194 #interrupt-cells = <2>; 195 interrupt-parent = <&gpio2>; 196 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 197 pinctrl-names = "default"; 198 pinctrl-0 = <&pinctrl_i2c4_pcal6408>; 199 vcc-supply = <®_3p3v>; 200 }; 201}; 202 203&lpi2c6 { 204 clock-frequency = <100000>; 205 pinctrl-names = "default"; 206 pinctrl-0 = <&pinctrl_lpi2c6>; 207 status = "okay"; 208 209 pcal6416: gpio@21 { 210 compatible = "nxp,pcal6416"; 211 #gpio-cells = <2>; 212 gpio-controller; 213 reg = <0x21>; 214 interrupt-controller; 215 #interrupt-cells = <2>; 216 interrupt-parent = <&gpio2>; 217 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 218 pinctrl-names = "default"; 219 pinctrl-0 = <&pinctrl_pcal6416>; 220 vcc-supply = <®_3p3v>; 221 222 pdm-can-sel-hog { 223 gpio-hog; 224 gpios = <10 GPIO_ACTIVE_HIGH>; 225 output-low; 226 }; 227 228 mqs-en-hog { 229 gpio-hog; 230 gpios = <15 GPIO_ACTIVE_HIGH>; 231 output-low; 232 }; 233 }; 234}; 235 236&lpi2c7 { 237 clock-frequency = <1000000>; 238 pinctrl-names = "default"; 239 pinctrl-0 = <&pinctrl_lpi2c7>; 240 status = "okay"; 241 242 pcal6524: gpio@22 { 243 compatible = "nxp,pcal6524"; 244 reg = <0x22>; 245 pinctrl-names = "default"; 246 pinctrl-0 = <&pinctrl_pcal6524>; 247 gpio-controller; 248 #gpio-cells = <2>; 249 interrupt-controller; 250 #interrupt-cells = <2>; 251 interrupt-parent = <&gpio5>; 252 interrupts = <16 IRQ_TYPE_LEVEL_LOW>; 253 }; 254 255 ptn5110: tcpc@50 { 256 compatible = "nxp,ptn5110", "tcpci"; 257 reg = <0x50>; 258 interrupt-parent = <&gpio5>; 259 interrupts = <14 IRQ_TYPE_LEVEL_LOW>; 260 pinctrl-names = "default"; 261 pinctrl-0 = <&pinctrl_ptn5110>; 262 263 typec_con: connector { 264 compatible = "usb-c-connector"; 265 label = "USB-C"; 266 power-role = "dual"; 267 data-role = "dual"; 268 try-power-role = "sink"; 269 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 270 sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>; 271 op-sink-microwatt = <0>; 272 self-powered; 273 274 ports { 275 #address-cells = <1>; 276 #size-cells = <0>; 277 278 port@0 { 279 reg = <0>; 280 281 typec1_dr_sw: endpoint { 282 remote-endpoint = <&usb1_drd_sw>; 283 }; 284 }; 285 }; 286 }; 287 }; 288}; 289 290&lpuart1 { 291 /* console */ 292 pinctrl-names = "default"; 293 pinctrl-0 = <&pinctrl_uart1>; 294 status = "okay"; 295}; 296 297&lpuart5 { 298 /* BT */ 299 pinctrl-names = "default"; 300 pinctrl-0 = <&pinctrl_uart5>; 301 status = "okay"; 302 303 bluetooth { 304 compatible = "nxp,88w8987-bt"; 305 }; 306}; 307 308&lpspi7 { 309 cs-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; 310 pinctrl-names = "default"; 311 pinctrl-0 = <&pinctrl_lpspi7>; 312 status = "okay"; 313}; 314 315&scmi_misc { 316 nxp,ctrl-ids = <BRD_SM_CTRL_SD3_WAKE 1 317 BRD_SM_CTRL_M2E_WAKE 1 318 BRD_SM_CTRL_BT_WAKE 1 319 BRD_SM_CTRL_M2M_WAKE 1 320 BRD_SM_CTRL_BUTTON 1>; 321}; 322 323&tpm3 { 324 pinctrl-names = "default"; 325 pinctrl-0 = <&pinctrl_tpm3>; 326 status = "okay"; 327}; 328 329&tpm6 { 330 pinctrl-names = "default"; 331 pinctrl-0 = <&pinctrl_tpm6>; 332 status = "okay"; 333}; 334 335&usb1 { 336 dr_mode = "otg"; 337 hnp-disable; 338 srp-disable; 339 adp-disable; 340 usb-role-switch; 341 disable-over-current; 342 samsung,picophy-pre-emp-curr-control = <3>; 343 samsung,picophy-dc-vol-level-adjust = <7>; 344 status = "okay"; 345 346 port { 347 usb1_drd_sw: endpoint { 348 remote-endpoint = <&typec1_dr_sw>; 349 }; 350 }; 351}; 352 353&usb2 { 354 dr_mode = "host"; 355 disable-over-current; 356 vbus-supply = <®_usb_vbus>; 357 status = "okay"; 358}; 359 360&usdhc1 { 361 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 362 pinctrl-0 = <&pinctrl_usdhc1>; 363 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 364 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 365 pinctrl-3 = <&pinctrl_usdhc1>; 366 bus-width = <8>; 367 non-removable; 368 no-sdio; 369 no-sd; 370 status = "okay"; 371}; 372 373&usdhc2 { 374 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 375 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 376 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 377 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 378 pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 379 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 380 vmmc-supply = <®_usdhc2_vmmc>; 381 bus-width = <4>; 382 status = "okay"; 383}; 384 385&wdog3 { 386 fsl,ext-reset-output; 387 status = "okay"; 388}; 389 390&scmi_iomuxc { 391 pinctrl_flexcan1: flexcan1grp { 392 fsl,pins = < 393 IMX952_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e 394 IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e 395 >; 396 }; 397 398 pinctrl_flexcan2: flexcan2grp { 399 fsl,pins = < 400 IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_CAN2_TX 0x39e 401 IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_CAN2_RX 0x39e 402 >; 403 }; 404 405 pinctrl_lpi2c2: lpi2c2grp { 406 fsl,pins = < 407 IMX952_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e 408 IMX952_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e 409 >; 410 }; 411 412 pinctrl_lpi2c3: lpi2c3grp { 413 fsl,pins = < 414 IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPI2C3_SDA 0x40000b9e 415 IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPI2C3_SCL 0x40000b9e 416 >; 417 }; 418 419 pinctrl_lpi2c4: lpi2c4grp { 420 fsl,pins = < 421 IMX952_PAD_GPIO_IO30__WAKEUPMIX_TOP_LPI2C4_SDA 0x40000b9e 422 IMX952_PAD_GPIO_IO31__WAKEUPMIX_TOP_LPI2C4_SCL 0x40000b9e 423 >; 424 }; 425 426 pinctrl_i2c4_pcal6408: i2c4pcal6408grp { 427 fsl,pins = < 428 IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_GPIO2_IO_18 0x31e 429 >; 430 }; 431 432 pinctrl_lpi2c6: lpi2c6grp { 433 fsl,pins = < 434 IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPI2C6_SDA 0x40000b9e 435 IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPI2C6_SCL 0x40000b9e 436 >; 437 }; 438 439 pinctrl_lpi2c7: lpi2c7grp { 440 fsl,pins = < 441 IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_LPI2C7_SDA 0x40000b9e 442 IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_LPI2C7_SCL 0x40000b9e 443 >; 444 }; 445 446 pinctrl_lpspi7: lpspi7grp { 447 fsl,pins = < 448 IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_GPIO2_IO_4 0x39e 449 IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_LPSPI7_SIN 0x39e 450 IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_LPSPI7_SOUT 0x39e 451 IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPSPI7_SCK 0x39e 452 >; 453 }; 454 455 pinctrl_pcal6416: pcal6416grp { 456 fsl,pins = < 457 IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_GPIO2_IO_10 0x31e 458 >; 459 }; 460 461 pinctrl_pcal6524: pcal6524grp { 462 fsl,pins = < 463 IMX952_PAD_GPIO_IO36__WAKEUPMIX_TOP_GPIO5_IO_16 0x31e 464 >; 465 }; 466 467 pinctrl_ptn5110: ptn5110grp { 468 fsl,pins = < 469 IMX952_PAD_GPIO_IO34__WAKEUPMIX_TOP_GPIO5_IO_14 0x31e 470 >; 471 }; 472 473 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 474 fsl,pins = < 475 IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_GPIO3_IO_7 0x31e 476 >; 477 }; 478 479 pinctrl_tpm3: tpm3grp { 480 fsl,pins = < 481 IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_TPM3_CH2 0x51e 482 >; 483 }; 484 485 pinctrl_tpm6: tpm6grp { 486 fsl,pins = < 487 IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_TPM6_CH2 0x51e 488 >; 489 }; 490 491 pinctrl_uart1: uart1grp { 492 fsl,pins = < 493 IMX952_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e 494 IMX952_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e 495 >; 496 }; 497 498 pinctrl_uart5: uart5grp { 499 fsl,pins = < 500 IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_LPUART5_TX 0x31e 501 IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_LPUART5_RX 0x31e 502 IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_LPUART5_RTS_B 0x31e 503 IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_LPUART5_CTS_B 0x31e 504 >; 505 }; 506 507 pinctrl_usdhc1: usdhc1grp { 508 fsl,pins = < 509 IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x158e 510 IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x138e 511 IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x138e 512 IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x138e 513 IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x138e 514 IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x138e 515 IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x138e 516 IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x138e 517 IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x138e 518 IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x138e 519 IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x158e 520 >; 521 }; 522 523 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 524 fsl,pins = < 525 IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x158e 526 IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x138e 527 IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x138e 528 IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x138e 529 IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x138e 530 IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x138e 531 IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x138e 532 IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x138e 533 IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x138e 534 IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x138e 535 IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x158e 536 >; 537 }; 538 539 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 540 fsl,pins = < 541 IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x159e 542 IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x139e 543 IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x139e 544 IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x139e 545 IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x139e 546 IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x139e 547 IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x139e 548 IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x139e 549 IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x139e 550 IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x139e 551 IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x159e 552 >; 553 }; 554 555 pinctrl_usdhc2: usdhc2grp { 556 fsl,pins = < 557 IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e 558 IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e 559 IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e 560 IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e 561 IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e 562 IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e 563 IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e 564 >; 565 }; 566 567 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 568 fsl,pins = < 569 IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e 570 IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e 571 IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e 572 IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e 573 IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e 574 IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e 575 IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e 576 >; 577 }; 578 579 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 580 fsl,pins = < 581 IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e 582 IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e 583 IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e 584 IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e 585 IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e 586 IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e 587 IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e 588 >; 589 }; 590 591 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 592 fsl,pins = < 593 IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_GPIO3_IO_0 0x31e 594 >; 595 }; 596}; 597