1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ 2 /* 3 * Copyright 2025 NXP 4 */ 5 6 #ifndef __CLOCK_IMX952_H__ 7 #define __CLOCK_IMX952_H__ 8 9 /* Clock Source */ 10 #define IMX952_CLK_EXT 0 11 #define IMX952_CLK_OSC32K 1 12 #define IMX952_CLK_OSC24M 2 13 #define IMX952_CLK_FRO 3 14 #define IMX952_CLK_SYSPLL1_VCO 4 15 #define IMX952_CLK_SYSPLL1_PFD0_UNGATED 5 16 #define IMX952_CLK_SYSPLL1_PFD0 6 17 #define IMX952_CLK_SYSPLL1_PFD0_DIV2 7 18 #define IMX952_CLK_SYSPLL1_PFD1_UNGATED 8 19 #define IMX952_CLK_SYSPLL1_PFD1 9 20 #define IMX952_CLK_SYSPLL1_PFD1_DIV2 10 21 #define IMX952_CLK_SYSPLL1_PFD2_UNGATED 11 22 #define IMX952_CLK_SYSPLL1_PFD2 12 23 #define IMX952_CLK_SYSPLL1_PFD2_DIV2 13 24 #define IMX952_CLK_AUDIOPLL1_VCO 14 25 #define IMX952_CLK_AUDIOPLL1 15 26 #define IMX952_CLK_AUDIOPLL2_VCO 16 27 #define IMX952_CLK_AUDIOPLL2 17 28 #define IMX952_CLK_VIDEOPLL1_VCO 18 29 #define IMX952_CLK_VIDEOPLL1 19 30 #define IMX952_CLK_SRC_RESERVED20 20 31 #define IMX952_CLK_SYSPLL1_PFD3_UNGATED 21 32 #define IMX952_CLK_SYSPLL1_PFD3 22 33 #define IMX952_CLK_SYSPLL1_PFD3_DIV2 23 34 #define IMX952_CLK_ARMPLL_VCO 24 35 #define IMX952_CLK_ARMPLL_PFD0_UNGATED 25 36 #define IMX952_CLK_ARMPLL_PFD0 26 37 #define IMX952_CLK_ARMPLL_PFD1_UNGATED 27 38 #define IMX952_CLK_ARMPLL_PFD1 28 39 #define IMX952_CLK_ARMPLL_PFD2_UNGATED 29 40 #define IMX952_CLK_ARMPLL_PFD2 30 41 #define IMX952_CLK_ARMPLL_PFD3_UNGATED 31 42 #define IMX952_CLK_ARMPLL_PFD3 32 43 #define IMX952_CLK_DRAMPLL_VCO 33 44 #define IMX952_CLK_DRAMPLL 34 45 #define IMX952_CLK_HSIOPLL_VCO 35 46 #define IMX952_CLK_HSIOPLL 36 47 #define IMX952_CLK_LDBPLL_VCO 37 48 #define IMX952_CLK_LDBPLL 38 49 #define IMX952_CLK_EXT1 39 50 #define IMX952_CLK_EXT2 40 51 52 /* Clock ROOT */ 53 #define IMX952_CLK_ADC 41 54 #define IMX952_CLK_RESERVED1 42 55 #define IMX952_CLK_BUSAON 43 56 #define IMX952_CLK_CAN1 44 57 #define IMX952_CLK_RESERVED4 45 58 #define IMX952_CLK_I3C1SLOW 46 59 #define IMX952_CLK_LPI2C1 47 60 #define IMX952_CLK_LPI2C2 48 61 #define IMX952_CLK_LPSPI1 49 62 #define IMX952_CLK_LPSPI2 50 63 #define IMX952_CLK_LPTMR1 51 64 #define IMX952_CLK_LPUART1 52 65 #define IMX952_CLK_LPUART2 53 66 #define IMX952_CLK_M33 54 67 #define IMX952_CLK_M33SYSTICK 55 68 #define IMX952_CLK_RESERVED15 56 69 #define IMX952_CLK_PDM 57 70 #define IMX952_CLK_SAI1 58 71 #define IMX952_CLK_RESERVED18 59 72 #define IMX952_CLK_TPM2 60 73 #define IMX952_CLK_RESERVED20 61 74 #define IMX952_CLK_CAMAPB 62 75 #define IMX952_CLK_CAMAXI 63 76 #define IMX952_CLK_CAMCM0 64 77 #define IMX952_CLK_CAMISI 65 78 #define IMX952_CLK_CAMPHYCFG 66 79 #define IMX952_CLK_MIPIPHYPLLBYPASS 67 80 #define IMX952_CLK_RESERVED27 68 81 #define IMX952_CLK_MIPITESTBYTE 69 82 #define IMX952_CLK_A55 70 83 #define IMX952_CLK_A55MTRBUS 71 84 #define IMX952_CLK_A55PERIPH 72 85 #define IMX952_CLK_DRAMALT 73 86 #define IMX952_CLK_DRAMAPB 74 87 #define IMX952_CLK_DISPAPB 75 88 #define IMX952_CLK_DISPAXI 76 89 #define IMX952_CLK_DISPLPSPI 77 90 #define IMX952_CLK_DISPOCRAM 78 91 #define IMX952_CLK_DISPPHYCFG 79 92 #define IMX952_CLK_DISP1PIX 80 93 #define IMX952_CLK_DISPCDPHYAPB 81 94 #define IMX952_CLK_RESERVED41 82 95 #define IMX952_CLK_GPUAPB 83 96 #define IMX952_CLK_GPU 84 97 #define IMX952_CLK_HSIOACSCAN480M 85 98 #define IMX952_CLK_HSIOACSCAN80M 86 99 #define IMX952_CLK_HSIO 87 100 #define IMX952_CLK_HSIOPCIEAUX 88 101 #define IMX952_CLK_HSIOPCIETEST160M 89 102 #define IMX952_CLK_HSIOPCIETEST400M 90 103 #define IMX952_CLK_HSIOPCIETEST500M 91 104 #define IMX952_CLK_HSIOUSBTEST50M 92 105 #define IMX952_CLK_HSIOUSBTEST60M 93 106 #define IMX952_CLK_BUSM7 94 107 #define IMX952_CLK_M7 95 108 #define IMX952_CLK_M7SYSTICK 96 109 #define IMX952_CLK_BUSNETCMIX 97 110 #define IMX952_CLK_ENET 98 111 #define IMX952_CLK_ENETPHYTEST200M 99 112 #define IMX952_CLK_ENETPHYTEST500M 100 113 #define IMX952_CLK_ENETPHYTEST667M 101 114 #define IMX952_CLK_ENETREF 102 115 #define IMX952_CLK_ENETTIMER1 103 116 #define IMX952_CLK_RESERVED63 104 117 #define IMX952_CLK_SAI2 105 118 #define IMX952_CLK_NOCAPB 106 119 #define IMX952_CLK_NOC 107 120 #define IMX952_CLK_NPUAPB 108 121 #define IMX952_CLK_NPU 109 122 #define IMX952_CLK_CCMCKO1 110 123 #define IMX952_CLK_CCMCKO2 111 124 #define IMX952_CLK_CCMCKO3 112 125 #define IMX952_CLK_CCMCKO4 113 126 #define IMX952_CLK_VPUAPB 114 127 #define IMX952_CLK_VPU 115 128 #define IMX952_CLK_RESERVED75 116 129 #define IMX952_CLK_RESERVED76 117 130 #define IMX952_CLK_AUDIOXCVR 118 131 #define IMX952_CLK_BUSWAKEUP 119 132 #define IMX952_CLK_CAN2 120 133 #define IMX952_CLK_CAN3 121 134 #define IMX952_CLK_CAN4 122 135 #define IMX952_CLK_CAN5 123 136 #define IMX952_CLK_FLEXIO1 124 137 #define IMX952_CLK_FLEXIO2 125 138 #define IMX952_CLK_XSPI1 126 139 #define IMX952_CLK_RESERVED86 127 140 #define IMX952_CLK_I3C2SLOW 128 141 #define IMX952_CLK_LPI2C3 129 142 #define IMX952_CLK_LPI2C4 130 143 #define IMX952_CLK_LPI2C5 131 144 #define IMX952_CLK_LPI2C6 132 145 #define IMX952_CLK_LPI2C7 133 146 #define IMX952_CLK_LPI2C8 134 147 #define IMX952_CLK_LPSPI3 135 148 #define IMX952_CLK_LPSPI4 136 149 #define IMX952_CLK_LPSPI5 137 150 #define IMX952_CLK_LPSPI6 138 151 #define IMX952_CLK_LPSPI7 139 152 #define IMX952_CLK_LPSPI8 140 153 #define IMX952_CLK_LPTMR2 141 154 #define IMX952_CLK_LPUART3 142 155 #define IMX952_CLK_LPUART4 143 156 #define IMX952_CLK_LPUART5 144 157 #define IMX952_CLK_LPUART6 145 158 #define IMX952_CLK_LPUART7 146 159 #define IMX952_CLK_LPUART8 147 160 #define IMX952_CLK_SAI3 148 161 #define IMX952_CLK_SAI4 149 162 #define IMX952_CLK_SAI5 150 163 #define IMX952_CLK_SPDIF 151 164 #define IMX952_CLK_SWOTRACE 152 165 #define IMX952_CLK_TPM4 153 166 #define IMX952_CLK_TPM5 154 167 #define IMX952_CLK_TPM6 155 168 #define IMX952_CLK_MIPIPHYDFT400 156 169 #define IMX952_CLK_MIPIPHYDFT540 157 170 #define IMX952_CLK_USDHC1 158 171 #define IMX952_CLK_USDHC2 159 172 #define IMX952_CLK_USDHC3 160 173 #define IMX952_CLK_V2XPK 161 174 #define IMX952_CLK_WAKEUPAXI 162 175 #define IMX952_CLK_XSPISLVROOT 163 176 #define IMX952_CLK_AUDMIX1 164 177 #define IMX952_CLK_ASRC1 165 178 #define IMX952_CLK_ASRC2 166 179 #define IMX952_CLK_GPT1 167 180 #define IMX952_CLK_GPT2 168 181 #define IMX952_CLK_GPT3 169 182 #define IMX952_CLK_GPT4 170 183 184 /* Clock GPR SEL */ 185 #define IMX952_CLK_GPR_SEL_EXT 171 186 #define IMX952_CLK_GPR_SEL_A55C0 172 187 #define IMX952_CLK_GPR_SEL_A55C1 173 188 #define IMX952_CLK_GPR_SEL_A55C2 174 189 #define IMX952_CLK_GPR_SEL_A55C3 175 190 #define IMX952_CLK_GPR_SEL_A55P 176 191 #define IMX952_CLK_GPR_SEL_DRAM 177 192 #define IMX952_CLK_GPR_SEL_TEMPSENSE 178 193 194 /* Clock CGC */ 195 #define IMX952_CLK_CGC_NPU 179 196 #define IMX952_CLK_CGC_GPU 180 197 #define IMX952_CLK_CGC_CAMISI 181 198 #define IMX952_CLK_CGC_CAMISP 182 199 #define IMX952_CLK_CGC_CAMCSI0 183 200 #define IMX952_CLK_CGC_CAMCSI1 184 201 #define IMX952_CLK_CGC_CAMOCRAM 185 202 #define IMX952_CLK_CGC_HSIOUSB 186 203 #define IMX952_CLK_CGC_HSIOPCIE 187 204 #define IMX952_CLK_CGC_DISPOCRAM 188 205 #define IMX952_CLK_CGC_DISPSEERIS 189 206 #define IMX952_CLK_CGC_DISPDSI 190 207 #define IMX952_CLK_CGC_NOCGIC 191 208 #define IMX952_CLK_CGC_NOCOCRAM 192 209 #define IMX952_CLK_CGC_NETC 193 210 #define IMX952_CLK_CGC_VPUENC 194 211 #define IMX952_CLK_CGC_VPUJPEGENC 195 212 #define IMX952_CLK_CGC_VPUJPEGDEC 196 213 #define IMX952_CLK_CGC_VPUDEC 197 214 215 #endif 216