1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright (c) Toradex 4 * 5 * Common dtsi for Verdin iMX95 SoM 6 * 7 * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 8 */ 9 10#include <dt-bindings/net/ti-dp83867.h> 11#include "imx95.dtsi" 12 13/ { 14 aliases { 15 can0 = &flexcan1; 16 can1 = &flexcan2; 17 eeprom0 = &som_eeprom; 18 ethernet0 = &enetc_port0; 19 ethernet1 = &enetc_port1; 20 i2c0 = &lpi2c2; 21 i2c1 = &lpi2c4; 22 i2c2 = &lpi2c3; 23 i2c3 = &i3c2; 24 i2c4 = &lpi2c5; 25 mmc0 = &usdhc1; 26 mmc1 = &usdhc2; 27 mmc2 = &usdhc3; 28 rtc0 = &rtc_i2c; 29 rtc1 = &scmi_bbm; 30 serial0 = &lpuart7; 31 serial1 = &lpuart8; 32 serial2 = &lpuart1; 33 serial3 = &lpuart2; 34 serial4 = &lpuart6; 35 usb0 = &usb2; 36 usb1 = &usb3; 37 }; 38 39 chosen { 40 stdout-path = "serial2:115200n8"; 41 }; 42 43 connector { 44 compatible = "gpio-usb-b-connector", "usb-b-connector"; 45 /* Verdin USB_1_ID (SODIMM 161) */ 46 id-gpios = <&som_gpio_expander 5 GPIO_ACTIVE_HIGH>; 47 label = "USB_1"; 48 self-powered; 49 vbus-supply = <®_usb1_vbus>; 50 51 port { 52 usb_dr_connector: endpoint { 53 remote-endpoint = <&usb1_id>; 54 }; 55 }; 56 }; 57 58 verdin_gpio_keys: gpio-keys { 59 compatible = "gpio-keys"; 60 pinctrl-names = "default"; 61 pinctrl-0 = <&pinctrl_ctrl_wake1_mico>; 62 63 status = "disabled"; 64 65 verdin_key_wakeup: key-wakeup { 66 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ 67 gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; 68 label = "Wake-Up"; 69 linux,code = <KEY_WAKEUP>; 70 wakeup-source; 71 }; 72 }; 73 74 reg_1p8v: regulator-1p8v { 75 compatible = "regulator-fixed"; 76 regulator-max-microvolt = <1800000>; 77 regulator-min-microvolt = <1800000>; 78 regulator-name = "On-module +V1.8"; 79 }; 80 81 /* 82 * By default we enable CTRL_SLEEP_MOCI#, this is required to have 83 * peripherals on the carrier board powered. 84 * If more granularity or power saving is required this can be disabled 85 * in the carrier board device tree files. 86 */ 87 reg_force_sleep_moci: regulator-force-sleep-moci { 88 compatible = "regulator-fixed"; 89 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ 90 gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; 91 enable-active-high; 92 regulator-always-on; 93 regulator-boot-on; 94 regulator-name = "CTRL_SLEEP_MOCI#"; 95 }; 96 97 reg_usb1_vbus: regulator-usb1-vbus { 98 compatible = "regulator-fixed"; 99 /* Verdin USB_1_EN (SODIMM 155) */ 100 gpios = <&som_gpio_expander 7 GPIO_ACTIVE_HIGH>; 101 enable-active-high; 102 regulator-name = "USB_1_EN"; 103 }; 104 105 reg_usb2_vbus: regulator-usb2-vbus { 106 compatible = "regulator-fixed"; 107 /* Verdin USB_2_EN (SODIMM 185) */ 108 gpios = <&som_gpio_expander 8 GPIO_ACTIVE_HIGH>; 109 enable-active-high; 110 regulator-name = "USB_2_EN"; 111 }; 112 113 reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { 114 compatible = "regulator-gpio"; 115 pinctrl-names = "default"; 116 pinctrl-0 = <&pinctrl_usdhc2_vsel>; 117 gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; 118 regulator-max-microvolt = <3300000>; 119 regulator-min-microvolt = <1800000>; 120 states = <1800000 0x1>, 121 <3300000 0x0>; 122 regulator-name = "PMIC_SD2_VSEL"; 123 }; 124 125 reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { 126 compatible = "regulator-fixed"; 127 pinctrl-names = "default"; 128 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; 129 /* Verdin SD_1_PWR_EN (SODIMM 76) */ 130 gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; 131 enable-active-high; 132 off-on-delay-us = <100000>; 133 regulator-max-microvolt = <3300000>; 134 regulator-min-microvolt = <3300000>; 135 regulator-name = "SD_1_PWR_EN"; 136 startup-delay-us = <20000>; 137 }; 138 139 cm7: remoteproc-cm7 { 140 compatible = "fsl,imx95-cm7"; 141 mbox-names = "tx", "rx", "rxdb"; 142 mboxes = <&mu7 0 1 143 &mu7 1 1 144 &mu7 3 1>; 145 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 146 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>, <&m7_reserved>; 147 }; 148 149 reserved-memory { 150 #address-cells = <2>; 151 #size-cells = <2>; 152 ranges; 153 154 linux_cma: linux,cma { 155 compatible = "shared-dma-pool"; 156 reusable; 157 size = <0 0x3c000000>; 158 alloc-ranges = <0 0x80000000 0 0x7F000000>; 159 linux,cma-default; 160 }; 161 162 m7_reserved: memory@80000000 { 163 reg = <0 0x80000000 0 0x1000000>; 164 no-map; 165 }; 166 167 vdev0vring0: vdev0vring0@88000000 { 168 reg = <0 0x88000000 0 0x8000>; 169 no-map; 170 }; 171 172 vdev0vring1: vdev0vring1@88008000 { 173 reg = <0 0x88008000 0 0x8000>; 174 no-map; 175 }; 176 177 vdev1vring0: vdev1vring0@88010000 { 178 reg = <0 0x88010000 0 0x8000>; 179 no-map; 180 }; 181 182 vdev1vring1: vdev1vring1@88018000 { 183 reg = <0 0x88018000 0 0x8000>; 184 no-map; 185 }; 186 187 vdevbuffer: vdevbuffer@88020000 { 188 compatible = "shared-dma-pool"; 189 reg = <0 0x88020000 0 0x100000>; 190 no-map; 191 }; 192 193 rsc_table: rsc-table@88220000 { 194 reg = <0 0x88220000 0 0x1000>; 195 no-map; 196 }; 197 }; 198}; 199 200/* Verdin ADC_1, ADC_2, ADC_3 and ADC_4 */ 201&adc1 { 202 vref-supply = <®_1p8v>; 203}; 204 205/* Verdin ETH_1 (On-module PHY) */ 206&enetc_port0 { 207 pinctrl-names = "default"; 208 pinctrl-0 = <&pinctrl_enetc0>; 209 phy-handle = <ðphy1>; 210 phy-mode = "rgmii-id"; 211}; 212 213/* Verdin ETH_2_RGMII */ 214&enetc_port1 { 215 pinctrl-names = "default"; 216 pinctrl-0 = <&pinctrl_enetc1>; 217}; 218 219/* Verdin CAN_1 */ 220&flexcan1 { 221 pinctrl-names = "default"; 222 pinctrl-0 = <&pinctrl_flexcan1>; 223}; 224 225/* Verdin CAN_2 */ 226&flexcan2 { 227 pinctrl-names = "default"; 228 pinctrl-0 = <&pinctrl_flexcan2>; 229}; 230 231/* Verdin QSPI_1 */ 232&flexspi1 { 233 pinctrl-names = "default"; 234 pinctrl-0 = <&pinctrl_flexspi1>; 235}; 236 237&gpio1 { 238 gpio-line-names = 239 "", /* 0 */ 240 "", 241 "", 242 "", 243 "SODIMM_147", 244 "SODIMM_149", 245 "SODIMM_151", 246 "SODIMM_153", 247 "SODIMM_20", 248 "SODIMM_22", 249 "SODIMM_252", /* 10 */ 250 "", 251 "SODIMM_189", 252 "IO_EXP_INT", 253 "SODIMM_256", 254 ""; 255 256 status = "okay"; 257}; 258 259&gpio2 { 260 gpio-line-names = 261 "SODIMM_206", /* 0 */ 262 "SODIMM_198", 263 "SODIMM_200", 264 "SODIMM_196", 265 "", 266 "SODIMM_15", 267 "SODIMM_16", 268 "", 269 "SODIMM_131", 270 "SODIMM_129", 271 "SODIMM_135", /* 10 */ 272 "SODIMM_133", 273 "SODIMM_139", 274 "SODIMM_137", 275 "SODIMM_143", 276 "SODIMM_141", 277 "SODIMM_30", 278 "SODIMM_38", 279 "SODIMM_208", 280 "SODIMM_19", 281 "SODIMM_36", /* 20 */ 282 "SODIMM_34", 283 "SODIMM_93", 284 "SODIMM_95", 285 "SODIMM_210", 286 "SODIMM_24", 287 "SODIMM_32", 288 "SODIMM_26", 289 "SODIMM_53", 290 "SODIMM_55", 291 "SODIMM_12", /* 30 */ 292 "SODIMM_14"; 293}; 294 295&gpio3 { 296 gpio-line-names = 297 "SODIMM_84", /* 0 */ 298 "SODIMM_78", 299 "SODIMM_74", 300 "SODIMM_80", 301 "SODIMM_82", 302 "SODIMM_70", 303 "SODIMM_72", 304 "SODIMM_76", 305 "", 306 "", 307 "", /* 10 */ 308 "", 309 "", 310 "", 311 "", 312 "", 313 "", 314 "", 315 "", 316 "PMIC_SD2_VSEL", 317 "", /* 20 */ 318 "", 319 "", 320 "", 321 "", 322 "", 323 "SODIMM_91", 324 "SODIMM_218", 325 "", 326 "", 327 "", /* 30 */ 328 ""; 329}; 330 331&gpio4 { 332 gpio-line-names = 333 "SODIMM_59", /* 0 */ 334 "SODIMM_57", 335 "", 336 "", 337 "", 338 "", 339 "", 340 "", 341 "", 342 "", 343 "", /* 10 */ 344 "", 345 "", 346 "", 347 "SODIMM_193", 348 "SODIMM_191", 349 "SODIMM_215", 350 "SODIMM_217", 351 "SODIMM_219", 352 "SODIMM_221", 353 "SODIMM_211", /* 20 */ 354 "SODIMM_213", 355 "SODIMM_199", 356 "SODIMM_197", 357 "SODIMM_201", 358 "SODIMM_203", 359 "SODIMM_205", 360 "SODIMM_207", 361 "SODIMM_216", 362 "SODIMM_202"; 363}; 364 365&gpio5 { 366 gpio-line-names = 367 "SODIMM_56", /* 0 */ 368 "SODIMM_58", 369 "SODIMM_60", 370 "SODIMM_62", 371 "SODIMM_46", 372 "SODIMM_44", 373 "SODIMM_42", 374 "SODIMM_48", 375 "SODIMM_66", 376 "SODIMM_52", 377 "SODIMM_54", /* 10 */ 378 "SODIMM_64", 379 "SODIMM_212", 380 "", 381 "", 382 "", 383 "", 384 ""; 385}; 386 387/* Verdin I2C_3_HDMI */ 388&i3c2 { 389 pinctrl-names = "default"; 390 pinctrl-0 = <&pinctrl_i3c2>; 391 i2c-scl-hz = <400000>; 392}; 393 394/* CTRL_I2C (On-module I2C) */ 395&lpi2c2 { 396 pinctrl-names = "default", "gpio"; 397 pinctrl-0 = <&pinctrl_lpi2c2>, <&pinctrl_io_exp_int>; 398 pinctrl-1 = <&pinctrl_lpi2c2_gpio>, <&pinctrl_io_exp_int>; 399 clock-frequency = <400000>; 400 scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 401 sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 402 single-master; 403 404 status = "okay"; 405 406 som_gpio_expander: gpio@20 { 407 compatible = "nxp,pcal6416"; 408 reg = <0x20>; 409 #interrupt-cells = <2>; 410 interrupt-controller; 411 interrupt-parent = <&gpio1>; 412 interrupts = <13 IRQ_TYPE_LEVEL_LOW>; 413 #gpio-cells = <2>; 414 gpio-controller; 415 416 gpio-line-names = 417 "SODIMM_220", /* 0 */ 418 "SODIMM_222", 419 "SODIMM_17", 420 "SODIMM_21", 421 "SODIMM_244", 422 "SODIMM_161", 423 "SODIMM_157", 424 "SODIMM_155", 425 "SODIMM_185", 426 "SODIMM_187", 427 "USB_RECOV_CTRL#", /* 10 */ 428 "ENET1_INT#", 429 "TPM_INT#", 430 "TPM_CS#", 431 "", 432 ""; 433 434 /* 435 * Switch USB to default position: 436 * - SoC USB2 -> Verdin USB_1 437 * - SoC USB1 -> Verdin USB_2 438 * Reset configuration: 439 * - SoC USB1 -> Verdin USB_1 (USB recovery) 440 * - SoC USB2 not connected 441 */ 442 usb_recov_ctrl: usb-recov-ctrl-hog { 443 gpio-hog; 444 gpios = <10 GPIO_ACTIVE_HIGH>; 445 line-name = "USB_RECOV_CTRL#"; 446 output-high; 447 }; 448 }; 449 450 rtc_i2c: rtc@32 { 451 compatible = "epson,rx8130"; 452 reg = <0x32>; 453 }; 454 455 temperature-sensor@48 { 456 compatible = "ti,tmp1075"; 457 reg = <0x48>; 458 }; 459 460 som_eeprom: eeprom@50 { 461 compatible = "st,24c02", "atmel,24c02"; 462 reg = <0x50>; 463 pagesize = <16>; 464 }; 465}; 466 467/* Verdin I2C_2_DSI */ 468&lpi2c3 { 469 pinctrl-names = "default", "gpio"; 470 pinctrl-0 = <&pinctrl_lpi2c3>; 471 pinctrl-1 = <&pinctrl_lpi2c3_gpio>; 472 clock-frequency = <100000>; 473 scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 474 sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 475 single-master; 476}; 477 478/* Verdin I2C_1 */ 479&lpi2c4 { 480 pinctrl-names = "default", "gpio"; 481 pinctrl-0 = <&pinctrl_lpi2c4>; 482 pinctrl-1 = <&pinctrl_lpi2c4_gpio>; 483 clock-frequency = <100000>; 484 scl-gpios = <&gpio2 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 485 sda-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 486 single-master; 487}; 488 489/* Verdin I2C_4_CSI */ 490&lpi2c5 { 491 pinctrl-names = "default", "gpio"; 492 pinctrl-0 = <&pinctrl_lpi2c5>; 493 pinctrl-1 = <&pinctrl_lpi2c5_gpio>; 494 clock-frequency = <100000>; 495 scl-gpios = <&gpio2 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 496 sda-gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 497 single-master; 498}; 499 500/* Verdin SPI_1 */ 501&lpspi6 { 502 pinctrl-names = "default"; 503 pinctrl-0 = <&pinctrl_lpspi6>, <&pinctrl_spi1_cs>; 504 cs-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>, 505 <&som_gpio_expander 13 GPIO_ACTIVE_LOW>; 506 507 status = "okay"; 508 509 som_tpm: tpm@1 { 510 compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; 511 reg = <0x1>; 512 interrupt-parent = <&som_gpio_expander>; 513 interrupts = <12 IRQ_TYPE_EDGE_FALLING>; 514 /* 515 * Maximum TPM-supported speed is 18.5 MHz, limited to 12 MHz 516 * here as lpspi6's per-clock (twice the max speed) is 24 MHz 517 */ 518 spi-max-frequency = <12000000>; 519 }; 520}; 521 522/* Verdin UART_3, used as the Linux console */ 523&lpuart1 { 524 pinctrl-names = "default"; 525 pinctrl-0 = <&pinctrl_uart1>; 526}; 527 528/* Verdin UART_4 */ 529&lpuart2 { 530 pinctrl-names = "default"; 531 pinctrl-0 = <&pinctrl_uart2>; 532}; 533 534/* Verdin UART_1 */ 535&lpuart7 { 536 pinctrl-names = "default"; 537 pinctrl-0 = <&pinctrl_uart7>; 538 uart-has-rtscts; 539}; 540 541/* Verdin UART_2 */ 542&lpuart8 { 543 pinctrl-names = "default"; 544 pinctrl-0 = <&pinctrl_uart8>; 545 uart-has-rtscts; 546}; 547 548&mu7 { 549 status = "okay"; 550}; 551 552&netc_blk_ctrl { 553 status = "okay"; 554}; 555 556&netc_bus0 { 557 msi-map = <0x0 &its 0x60 0x1>, //ENETC0 PF 558 <0x10 &its 0x61 0x1>, //ENETC0 VF0 559 <0x20 &its 0x62 0x1>, //ENETC0 VF1 560 <0x40 &its 0x63 0x1>, //ENETC1 PF 561 <0x50 &its 0x65 0x1>, //ENETC1 VF0 562 <0x60 &its 0x66 0x1>, //ENETC1 VF1 563 <0x80 &its 0x64 0x1>, //ENETC2 PF 564 <0xc0 &its 0x67 0x1>; //NETC Timer 565 iommu-map = <0x0 &smmu 0x20 0x1>, 566 <0x10 &smmu 0x21 0x1>, 567 <0x20 &smmu 0x22 0x1>, 568 <0x40 &smmu 0x23 0x1>, 569 <0x50 &smmu 0x25 0x1>, 570 <0x60 &smmu 0x26 0x1>, 571 <0x80 &smmu 0x24 0x1>, 572 <0xc0 &smmu 0x27 0x1>; 573}; 574 575/* Verdin ETH_2_RGMII_MDIO, shared between all ethernet ports */ 576&netc_emdio { 577 pinctrl-names = "default"; 578 pinctrl-0 = <&pinctrl_emdio>; 579 580 status = "okay"; 581 582 ethphy1: ethernet-phy@0 { 583 reg = <0>; 584 interrupt-parent = <&som_gpio_expander>; 585 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 586 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 587 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 588 }; 589}; 590 591&netc_timer { 592 status = "okay"; 593}; 594 595&netcmix_blk_ctrl { 596 status = "okay"; 597}; 598 599/* Verdin PCIE_1 */ 600&pcie0 { 601 /* PCIE_1_RESET# (SODIMM 244) */ 602 reset-gpios = <&som_gpio_expander 4 GPIO_ACTIVE_LOW>; 603}; 604 605/* Verdin I2S_1 */ 606&sai3 { 607 pinctrl-names = "default"; 608 pinctrl-0 = <&pinctrl_sai3>; 609 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 610 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 611 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 612 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 613 <&scmi_clk IMX95_CLK_SAI3>; 614 assigned-clock-parents = <0>, <0>, <0>, <0>, 615 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 616 assigned-clock-rates = <3932160000>, 617 <3612672000>, <393216000>, 618 <361267200>, <12288000>; 619 #sound-dai-cells = <0>; 620 fsl,sai-mclk-direction-output; 621}; 622 623&scmi_bbm { 624 linux,code = <KEY_POWER>; 625}; 626 627&thermal_zones { 628 /* PF09 Main PMIC */ 629 pf09-thermal { 630 polling-delay = <2000>; 631 polling-delay-passive = <250>; 632 thermal-sensors = <&scmi_sensor 2>; 633 634 trips { 635 trip0 { 636 hysteresis = <2000>; 637 temperature = <155000>; 638 type = "critical"; 639 }; 640 }; 641 }; 642 643 /* PF53 VDD_ARM PMIC */ 644 pf53-arm-thermal { 645 polling-delay = <2000>; 646 polling-delay-passive = <250>; 647 thermal-sensors = <&scmi_sensor 4>; 648 649 trips { 650 trip0 { 651 hysteresis = <2000>; 652 temperature = <155000>; 653 type = "critical"; 654 }; 655 }; 656 }; 657 658 /* PF53 VDD_SOC PMIC */ 659 pf53-soc-thermal { 660 polling-delay = <2000>; 661 polling-delay-passive = <250>; 662 thermal-sensors = <&scmi_sensor 3>; 663 664 trips { 665 trip0 { 666 hysteresis = <2000>; 667 temperature = <155000>; 668 type = "critical"; 669 }; 670 }; 671 }; 672}; 673 674/* Verdin PWM_1 */ 675&tpm4 { 676 pinctrl-names = "default"; 677 pinctrl-0 = <&pinctrl_tpm4>; 678}; 679 680/* Verdin PWM_2 */ 681&tpm5 { 682 pinctrl-names = "default"; 683 pinctrl-0 = <&pinctrl_tpm5>; 684}; 685 686/* Verdin PWM_3_DSI */ 687&tpm6 { 688 pinctrl-names = "default"; 689 pinctrl-0 = <&pinctrl_tpm6>; 690}; 691 692/* Verdin USB_1 */ 693&usb2 { 694 dr_mode = "otg"; 695 adp-disable; 696 hnp-disable; 697 srp-disable; 698 usb-role-switch; 699 vbus-supply = <®_usb1_vbus>; 700 701 port { 702 usb1_id: endpoint { 703 remote-endpoint = <&usb_dr_connector>; 704 }; 705 }; 706}; 707 708/* Verdin USB_2 */ 709&usb3 { 710 fsl,disable-port-power-control; 711}; 712 713&usb3_dwc3 { 714 dr_mode = "host"; 715}; 716 717&usb3_phy { 718 vbus-supply = <®_usb2_vbus>; 719}; 720 721/* On-module eMMC */ 722&usdhc1 { 723 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 724 pinctrl-0 = <&pinctrl_usdhc1>; 725 pinctrl-1 = <&pinctrl_usdhc1>; 726 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 727 bus-width = <8>; 728 non-removable; 729 no-sdio; 730 no-sd; 731 732 status = "okay"; 733}; 734 735/* Verdin SD_1 */ 736&usdhc2 { 737 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 738 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; 739 pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; 740 pinctrl-2 = <&pinctrl_usdhc2_200mhz>,<&pinctrl_usdhc2_cd>; 741 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd>; 742 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 743 vmmc-supply = <®_usdhc2_vmmc>; 744 vqmmc-supply = <®_usdhc2_vqmmc>; 745}; 746 747&wdog3 { 748 fsl,ext-reset-output; 749 750 status = "okay"; 751}; 752 753&scmi_iomuxc { 754 /* On-module Bluetooth on WB SKUs, module-specific UART otherwise */ 755 pinctrl_bt_uart: btuartgrp { 756 fsl,pins = <IMX95_PAD_GPIO_IO04__LPUART6_TX 0x31e>, /* WiFi_UART_SoC_TXD */ 757 <IMX95_PAD_GPIO_IO33__LPUART6_RX 0x31e>, /* WiFi_UART_SoC_RXD */ 758 <IMX95_PAD_GPIO_IO34__LPUART6_CTS_B 0x31e>, /* WiFi_UART_SoC_CTS */ 759 <IMX95_PAD_GPIO_IO07__LPUART6_RTS_B 0x31e>; /* WiFi_UART_SoC_RTS */ 760 }; 761 762 /* Verdin CSI_1_MCLK */ 763 pinctrl_csi1_mclk: csi1mclkgrp { 764 fsl,pins = <IMX95_PAD_CCM_CLKO1__CCMSRCGPCMIX_TOP_CLKO_1 0x51e>; /* SODIMM 91 */ 765 }; 766 767 /* Verdin CTRL_SLEEP_MOCI# */ 768 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { 769 fsl,pins = <IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14 0x51e>; /* SODIMM 256 */ 770 }; 771 772 /* Verdin CTRL_WAKE1_MICO# */ 773 pinctrl_ctrl_wake1_mico: ctrlwake1micogrp { 774 fsl,pins = <IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_BIT10 0x31e>; /* SODIMM 252 */ 775 }; 776 777 /* Verdin ETH_2_RGMII_MDIO, shared between all ethernet ports */ 778 pinctrl_emdio: emdiogrp { 779 fsl,pins = <IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x50e>, /* ENET2_MDC, SODIMM 193 */ 780 <IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e>; /* ENET2_MDIO, SODIMM 191 */ 781 }; 782 783 /* Verdin ETH_1 (On-module PHY) */ 784 pinctrl_enetc0: enetc0grp { 785 fsl,pins = <IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e>, /* ENET1_TX_CTL */ 786 <IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e>, /* ENET1_TXC */ 787 <IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e>, /* ENET1_TDO */ 788 <IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e>, /* ENET1_TD1 */ 789 <IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e>, /* ENET1_TD2 */ 790 <IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e>, /* ENET1_TD3 */ 791 <IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e>, /* ENET1_RX_CTL */ 792 <IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e>, /* ENET1_RXC */ 793 <IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e>, /* ENET1_RD0 */ 794 <IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e>, /* ENET1_RD1 */ 795 <IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e>, /* ENET1_RD2 */ 796 <IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e>; /* ENET1_RD3 */ 797 }; 798 799 /* Verdin ETH_2_RGMII */ 800 pinctrl_enetc1: enetc1grp { 801 fsl,pins = <IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e>, /* ENET2_TX_CTL */ 802 <IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x58e>, /* ENET2_TXC */ 803 <IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x50e>, /* ENET2_TD0 */ 804 <IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x50e>, /* ENET2_TD1 */ 805 <IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x50e>, /* ENET2_TD2 */ 806 <IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x50e>, /* ENET2_TD3 */ 807 <IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e>, /* ENET2_RX_CTL */ 808 <IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x58e>, /* ENET2_RXC */ 809 <IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e>, /* ENET2_RD0 */ 810 <IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e>, /* ENET2_RD1 */ 811 <IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e>, /* ENET2_RD2 */ 812 <IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x57e>; /* ENET2_RD3 */ 813 }; 814 815 /* Verdin ETH_2_RGMII_INT# */ 816 pinctrl_eth2_rgmii_int: eth2rgmiiintgrp { 817 fsl,pins = <IMX95_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_BIT12 0x31e>; /* SODIMM 189 */ 818 }; 819 820 /* Verdin CAN_1 */ 821 pinctrl_flexcan1: flexcan1grp { 822 fsl,pins = <IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e>, /* SODIMM 20 */ 823 <IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e>; /* SODIMM 22 */ 824 }; 825 826 /* Verdin CAN_2 */ 827 pinctrl_flexcan2: flexcan2grp { 828 fsl,pins = <IMX95_PAD_GPIO_IO25__CAN2_TX 0x39e>, /* SODIMM 24 */ 829 <IMX95_PAD_GPIO_IO27__CAN2_RX 0x39e>; /* SODIMM 26 */ 830 }; 831 832 /* Verdin QSPI_1 */ 833 pinctrl_flexspi1: flexspi1grp { 834 fsl,pins = <IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x3fe>, /* SODIMM 54 */ 835 <IMX95_PAD_XSPI1_SS1_B__FLEXSPI1_A_SS1_B 0x3fe>, /* SODIMM 64 */ 836 <IMX95_PAD_XSPI1_SCLK__XSPI_CLK 0x3fe>, /* SODIMM 52 */ 837 <IMX95_PAD_XSPI1_DATA0__XSPI_DATA_BIT0 0x3fe>, /* SODIMM 56 */ 838 <IMX95_PAD_XSPI1_DATA1__XSPI_DATA_BIT1 0x3fe>, /* SODIMM 58 */ 839 <IMX95_PAD_XSPI1_DATA2__XSPI_DATA_BIT2 0x3fe>, /* SODIMM 60 */ 840 <IMX95_PAD_XSPI1_DATA3__XSPI_DATA_BIT3 0x3fe>, /* SODIMM 62 */ 841 <IMX95_PAD_XSPI1_DQS__XSPI_DQS 0x3fe>; /* SODIMM 66 */ 842 }; 843 844 /* Verdin GPIO_1 */ 845 pinctrl_gpio1: gpio1grp { 846 fsl,pins = <IMX95_PAD_GPIO_IO00__GPIO2_IO_BIT0 0x51e>; /* SODIMM 206 */ 847 }; 848 849 /* Verdin GPIO_2 */ 850 pinctrl_gpio2: gpio2grp { 851 fsl,pins = <IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x51e>; /* SODIMM 208 */ 852 }; 853 854 /* Verdin GPIO_3 */ 855 pinctrl_gpio3: gpio3grp { 856 fsl,pins = <IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24 0x51e>; /* SODIMM 210 */ 857 }; 858 859 /* Verdin GPIO_4 */ 860 pinctrl_gpio4: gpio4grp { 861 fsl,pins = <IMX95_PAD_GPIO_IO32__GPIO5_IO_BIT12 0x51e>; /* SODIMM 212 */ 862 }; 863 864 /* Verdin GPIO_5_CSI */ 865 pinctrl_gpio5: gpio5grp { 866 fsl,pins = <IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x51e>; /* SODIMM 216 */ 867 }; 868 869 /* Verdin GPIO_6_CSI */ 870 pinctrl_gpio6: gpio6grp { 871 fsl,pins = <IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x51e>; /* SODIMM 218 */ 872 }; 873 874 /* Verdin I2S_2_BCLK as GPIO (conflict with Verdin I2S_2) */ 875 pinctrl_i2s_2_bclk_gpio: i2s2bclkgpiogrp { 876 fsl,pins = <IMX95_PAD_XSPI1_DATA6__GPIO5_IO_BIT6 0x51e>; /* SODIMM 42 */ 877 }; 878 879 /* Verdin I2S_2_D_IN as GPIO (conflict with Verdin I2S_2) */ 880 pinctrl_i2s_2_d_in_gpio: i2s2dingpiogrp { 881 fsl,pins = <IMX95_PAD_XSPI1_DATA7__GPIO5_IO_BIT7 0x31e>; /* SODIMM 48 */ 882 }; 883 884 /* Verdin I2S_2_D_OUT as GPIO (conflict with Verdin I2S_2) */ 885 pinctrl_i2s_2_d_out_gpio: i2s2doutgpiogrp { 886 fsl,pins = <IMX95_PAD_XSPI1_DATA4__GPIO5_IO_BIT4 0x51e>; /* SODIMM 46 */ 887 }; 888 889 /* Verdin I2S_2_SYNC as GPIO (conflict with Verdin I2S_2) */ 890 pinctrl_i2s_2_sync_gpio: i2s2syncgpiogrp { 891 fsl,pins = <IMX95_PAD_XSPI1_DATA5__GPIO5_IO_BIT5 0x51e>; /* SODIMM 44 */ 892 }; 893 894 /* Verdin I2C_3_HDMI */ 895 pinctrl_i3c2: i3c2cgrp { 896 fsl,pins = <IMX95_PAD_ENET1_MDC__I3C2_SCL 0x40001186>, /* SODIMM 59 */ 897 <IMX95_PAD_ENET1_MDIO__I3C2_SDA 0x40001186>; /* SODIMM 57 */ 898 }; 899 900 pinctrl_io_exp_int: ioexpintgrp { 901 fsl,pins = <IMX95_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_BIT13 0x31e>; /* IO_EXP_INT */ 902 }; 903 904 /* CTRL_I2C (On-module I2C) */ 905 pinctrl_lpi2c2_gpio: lpi2c2gpiogrp { 906 fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_BIT2 0x40001b9e>, /* CTRL_I2C_SCL */ 907 <IMX95_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_BIT3 0x40001b9e>; /* CTRL_I2C_SDA */ 908 }; 909 910 pinctrl_lpi2c2: lpi2c2grp { 911 fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40001b9e>, /* CTRL_I2C_SCL */ 912 <IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40001b9e>; /* CTRL_I2C_SDA */ 913 }; 914 915 /* Verdin I2C_2_DSI */ 916 pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { 917 fsl,pins = <IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x40001b9e>, /* SODIMM 53 */ 918 <IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x40001b9e>; /* SODIMM 55 */ 919 }; 920 921 pinctrl_lpi2c3: lpi2c3grp { 922 fsl,pins = <IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40001b9e>, /* SODIMM 53 */ 923 <IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40001b9e>; /* SODIMM 55 */ 924 }; 925 926 /* Verdin I2C_1 */ 927 pinctrl_lpi2c4_gpio: lpi2c4gpiogrp { 928 fsl,pins = <IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31 0x40001b9e>, /* SODIMM 14 */ 929 <IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30 0x40001b9e>; /* SODIMM 12 */ 930 }; 931 932 pinctrl_lpi2c4: lpi2c4grp { 933 fsl,pins = <IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40001b9e>, /* SODIMM 14 */ 934 <IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40001b9e>; /* SODIMM 12 */ 935 }; 936 937 /* Verdin I2C_4_CSI */ 938 pinctrl_lpi2c5_gpio: lpi2c5gpiogrp { 939 fsl,pins = <IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22 0x40001b9e>, /* SODIMM 93 */ 940 <IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23 0x40001b9e>; /* SODIMM 95 */ 941 }; 942 943 pinctrl_lpi2c5: lpi2c5grp { 944 fsl,pins = <IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x40001b9e>, /* SODIMM 93 */ 945 <IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x40001b9e>; /* SODIMM 95 */ 946 }; 947 948 /* Verdin SPI_1 */ 949 pinctrl_lpspi6: lpspi6grp { 950 fsl,pins = <IMX95_PAD_GPIO_IO01__LPSPI6_SIN 0x3fe>, /* SODIMM 198 */ 951 <IMX95_PAD_GPIO_IO02__LPSPI6_SOUT 0x3fe>, /* SODIMM 200 */ 952 <IMX95_PAD_GPIO_IO03__LPSPI6_SCK 0x3fe>; /* SODIMM 196 */ 953 }; 954 955 /* Verdin QSPI_1_CLK as GPIO (conflict with Verdin QSPI_1 interface) */ 956 pinctrl_qspi1_clk_gpio: qspi1clkgpiogrp { 957 fsl,pins = <IMX95_PAD_XSPI1_SCLK__GPIO5_IO_BIT9 0x11e>; /* SODIMM 52 */ 958 }; 959 960 /* Verdin QSPI_1_CS2# as GPIO (conflict with Verdin QSPI_1 interface) */ 961 pinctrl_qspi1_cs2_gpio: qspi1cs2gpiogrp { 962 fsl,pins = <IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x11e>; /* SODIMM 64 */ 963 }; 964 965 /* Verdin QSPI_1_CS# as GPIO (conflict with Verdin QSPI_1 interface) */ 966 pinctrl_qspi1_cs_gpio: qspi1csgpiogrp { 967 fsl,pins = <IMX95_PAD_XSPI1_SS0_B__GPIO5_IO_BIT10 0x11e>; /* SODIMM 54 */ 968 }; 969 970 /* Verdin QSPI_1_DQS as GPIO (conflict with Verdin QSPI_1 interface) */ 971 pinctrl_qspi1_dqs_gpio: qspi1dqsgpiogrp { 972 fsl,pins = <IMX95_PAD_XSPI1_DQS__GPIO5_IO_BIT8 0x11e>; /* SODIMM 66 */ 973 }; 974 975 /* Verdin QSPI_1_IO0 as GPIO (conflict with Verdin QSPI_1 interface) */ 976 pinctrl_qspi1_io0_gpio: qspi1io0gpiogrp { 977 fsl,pins = <IMX95_PAD_XSPI1_DATA0__GPIO5_IO_BIT0 0x119e>; /* SODIMM 56 */ 978 }; 979 980 /* Verdin QSPI_1_IO1 as GPIO (conflict with Verdin QSPI_1 interface) */ 981 pinctrl_qspi1_io1_gpio: qspi1io1gpiogrp { 982 fsl,pins = <IMX95_PAD_XSPI1_DATA1__GPIO5_IO_BIT1 0x119e>; /* SODIMM 58 */ 983 }; 984 985 /* Verdin QSPI_1_IO2 as GPIO (conflict with Verdin QSPI_1 interface) */ 986 pinctrl_qspi1_io2_gpio: qspi1io2gpiogrp { 987 fsl,pins = <IMX95_PAD_XSPI1_DATA2__GPIO5_IO_BIT2 0x11e>; /* SODIMM 60 */ 988 }; 989 990 /* Verdin QSPI_1_IO3 as GPIO (conflict with Verdin QSPI_1 interface) */ 991 pinctrl_qspi1_io3_gpio: qspi1io3gpiogrp { 992 fsl,pins = <IMX95_PAD_XSPI1_DATA3__GPIO5_IO_BIT3 0x11e>; /* SODIMM 62 */ 993 }; 994 995 /* Verdin I2S_1 */ 996 pinctrl_sai3: sai3grp { 997 fsl,pins = <IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x11e>, /* SODIMM 30 */ 998 <IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x11e>, /* SODIMM 36 */ 999 <IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x11e>, /* SODIMM 34 */ 1000 <IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x11e>; /* SODIMM 32 */ 1001 }; 1002 1003 /* Verdin I2S_1_MCLK */ 1004 pinctrl_sai3_mclk: sai3mclkgrp { 1005 fsl,pins = <IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e>; /* SODIMM 38 */ 1006 }; 1007 1008 /* Verdin I2S_2 */ 1009 pinctrl_sai5: sai5grp { 1010 fsl,pins = <IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0 0x11e>, /* SODIMM 46 */ 1011 <IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC 0x11e>, /* SODIMM 44 */ 1012 <IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK 0x11e>, /* SODIMM 42 */ 1013 <IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0 0x11e>; /* SODIMM 48 */ 1014 }; 1015 1016 /* Verdin SPI_1_CS */ 1017 pinctrl_spi1_cs: spi1csgrp { 1018 fsl,pins = <IMX95_PAD_CCM_CLKO4__GPIO4_IO_BIT29 0x3fe>; /* SODIMM 202 */ 1019 }; 1020 1021 /* Verdin PWM_1 */ 1022 pinctrl_tpm4: tpm4grp { 1023 fsl,pins = <IMX95_PAD_GPIO_IO05__TPM4_CH0 0x11e>; /* SODIMM 15 */ 1024 }; 1025 1026 /* Verdin PWM_2 */ 1027 pinctrl_tpm5: tpm5grp { 1028 fsl,pins = <IMX95_PAD_GPIO_IO06__TPM5_CH0 0x11e>; /* SODIMM 16 */ 1029 }; 1030 1031 /* Verdin PWM_3_DSI as GPIO */ 1032 pinctrl_tpm6_gpio: tpm6gpiogrp { 1033 fsl,pins = <IMX95_PAD_GPIO_IO19__GPIO2_IO_BIT19 0x51e>; /* SODIMM 19 */ 1034 }; 1035 1036 /* Verdin PWM_3_DSI */ 1037 pinctrl_tpm6: tpm6grp { 1038 fsl,pins = <IMX95_PAD_GPIO_IO19__TPM6_CH2 0x11e>; /* SODIMM 19 */ 1039 }; 1040 1041 /* Verdin UART_3, used as the Linux Console */ 1042 pinctrl_uart1: uart1grp { 1043 fsl,pins = <IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e>, /* SODIMM 147 */ 1044 <IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e>; /* SODIMM 149 */ 1045 }; 1046 1047 /* Verdin UART_4 */ 1048 pinctrl_uart2: uart2grp { 1049 fsl,pins = <IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x31e>, /* SODIMM 151 */ 1050 <IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x31e>; /* SODIMM 153 */ 1051 }; 1052 1053 /* Verdin UART_1 */ 1054 pinctrl_uart7: uart7grp { 1055 fsl,pins = <IMX95_PAD_GPIO_IO08__LPUART7_TX 0x31e>, /* SODIMM 131 */ 1056 <IMX95_PAD_GPIO_IO09__LPUART7_RX 0x31e>, /* SODIMM 129 */ 1057 <IMX95_PAD_GPIO_IO10__LPUART7_CTS_B 0x31e>, /* SODIMM 135 */ 1058 <IMX95_PAD_GPIO_IO11__LPUART7_RTS_B 0x31e>; /* SODIMM 133 */ 1059 }; 1060 1061 /* Verdin UART_2 */ 1062 pinctrl_uart8: uart8grp { 1063 fsl,pins = <IMX95_PAD_GPIO_IO12__LPUART8_TX 0x31e>, /* SODIMM 139 */ 1064 <IMX95_PAD_GPIO_IO13__LPUART8_RX 0x31e>, /* SODIMM 137 */ 1065 <IMX95_PAD_GPIO_IO14__LPUART8_CTS_B 0x31e>, /* SODIMM 143 */ 1066 <IMX95_PAD_GPIO_IO15__LPUART8_RTS_B 0x31e>; /* SODIMM 141 */ 1067 }; 1068 1069 /* On-module eMMC */ 1070 pinctrl_usdhc1: usdhc1grp { 1071 fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e>, /* SD1_CLK */ 1072 <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e>, /* SD1_CMD */ 1073 <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e>, /* SD1_DATA0 */ 1074 <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e>, /* SD1_DATA1 */ 1075 <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e>, /* SD1_DATA2 */ 1076 <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e>, /* SD1_DATA3 */ 1077 <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e>, /* SD1_DATA4 */ 1078 <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e>, /* SD1_DATA5 */ 1079 <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e>, /* SD1_DATA6 */ 1080 <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e>, /* SD1_DATA7 */ 1081 <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e>; /* SD1_STROBE */ 1082 }; 1083 1084 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1085 fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe>, /* SD1_CLK */ 1086 <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe>, /* SD1_CMD */ 1087 <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe>, /* SD1_DATA0 */ 1088 <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe>, /* SD1_DATA1 */ 1089 <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe>, /* SD1_DATA2 */ 1090 <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe>, /* SD1_DATA3 */ 1091 <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe>, /* SD1_DATA4 */ 1092 <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe>, /* SD1_DATA5 */ 1093 <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe>, /* SD1_DATA6 */ 1094 <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe>, /* SD1_DATA7 */ 1095 <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe>; /* SD1_STROBE */ 1096 }; 1097 1098 /* Verdin SD_1 */ 1099 pinctrl_usdhc2: usdhc2grp { 1100 fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e>, /* SODIMM 78 */ 1101 <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e>, /* SODIMM 74 */ 1102 <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e>, /* SODIMM 80 */ 1103 <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e>, /* SODIMM 82 */ 1104 <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e>, /* SODIMM 70 */ 1105 <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e>; /* SODIMM 72 */ 1106 }; 1107 1108 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1109 fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe>, /* SODIMM 78 */ 1110 <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe>, /* SODIMM 74 */ 1111 <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe>, /* SODIMM 80 */ 1112 <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe>, /* SODIMM 82 */ 1113 <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe>, /* SODIMM 70 */ 1114 <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe>; /* SODIMM 72 */ 1115 }; 1116 1117 pinctrl_usdhc2_sleep: usdhc2-sleepgrp { 1118 fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x400>, /* SODIMM 78 */ 1119 <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x400>, /* SODIMM 74 */ 1120 <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x400>, /* SODIMM 80 */ 1121 <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x400>, /* SODIMM 82 */ 1122 <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x400>, /* SODIMM 70 */ 1123 <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x400>; /* SODIMM 72 */ 1124 }; 1125 1126 /* Verdin SD_1_CD# */ 1127 pinctrl_usdhc2_cd: usdhc2-cdgrp { 1128 fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>; /* SODIMM 84 */ 1129 }; 1130 1131 /* Verdin SD_1_PWR_EN */ 1132 pinctrl_usdhc2_pwr_en: usdhc2-pwrengrp { 1133 fsl,pins = <IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x11e>; /* SODIMM 76 */ 1134 }; 1135 1136 pinctrl_usdhc2_vsel: usdhc2-vselgrp { 1137 fsl,pins = <IMX95_PAD_SD2_VSELECT__GPIO3_IO_BIT19 0x4>; /* PMIC_SD2_VSEL */ 1138 }; 1139 1140 /* On-module Wi-Fi on WB SKUs, module-specific SDIO otherwise */ 1141 pinctrl_usdhc3: usdhc3grp { 1142 fsl,pins = <IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e>, /* SD3_CLK */ 1143 <IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e>, /* SD3_CMD */ 1144 <IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e>, /* SD3_DATA0 */ 1145 <IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e>, /* SD3_DATA1 */ 1146 <IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e>, /* SD3_DATA2 */ 1147 <IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e>; /* SD3_DATA3 */ 1148 }; 1149 1150 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1151 fsl,pins = <IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe>, /* SD3_CLK */ 1152 <IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe>, /* SD3_CMD */ 1153 <IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe>, /* SD3_DATA1 */ 1154 <IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe>, /* SD3_DATA2 */ 1155 <IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe>, /* SD3_DATA3 */ 1156 <IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe>; /* SD3_DATA4 */ 1157 }; 1158 1159 pinctrl_wifi_pwr_en: wifipwrengrp { 1160 fsl,pins = <IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11 0x51e>; /* PMIC_EN_WIFI */ 1161 }; 1162}; 1163