1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2/* 3 * Copyright (c) 2024-2026 TQ-Systems GmbH <linux@ew.tq-group.com>, 4 * D-82229 Seefeld, Germany. 5 * Author: Alexander Stein 6 * Author: Markus Niebel 7 */ 8 9/dts-v1/; 10 11#include <dt-bindings/leds/common.h> 12#include <dt-bindings/net/ti-dp83867.h> 13#include <dt-bindings/pwm/pwm.h> 14#include <dt-bindings/usb/pd.h> 15#include "imx95-tqma9596la.dtsi" 16 17/ { 18 model = "TQ-Systems i.MX95 TQMa95xxLA on MBa95xxCA"; 19 compatible = "tq,imx95-tqma9596la-mba95xxca", "tq,imx95-tqma9596la", "fsl,imx95"; 20 chassis-type = "embedded"; 21 22 aliases { 23 ethernet0 = &enetc_port0; 24 ethernet1 = &enetc_port1; 25 ethernet2 = &enetc_port2; 26 gpio0 = &gpio1; 27 gpio1 = &gpio2; 28 gpio2 = &gpio3; 29 gpio3 = &gpio4; 30 i2c0 = &lpi2c1; 31 i2c1 = &lpi2c2; 32 i2c2 = &lpi2c3; 33 i2c3 = &lpi2c4; 34 i2c4 = &lpi2c5; 35 i2c5 = &lpi2c6; 36 i2c6 = &lpi2c7; 37 i2c7 = &lpi2c8; 38 mmc0 = &usdhc1; 39 mmc1 = &usdhc2; 40 rtc0 = &pcf85063; 41 rtc1 = &scmi_bbm; 42 serial0 = &lpuart1; 43 serial1 = &lpuart2; 44 serial2 = &lpuart3; 45 serial3 = &lpuart4; 46 serial4 = &lpuart5; 47 serial5 = &lpuart6; 48 serial6 = &lpuart7; 49 serial7 = &lpuart8; 50 spi0 = &flexspi1; 51 }; 52 53 chosen { 54 stdout-path = &lpuart1; 55 }; 56 57 backlight_lvds: backlight-lvds { 58 compatible = "pwm-backlight"; 59 pwms = <&tpm5 2 100000 0>; 60 brightness-levels = <0 4 8 16 32 64 128 255>; 61 default-brightness-level = <7>; 62 enable-gpios = <&expander2 6 GPIO_ACTIVE_HIGH>; 63 power-supply = <®_12v0>; 64 status = "disabled"; 65 }; 66 67 clk_eth: clk-eth { 68 compatible = "fixed-clock"; 69 #clock-cells = <0>; 70 clock-frequency = <156250000>; 71 }; 72 73 /* 74 * TODO: gate is disabled for now and GPIO are hogged 75 * ENETC driver switches the clock far too late for ENETC2 + SFP 76 */ 77 clk_eth_gate: clk-eth-gate { 78 compatible = "gpio-gate-clock"; 79 enable-gpios = <&expander2 0 GPIO_ACTIVE_HIGH>; 80 clocks = <&clk_eth>; 81 #clock-cells = <0>; 82 status = "disabled"; 83 }; 84 85 clk_xtal25: clk-xtal25 { 86 compatible = "fixed-clock"; 87 #clock-cells = <0>; 88 clock-frequency = <25000000>; 89 }; 90 91 gpio-keys { 92 compatible = "gpio-keys"; 93 autorepeat; 94 95 button-b { 96 label = "BUTTON_B#"; 97 linux,code = <BTN_1>; 98 gpios = <&expander1 0 GPIO_ACTIVE_LOW>; 99 wakeup-source; 100 }; 101 }; 102 103 gpio-leds { 104 compatible = "gpio-leds"; 105 106 led-1 { 107 color = <LED_COLOR_ID_GREEN>; 108 function = LED_FUNCTION_STATUS; 109 gpios = <&expander2 13 GPIO_ACTIVE_HIGH>; 110 linux,default-trigger = "default-on"; 111 }; 112 113 led-2 { 114 color = <LED_COLOR_ID_AMBER>; 115 function = LED_FUNCTION_HEARTBEAT; 116 gpios = <&expander2 14 GPIO_ACTIVE_HIGH>; 117 linux,default-trigger = "heartbeat"; 118 }; 119 }; 120 121 iio-hwmon { 122 compatible = "iio-hwmon"; 123 io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>, 124 <&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>; 125 }; 126 127 reg_v1v8_mb: regulator-v1v8-mb { 128 compatible = "regulator-fixed"; 129 regulator-name = "V_1V8_MB"; 130 regulator-min-microvolt = <1800000>; 131 regulator-max-microvolt = <1800000>; 132 regulator-always-on; 133 }; 134 135 reg_v3v3_mb: regulator-v3v3-mb { 136 compatible = "regulator-fixed"; 137 regulator-name = "V_3V3_MB"; 138 regulator-min-microvolt = <3300000>; 139 regulator-max-microvolt = <3300000>; 140 regulator-always-on; 141 }; 142 143 reg_3v3a_10g: regulator-3v3a-10g { 144 compatible = "regulator-fixed"; 145 regulator-name = "3V3A_10G"; 146 regulator-min-microvolt = <3300000>; 147 regulator-max-microvolt = <3300000>; 148 gpio = <&expander2 15 GPIO_ACTIVE_HIGH>; 149 startup-delay-us = <2000>; 150 enable-active-high; 151 }; 152 153 reg_12v0: regulator-12v0 { 154 compatible = "regulator-fixed"; 155 regulator-name = "12V0"; 156 regulator-min-microvolt = <12000000>; 157 regulator-max-microvolt = <12000000>; 158 gpio = <&expander1 15 GPIO_ACTIVE_HIGH>; 159 enable-active-high; 160 }; 161 162 reg_pwm_fan: regulator-pwm-fan { 163 compatible = "regulator-fixed"; 164 regulator-name = "FAN_PWR"; 165 regulator-min-microvolt = <12000000>; 166 regulator-max-microvolt = <12000000>; 167 gpio = <&expander3 15 GPIO_ACTIVE_HIGH>; 168 enable-active-high; 169 vin-supply = <®_12v0>; 170 /* 171 * emc2305 fan driver lacks support for fan-supply, so 172 * alway enable it for now. 173 * Remove this line once support is added 174 */ 175 regulator-always-on; 176 }; 177 178 reg_lvds: regulator-lvds { 179 compatible = "regulator-fixed"; 180 regulator-name = "LCD_PWR_EN"; 181 regulator-min-microvolt = <3300000>; 182 regulator-max-microvolt = <3300000>; 183 gpio = <&expander2 7 GPIO_ACTIVE_HIGH>; 184 enable-active-high; 185 }; 186 187 /* USB NC limitations, RM 162.1.2 VBUS limitations */ 188 reg_vbus_usb3: regulator-vbus-usb3 { 189 compatible = "regulator-fixed"; 190 regulator-min-microvolt = <5000000>; 191 regulator-max-microvolt = <5000000>; 192 regulator-name = "USB3_VBUS"; 193 gpio = <&gpio4 1 GPIO_ACTIVE_HIGH>; 194 enable-active-high; 195 }; 196 197 reserved-memory { 198 #address-cells = <2>; 199 #size-cells = <2>; 200 ranges; 201 202 linux_cma: linux,cma { 203 compatible = "shared-dma-pool"; 204 reusable; 205 size = <0 0x28000000>; 206 alloc-ranges = <0 0x80000000 0 0x80000000>; 207 linux,cma-default; 208 }; 209 }; 210 211 sfp_xfi: sfp-xfi { 212 compatible = "sff,sfp"; 213 pinctrl-names = "default"; 214 pinctrl-0 = <&pinctrl_sfp>; 215 i2c-bus = <&lpi2c7>; 216 maximum-power-milliwatt = <2000>; 217 mod-def0-gpios = <&expander1 3 GPIO_ACTIVE_LOW>; 218 tx-fault-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; 219 los-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; 220 tx-disable-gpios = <&expander2 2 GPIO_ACTIVE_HIGH>; 221 }; 222 223 sound { 224 compatible = "fsl,imx-audio-tlv320aic32x4"; 225 model = "tqm-tlv320aic32"; 226 audio-codec = <&tlv320aic3x04>; 227 audio-cpu = <&sai3>; 228 audio-routing = 229 "IN3_L", "Mic Jack", 230 "Mic Jack", "Mic Bias", 231 "Headphone Jack", "HPL", 232 "Headphone Jack", "HPR", 233 "IN1_L", "Line In Jack", 234 "IN1_R", "Line In Jack", 235 "Line Out Jack", "LOL", 236 "Line Out Jack", "LOR"; 237 }; 238 239 wifi-connector { 240 compatible = "pcie-m2-e-connector"; 241 vpcie3v3-supply = <®_v3v3_mb>; 242 vpcie1v8-supply = <®_v1v8_mb>; 243 i2c-parent = <&lpi2c2>; 244 w-disable1-gpios = <&expander2 9 GPIO_ACTIVE_LOW>; 245 w-disable2-gpios = <&expander2 10 GPIO_ACTIVE_LOW>; 246 /* UART_WAKE is connected to SM */ 247 /* SDIO_WAKE is connected to SM */ 248 sdio-reset-gpios = <&expander3 2 GPIO_ACTIVE_LOW>; 249 }; 250}; 251 252&adc1 { 253 status = "okay"; 254}; 255 256&enetc_port0 { 257 pinctrl-names = "default"; 258 pinctrl-0 = <&pinctrl_enetc0>; 259 phy-handle = <ðphy0>; 260 phy-mode = "rgmii-id"; 261 status = "okay"; 262}; 263 264&enetc_port1 { 265 pinctrl-names = "default"; 266 pinctrl-0 = <&pinctrl_enetc1>; 267 phy-handle = <ðphy1>; 268 phy-mode = "rgmii-id"; 269 status = "okay"; 270}; 271 272/* No support for XFI yet */ 273&enetc_port2 { 274 sfp = <&sfp_xfi>; 275 phy-mode = "10gbase-r"; 276 clocks = <&clk_eth>; 277 managed = "in-band-status"; 278 status = "disabled"; 279}; 280 281&flexcan1 { 282 pinctrl-names = "default"; 283 pinctrl-0 = <&pinctrl_flexcan1>; 284 status = "okay"; 285}; 286 287&flexcan2 { 288 pinctrl-names = "default"; 289 pinctrl-0 = <&pinctrl_flexcan2>; 290 status = "okay"; 291}; 292 293&lpi2c2 { 294 tlv320aic3x04: audio-codec@18 { 295 compatible = "ti,tlv320aic32x4"; 296 reg = <0x18>; 297 clocks = <&scmi_clk IMX95_CLK_SAI3>; 298 clock-names = "mclk"; 299 reset-gpios = <&expander1 14 GPIO_ACTIVE_LOW>; 300 iov-supply = <®_v3v3_mb>; 301 ldoin-supply = <®_v3v3_mb>; 302 }; 303 304 sensor_mb: temperature-sensor@1e { 305 compatible = "nxp,se97b", "jedec,jc-42.4-temp"; 306 reg = <0x1e>; 307 }; 308 309 fan_controller: fan-controller@2f { 310 compatible = "microchip,emc2301", "microchip,emc2305"; 311 reg = <0x2f>; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 #pwm-cells = <3>; 315 status = "okay"; 316 317 fan: fan@0 { 318 reg = <0x0>; 319 pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED 1>; 320 #cooling-cells = <2>; 321 fan-supply = <®_pwm_fan>; 322 }; 323 }; 324 325 ptn5110: usb-typec@50 { 326 compatible = "nxp,ptn5110", "tcpci"; 327 reg = <0x50>; 328 pinctrl-names = "default"; 329 pinctrl-0 = <&pinctrl_typec>; 330 interrupt-parent = <&gpio2>; 331 interrupts = <28 IRQ_TYPE_LEVEL_LOW>; 332 333 typec_con: connector { 334 compatible = "usb-c-connector"; 335 label = "X9"; 336 power-role = "source"; 337 data-role = "dual"; 338 source-pdos = <PDO_FIXED(5000, 500, PDO_FIXED_USB_COMM)>; 339 self-powered; 340 341 port { 342 typec_con_hs: endpoint { 343 remote-endpoint = <&typec_hs>; 344 }; 345 }; 346 }; 347 }; 348 349 eeprom_mb: eeprom@56 { 350 compatible = "nxp,se97b", "atmel,24c02"; 351 reg = <0x56>; 352 pagesize = <16>; 353 vcc-supply = <®_v3v3_mb>; 354 }; 355 356 pcieclk: clock-generator@68 { 357 compatible = "renesas,9fgv0441"; 358 reg = <0x68>; 359 clocks = <&clk_xtal25>; 360 #clock-cells = <1>; 361 }; 362 363 /* D39 IN/OUT 3V3 */ 364 expander1: gpio@74 { 365 compatible = "ti,tca9539"; 366 reg = <0x74>; 367 vcc-supply = <®_v3v3_mb>; 368 pinctrl-names = "default"; 369 pinctrl-0 = <&pinctrl_expander1>; 370 gpio-controller; 371 #gpio-cells = <2>; 372 interrupt-controller; 373 #interrupt-cells = <2>; 374 interrupt-parent = <&gpio2>; 375 interrupts = <14 IRQ_TYPE_EDGE_FALLING>; 376 377 gpio-line-names = 378 /* 00 */ "BUTTON_B#", "CAM0_SYNC_3V3", 379 /* 02 */ "CAM1_SYNC_3V3", "SFP_MOD_ABS", 380 /* 04 */ "DIG_IN1", "DIG_IN2", 381 /* 06 */ "DIG_IN3", "DIG_IN4", 382 /* 08 */ "DIG_OUT_1_2_STATE", "DIG_OUT_3_4_STATE", 383 /* 10 */ "DIG_OUT_1_EN", "DIG_OUT_2_EN", 384 /* 12 */ "DIG_OUT_3_EN", "DIG_OUT_4_EN", 385 /* 14 */ "AUDIO_RST#", "12V_EN"; 386 }; 387 388 /* D40 OUT 3V3 */ 389 expander2: gpio@75 { 390 compatible = "ti,tca9539"; 391 reg = <0x75>; 392 vcc-supply = <®_v3v3_mb>; 393 gpio-controller; 394 #gpio-cells = <2>; 395 396 gpio-line-names = 397 /* 00 */ "ETH10G_REFCLK_EN", "ETH10G_REFCLK_RST#", 398 /* 02 */ "SFP_TX_DIS", "USB3_RESET#", 399 /* 04 */ "USB2_RESET#", "LCD_RESET#", 400 /* 06 */ "LCD_BLT_EN", "LCD_PWR_EN", 401 /* 08 */ "M2_KEYE_PERST#", "M2_KEYE_WDISABLE1#", 402 /* 10 */ "M2_KEYE_WDISABLE2#", "M2_KEYB_PERST#", 403 /* 12 */ "M2_KEYB_WDISABLE1#", "USER_LED1", 404 /* 14 */ "USER_LED2", "3V3A_10G_EN"; 405 406 eth10g-refclk-en-hog { 407 gpio-hog; 408 gpios = <0 GPIO_ACTIVE_HIGH>; 409 output-high; 410 line-name = "ETH10G_REFCLK_EN"; 411 }; 412 413 eth10g-refclk-rst-hog { 414 gpio-hog; 415 gpios = <1 GPIO_ACTIVE_LOW>; 416 output-low; 417 line-name = "ETH10G_REFCLK_RST#"; 418 }; 419 420 m2-keyb-wdisable1-hog { 421 gpio-hog; 422 gpios = <12 GPIO_ACTIVE_LOW>; 423 output-low; 424 line-name = "M2_KEYB_WDISABLE1#"; 425 }; 426 }; 427 428 /* D41 OUT 1V8 */ 429 expander3: gpio@76 { 430 compatible = "ti,tca9539"; 431 reg = <0x76>; 432 vcc-supply = <®_v1v8_mb>; 433 gpio-controller; 434 #gpio-cells = <2>; 435 436 gpio-line-names = 437 /* 00 */ "ENET1_RESET#", "ENET2_RESET#", 438 /* 02 */ "M2_KEYE_SDIO_RST#", "M2_KEYE_DEV_WLAN_WAKE#", 439 /* 04 */ "M2_KEYE_DEV_BT_WAKE", "M2_KEYB_W_DISABLE2#", 440 /* 06 */ "M2_KEYB_RST#", "M2_KEYB_FULL_CARD_PWR_OFF#", 441 /* 08 */ "M2_KEYB_DPR", "CAM0_PWR#", 442 /* 10 */ "CAM1_PWR#", "CAM0_RST#", 443 /* 12 */ "CAM1_RST#", "CAM0_TRIGGER", 444 /* 14 */ "CAM1_TRIGGER", "FAN_PWR_EN"; 445 446 /* vendor defined pin 42 */ 447 m2-keye-dev_wlan-wake-hog { 448 gpio-hog; 449 gpios = <3 GPIO_ACTIVE_LOW>; 450 input; 451 line-name = "M2_KEYE_DEV_WLAN_WAKE#"; 452 }; 453 454 /* vendor defined pin 40 */ 455 m2-keye-dev_bt-wake-hog { 456 gpio-hog; 457 gpios = <4 GPIO_ACTIVE_LOW>; 458 input; 459 line-name = "M2_KEYE_DEV_BT_WAKE#"; 460 }; 461 462 m2-keyb-wdisable2-hog { 463 gpio-hog; 464 gpios = <5 GPIO_ACTIVE_LOW>; 465 output-low; 466 line-name = "M2_KEYB_WDISABLE2#"; 467 }; 468 469 m2-keyb-rst-hog { 470 gpio-hog; 471 gpios = <6 GPIO_ACTIVE_LOW>; 472 output-low; 473 line-name = "M2_KEYB_RST#"; 474 }; 475 476 m2-keyb-full-card-pwr-off-hog { 477 gpio-hog; 478 gpios = <7 GPIO_ACTIVE_LOW>; 479 output-low; 480 line-name = "M2_KEYB_FULL_CARD_PWR_OFF#"; 481 }; 482 }; 483}; 484 485/* X4 + SFP */ 486&lpi2c7 { 487 clock-frequency = <400000>; 488 pinctrl-names = "default", "gpio"; 489 pinctrl-0 = <&pinctrl_lpi2c7>; 490 pinctrl-1 = <&pinctrl_lpi2c7_recovery>; 491 scl-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 492 sda-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 493 status = "okay"; 494 495 /* TODO: 0x19: retimer */ 496 497 /* 0x50 / 0x51: SFP EEPROM */ 498}; 499 500/* X4 */ 501&lpspi4 { 502 pinctrl-names = "default"; 503 pinctrl-0 = <&pinctrl_lpspi4>; 504 cs-gpios = <&gpio5 14 GPIO_ACTIVE_LOW>, <&gpio5 13 GPIO_ACTIVE_LOW>; 505 /* max 30 MHz as per datasheet, without SCK loopback via pad (LPSPI_CFGR1[SAMPLE]) */ 506 status = "okay"; 507}; 508 509&lpuart1 { 510 /* console */ 511 pinctrl-names = "default"; 512 pinctrl-0 = <&pinctrl_lpuart1>; 513 status = "okay"; 514}; 515 516&lpuart2 { 517 /* SM */ 518 pinctrl-names = "default"; 519 pinctrl-0 = <&pinctrl_lpuart2>; 520 status = "reserved"; 521}; 522 523&lpuart5 { 524 /* X16 M.2 KEY E */ 525 pinctrl-names = "default"; 526 pinctrl-0 = <&pinctrl_lpuart5>; 527 status = "okay"; 528}; 529 530&lpuart7 { 531 /* X5 */ 532 pinctrl-names = "default"; 533 pinctrl-0 = <&pinctrl_lpuart7>; 534 status = "okay"; 535}; 536 537&lpuart8 { 538 /* X15 */ 539 pinctrl-names = "default"; 540 pinctrl-0 = <&pinctrl_lpuart8>; 541 linux,rs485-enabled-at-boot-time; 542 status = "okay"; 543}; 544 545&netc_blk_ctrl { 546 status = "okay"; 547}; 548 549&netc_emdio { 550 pinctrl-names = "default"; 551 pinctrl-0 = <&pinctrl_emdio>; 552 status = "okay"; 553 554 /* IRQ pin is AON GPIO, not usable */ 555 ethphy0: ethernet-phy@0 { 556 compatible = "ethernet-phy-ieee802.3-c22"; 557 reg = <0>; 558 reset-gpios = <&expander3 0 GPIO_ACTIVE_LOW>; 559 reset-assert-us = <500000>; 560 reset-deassert-us = <50000>; 561 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; 562 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; 563 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 564 ti,dp83867-rxctrl-strap-quirk; 565 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 566 }; 567 568 ethphy1: ethernet-phy@1 { 569 compatible = "ethernet-phy-ieee802.3-c22"; 570 reg = <1>; 571 pinctrl-names = "default"; 572 pinctrl-0 = <&pinctrl_ethphy1>; 573 reset-gpios = <&expander3 1 GPIO_ACTIVE_LOW>; 574 reset-assert-us = <500000>; 575 reset-deassert-us = <50000>; 576 interrupt-parent = <&gpio4>; 577 interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 578 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; 579 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; 580 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 581 ti,dp83867-rxctrl-strap-quirk; 582 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 583 }; 584}; 585 586&netc_timer { 587 status = "okay"; 588}; 589 590&netcmix_blk_ctrl { 591 status = "okay"; 592}; 593 594/* X16 M2 / E-Key mPCIe */ 595&pcie0 { 596 pinctrl-0 = <&pinctrl_pcie0>; 597 pinctrl-names = "default"; 598 clocks = <&scmi_clk IMX95_CLK_HSIO>, 599 <&scmi_clk IMX95_CLK_HSIOPLL>, 600 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 601 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, 602 <&hsio_blk_ctl 0>, 603 <&pcieclk 1>; 604 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref", "extref"; 605 reset-gpios = <&expander2 8 GPIO_ACTIVE_LOW>; 606 /* Not supported on REV.0100 */ 607 /* supports-clkreq; */ 608 status = "okay"; 609}; 610 611/* X17 M2 / B-Key PCIe */ 612&pcie1 { 613 pinctrl-0 = <&pinctrl_pcie1>; 614 pinctrl-names = "default"; 615 clocks = <&scmi_clk IMX95_CLK_HSIO>, 616 <&scmi_clk IMX95_CLK_HSIOPLL>, 617 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 618 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, 619 <&hsio_blk_ctl 0>, 620 <&pcieclk 0>; 621 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref", "extref"; 622 reset-gpios = <&expander2 11 GPIO_ACTIVE_LOW>; 623 /* Not supported on REV.0100 */ 624 /* supports-clkreq; */ 625 status = "okay"; 626}; 627 628®_sdvmmc { 629 status = "okay"; 630}; 631 632&sai3 { 633 #sound-dai-cells = <0>; 634 pinctrl-names = "default"; 635 pinctrl-0 = <&pinctrl_sai3>; 636 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 637 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 638 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 639 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 640 <&scmi_clk IMX95_CLK_SAI3>; 641 assigned-clock-parents = <0>, <0>, <0>, <0>, 642 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 643 assigned-clock-rates = <3932160000>, 644 <3612672000>, <393216000>, 645 <361267200>, <12288000>; 646 fsl,sai-mclk-direction-output; 647 status = "okay"; 648}; 649 650&scmi_bbm { 651 linux,code = <KEY_POWER>; 652}; 653 654&thermal_zones { 655 a55-thermal { 656 trips { 657 cpu_active0: trip-active0 { 658 temperature = <40000>; 659 hysteresis = <5000>; 660 type = "active"; 661 }; 662 663 cpu_active1: trip-active1 { 664 temperature = <48000>; 665 hysteresis = <3000>; 666 type = "active"; 667 }; 668 669 cpu_active2: trip-active2 { 670 temperature = <60000>; 671 hysteresis = <10000>; 672 type = "active"; 673 }; 674 }; 675 676 cooling-maps { 677 map1 { 678 trip = <&cpu_active0>; 679 cooling-device = <&fan 0 2>; 680 }; 681 682 map2 { 683 trip = <&cpu_active1>; 684 cooling-device = <&fan 3 5>; 685 }; 686 687 map3 { 688 trip = <&cpu_active2>; 689 cooling-device = <&fan 6 10>; 690 }; 691 }; 692 }; 693}; 694 695&tpm3 { 696 pinctrl-names = "default"; 697 pinctrl-0 = <&pinctrl_tpm3>; 698 status = "okay"; 699}; 700 701&tpm5 { 702 pinctrl-names = "default"; 703 pinctrl-0 = <&pinctrl_tpm5>; 704}; 705 706&usb2 { 707 dr_mode = "otg"; 708 hnp-disable; 709 srp-disable; 710 adp-disable; 711 usb-role-switch; 712 disable-over-current; 713 samsung,picophy-pre-emp-curr-control = <3>; 714 samsung,picophy-dc-vol-level-adjust = <7>; 715 status = "okay"; 716 717 port { 718 typec_hs: endpoint { 719 remote-endpoint = <&typec_con_hs>; 720 }; 721 }; 722}; 723 724&usb3 { 725 status = "okay"; 726}; 727 728&usb3_dwc3 { 729 dr_mode = "host"; 730 #address-cells = <1>; 731 #size-cells = <0>; 732 status = "okay"; 733 734 hub_2_0: hub@1 { 735 compatible = "usb451,8142"; 736 reg = <1>; 737 peer-hub = <&hub_3_0>; 738 reset-gpios = <&expander2 3 GPIO_ACTIVE_LOW>; 739 vdd-supply = <®_v3v3_mb>; 740 #address-cells = <1>; 741 #size-cells = <0>; 742 743 hub_2_1: hub@1 { 744 compatible = "usb424,2514"; 745 reg = <1>; 746 reset-gpios = <&expander2 4 GPIO_ACTIVE_LOW>; 747 vdd-supply = <®_v3v3_mb>; 748 vdda-supply = <®_v3v3_mb>; 749 }; 750 }; 751 752 hub_3_0: hub@2 { 753 compatible = "usb451,8140"; 754 reg = <2>; 755 peer-hub = <&hub_2_0>; 756 reset-gpios = <&expander2 3 GPIO_ACTIVE_LOW>; 757 vdd-supply = <®_v3v3_mb>; 758 }; 759}; 760 761&usb3_phy { 762 pinctrl-names = "default"; 763 pinctrl-0 = <&pinctrl_usb3>; 764 vbus-supply = <®_vbus_usb3>; 765 status = "okay"; 766}; 767 768/* X7 µSD */ 769&usdhc2 { 770 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 771 pinctrl-0 = <&pinctrl_usdhc2>; 772 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 773 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 774 vmmc-supply = <®_sdvmmc>; 775 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 776 no-mmc; 777 no-sdio; 778 disable-wp; 779 bus-width = <4>; 780 status = "okay"; 781}; 782 783&scmi_iomuxc { 784 pinctrl_enetc0: enetc0grp { 785 fsl,pins = <IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x1100>, 786 <IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x1100>, 787 <IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x1100>, 788 <IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x1100>, 789 <IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x1100>, 790 <IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x1100>, 791 <IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x11e>, 792 <IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x11e>, 793 <IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x11e>, 794 <IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x11e>, 795 <IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x11e>, 796 <IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x11e>; 797 }; 798 799 pinctrl_enetc1: enetc1grp { 800 fsl,pins = <IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x1100>, 801 <IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x1100>, 802 <IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x1100>, 803 <IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x1100>, 804 <IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x1100>, 805 <IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x1100>, 806 <IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x11e>, 807 <IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x11e>, 808 <IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x11e>, 809 <IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x11e>, 810 <IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x11e>, 811 <IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x11e>; 812 }; 813 814 pinctrl_ethphy1: ethphy1grp { 815 fsl,pins = <IMX95_PAD_ENET1_MDC__GPIO4_IO_BIT0 0x1100>; 816 }; 817 818 pinctrl_expander1: expander1grp { 819 fsl,pins = <IMX95_PAD_GPIO_IO14__GPIO2_IO_BIT14 0x1100>; 820 }; 821 822 pinctrl_flexcan1: flexcan1grp { 823 fsl,pins = <IMX95_PAD_SAI1_TXC__AONMIX_TOP_CAN1_RX 0x1300>, 824 <IMX95_PAD_SAI1_TXD0__AONMIX_TOP_CAN1_TX 0x31e>; 825 }; 826 827 pinctrl_flexcan2: flexcan2grp { 828 fsl,pins = <IMX95_PAD_GPIO_IO25__CAN2_TX 0x31e>, 829 <IMX95_PAD_GPIO_IO27__CAN2_RX 0x1300>; 830 }; 831 832 pinctrl_lpi2c7: lpi2c7grp { 833 fsl,pins = <IMX95_PAD_GPIO_IO07__LPI2C7_SCL 0x40001b1e>, 834 <IMX95_PAD_GPIO_IO06__LPI2C7_SDA 0x40001b1e>; 835 }; 836 837 pinctrl_lpi2c7_recovery: lpi2c7recoverygrp { 838 fsl,pins = <IMX95_PAD_GPIO_IO07__GPIO2_IO_BIT7 0x40001b1e>, 839 <IMX95_PAD_GPIO_IO06__GPIO2_IO_BIT6 0x40001b1e>; 840 }; 841 842 pinctrl_lpspi4: lpspi4grp { 843 fsl,pins = <IMX95_PAD_GPIO_IO37__LPSPI4_SCK 0x11e>, 844 <IMX95_PAD_GPIO_IO19__LPSPI4_SIN 0x111e>, 845 <IMX95_PAD_GPIO_IO36__LPSPI4_SOUT 0x11e>, 846 <IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x11e>, 847 <IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x11e>; 848 }; 849 850 pinctrl_lpuart1: lpuart1grp { 851 fsl,pins = <IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e>, 852 <IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x1300>; 853 }; 854 855 pinctrl_lpuart2: lpuart2grp { 856 fsl,pins = <IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x31e>, 857 <IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x1300>; 858 }; 859 860 pinctrl_lpuart5: lpuart5grp { 861 fsl,pins = <IMX95_PAD_GPIO_IO00__LPUART5_TX 0x31e>, 862 <IMX95_PAD_GPIO_IO01__LPUART5_RX 0x1300>, 863 <IMX95_PAD_GPIO_IO02__LPUART5_CTS_B 0x1300>, 864 <IMX95_PAD_GPIO_IO03__LPUART5_RTS_B 0x31e>; 865 }; 866 867 pinctrl_lpuart7: lpuart7grp { 868 fsl,pins = <IMX95_PAD_GPIO_IO08__LPUART7_TX 0x31e>, 869 <IMX95_PAD_GPIO_IO09__LPUART7_RX 0x1300>, 870 <IMX95_PAD_GPIO_IO10__LPUART7_CTS_B 0x1300>, 871 <IMX95_PAD_GPIO_IO11__LPUART7_RTS_B 0x31e>; 872 }; 873 874 pinctrl_lpuart8: lpuart8grp { 875 fsl,pins = <IMX95_PAD_GPIO_IO12__LPUART8_TX 0x31e>, 876 <IMX95_PAD_GPIO_IO13__LPUART8_RX 0x1300>, 877 <IMX95_PAD_GPIO_IO15__LPUART8_RTS_B 0x31e>; 878 }; 879 880 pinctrl_emdio: emdiogrp { 881 fsl,pins = <IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x51e>, 882 <IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x51e>; 883 }; 884 885 pinctrl_pcie0: pcie0grp { 886 fsl,pins = <IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x111e>; 887 }; 888 889 pinctrl_pcie1: pcie1grp { 890 fsl,pins = <IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x111e>; 891 }; 892 893 pinctrl_sai3: sai3grp { 894 fsl,pins = <IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x51e>, 895 <IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x51e>, 896 <IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x1300>, 897 <IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x51e>, 898 <IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x51e>; 899 }; 900 901 pinctrl_retimer: retimergrp { 902 fsl,pins = <IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x1100>; 903 }; 904 905 pinctrl_sfp: sfpgrp { 906 fsl,pins = <IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30 0x1100>, 907 <IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31 0x1100>; 908 }; 909 910 pinctrl_tpm3: tpm3grp { 911 fsl,pins = <IMX95_PAD_GPIO_IO24__TPM3_CH3 0x51e>; 912 }; 913 914 pinctrl_tpm5: tpm5grp { 915 fsl,pins = <IMX95_PAD_GPIO_IO18__TPM5_CH2 0x51e>; 916 }; 917 918 pinctrl_typec: typecgrp { 919 fsl,pins = <IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x1100>; 920 }; 921 922 pinctrl_usb3: usb3grp { 923 fsl,pins = <IMX95_PAD_ENET1_MDIO__GPIO4_IO_BIT1 0x31e>; 924 }; 925 926 pinctrl_usdhc2: usdhc2grp { 927 fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>, 928 <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x51e>, 929 <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x31e>, 930 <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x131e>, 931 <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x131e>, 932 <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x131e>, 933 <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x131e>, 934 <IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e>; 935 }; 936 937 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 938 fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>, 939 <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x58e>, 940 <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x38e>, 941 <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e>, 942 <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e>, 943 <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e>, 944 <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e>, 945 <IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e>; 946 }; 947 948 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 949 fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>, 950 <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x5fe>, 951 <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x3fe>, 952 <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe>, 953 <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe>, 954 <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe>, 955 <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe>, 956 <IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e>; 957 }; 958}; 959