1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright (C) 2025 Toradex 4 * 5 * https://www.toradex.com/computer-on-modules/smarc-arm-family/nxp-imx95 6 */ 7 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/net/ti-dp83867.h> 10#include "imx95.dtsi" 11 12/ { 13 aliases { 14 can0 = &flexcan1; 15 can1 = &flexcan2; 16 ethernet0 = &enetc_port0; 17 ethernet1 = &enetc_port1; 18 mmc0 = &usdhc1; 19 mmc1 = &usdhc2; 20 mmc2 = &usdhc3; 21 rtc0 = &rtc_i2c; 22 rtc1 = &scmi_bbm; 23 serial0 = &lpuart2; 24 serial1 = &lpuart1; 25 serial3 = &lpuart3; 26 }; 27 28 chosen { 29 stdout-path = "serial1:115200n8"; 30 }; 31 32 clk_dsi2dp_bridge: clock-dsi2dp-bridge { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <27000000>; 36 }; 37 38 clk_serdes_eth_ref: clock-eth-ref { 39 compatible = "gpio-gate-clock"; 40 #clock-cells = <0>; 41 /* CTRL_ETH_REF_CLK_STBY# */ 42 enable-gpios = <&som_gpio_expander_1 13 GPIO_ACTIVE_HIGH>; 43 }; 44 45 connector { 46 compatible = "gpio-usb-b-connector", "usb-b-connector"; 47 /* SMARC P64 - USB0_OTG_ID */ 48 id-gpios = <&som_gpio_expander_0 3 GPIO_ACTIVE_HIGH>; 49 label = "USB0"; 50 self-powered; 51 type = "micro"; 52 vbus-supply = <®_usb0_vbus>; 53 54 port { 55 usb_dr_connector: endpoint { 56 remote-endpoint = <&usb0_otg_id>; 57 }; 58 }; 59 }; 60 61 gpio-keys { 62 compatible = "gpio-keys"; 63 64 smarc_key_sleep: key-sleep { 65 gpios = <&som_ec_gpio_expander 4 GPIO_ACTIVE_LOW>; 66 label = "SMARC_SLEEP#"; 67 wakeup-source; 68 linux,code = <KEY_SLEEP>; 69 }; 70 71 smarc_switch_lid: switch-lid { 72 gpios = <&som_ec_gpio_expander 2 GPIO_ACTIVE_LOW>; 73 label = "SMARC_LID#"; 74 linux,code = <SW_LID>; 75 linux,input-type = <EV_SW>; 76 }; 77 }; 78 79 reg_module_1p8v: regulator-module-1p8v { 80 compatible = "regulator-fixed"; 81 regulator-max-microvolt = <1800000>; 82 regulator-min-microvolt = <1800000>; 83 regulator-name = "On-module +V1.8"; 84 }; 85 86 /* Non PMIC On-module Supplies */ 87 reg_module_dp_1p2v: regulator-module-dp-1p2v { 88 compatible = "regulator-fixed"; 89 regulator-max-microvolt = <1200000>; 90 regulator-min-microvolt = <1200000>; 91 regulator-name = "On-module +V1.2_DP"; 92 vin-supply = <®_module_1p8v>; 93 }; 94 95 reg_usb0_vbus: regulator-usb0-vbus { 96 compatible = "regulator-fixed"; 97 /* SMARC P62 - USB0_EN_OC# */ 98 gpios = <&som_gpio_expander_0 4 GPIO_ACTIVE_HIGH>; 99 enable-active-high; 100 regulator-name = "USB0_EN_OC#"; 101 }; 102 103 reg_usb1_vbus: regulator-usb1-vbus { 104 compatible = "regulator-fixed"; 105 /* CTRL_V_BUS_USB_HUB or SMARC P71 - USB2_EN_OC# */ 106 gpios = <&som_gpio_expander_0 6 GPIO_ACTIVE_HIGH>; 107 enable-active-high; 108 regulator-name = "CTRL_V_BUS_USB_HUB"; 109 }; 110 111 reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { 112 compatible = "regulator-fixed"; 113 pinctrl-names = "default"; 114 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; 115 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 116 enable-active-high; 117 off-on-delay-us = <100000>; 118 regulator-max-microvolt = <3300000>; 119 regulator-min-microvolt = <3300000>; 120 regulator-name = "SDIO_PWR_EN"; 121 startup-delay-us = <20000>; 122 }; 123 124 reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { 125 compatible = "regulator-gpio"; 126 pinctrl-names = "default"; 127 pinctrl-0 = <&pinctrl_usdhc2_vsel>; 128 gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; 129 regulator-max-microvolt = <3300000>; 130 regulator-min-microvolt = <1800000>; 131 states = <1800000 0x1>, 132 <3300000 0x0>; 133 regulator-name = "PMIC_SD2_VSEL"; 134 }; 135 136 reg_wifi_en: regulator-wifi-en { 137 compatible = "regulator-fixed"; 138 /* CTRL_EN_WIFI */ 139 gpios = <&som_gpio_expander_1 7 GPIO_ACTIVE_HIGH>; 140 enable-active-high; 141 regulator-max-microvolt = <3300000>; 142 regulator-min-microvolt = <3300000>; 143 regulator-name = "CTRL_EN_WIFI"; 144 startup-delay-us = <2000>; 145 }; 146 147 reserved-memory { 148 #address-cells = <2>; 149 #size-cells = <2>; 150 ranges; 151 152 linux_cma: linux,cma { 153 compatible = "shared-dma-pool"; 154 reusable; 155 size = <0 0x3c000000>; 156 alloc-ranges = <0 0x80000000 0 0x7F000000>; 157 linux,cma-default; 158 }; 159 }; 160}; 161 162/* SMARC GBE0 */ 163&enetc_port0 { 164 pinctrl-names = "default"; 165 pinctrl-0 = <&pinctrl_enetc0>, <&pinctrl_enetc0_1588_tmr>; 166 phy-handle = <ðphy1>; 167 phy-mode = "rgmii-id"; 168}; 169 170/* SMARC GBE1 */ 171&enetc_port1 { 172 pinctrl-names = "default"; 173 pinctrl-0 = <&pinctrl_enetc1>, <&pinctrl_enetc1_1588_tmr>; 174 phy-handle = <ðphy2>; 175 phy-mode = "rgmii-id"; 176}; 177 178/* SMARC CAN0 */ 179&flexcan1 { 180 pinctrl-names = "default"; 181 pinctrl-0 = <&pinctrl_flexcan1>; 182}; 183 184/* SMARC CAN1 */ 185&flexcan2 { 186 pinctrl-names = "default"; 187 pinctrl-0 = <&pinctrl_flexcan2>; 188}; 189 190&gpio1 { 191 gpio-line-names = "", /* 0 */ 192 "", 193 "SMARC_I2C_GP_CK", 194 "SMARC_I2C_GP_DAT", 195 "", 196 "", 197 "", 198 "", 199 "", 200 "", 201 "", /* 10 */ 202 "", 203 "", 204 "", 205 "CTRL_IO_EXP_INT_B"; 206 status = "okay"; 207}; 208 209&gpio2 { 210 gpio-line-names = "SMARC_SPI0_CS0#", /* 0 */ 211 "", 212 "", 213 "", 214 "", 215 "", 216 "SMARC_GPIO5", 217 "", 218 "I2C_CAM_DAT", 219 "I2C_CAM_CK", 220 "SMARC_GPIO12", /* 10 */ 221 "SMARC_GPIO13", 222 "", 223 "", 224 "", 225 "", 226 "", 227 "", 228 "SMARC_SPI1_CS0#", 229 "", 230 "", /* 20 */ 231 "", 232 "SMARC_I2C_LCD_DAT", 233 "SMARC_I2C_LCD_CK", 234 "SMARC_SPI0_CS1#", 235 "", 236 "", 237 "", 238 "SMARC_I2C_PM_DAT", 239 "SMARC_I2C_PM_CK", 240 "I2C_SOM_DAT", /* 30 */ 241 "I2C_SOM_CK"; 242 status = "okay"; 243}; 244 245&gpio3 { 246 gpio-line-names = "SMARC_SDIO_CD#", /* 0 */ 247 "", 248 "", 249 "", 250 "", 251 "", 252 "", 253 "SMARC_SDIO_PWR_EN", 254 "", 255 "", 256 "", /* 10 */ 257 "", 258 "", 259 "", 260 "", 261 "", 262 "", 263 "", 264 "", 265 "", 266 "PMIC_SD2_VSEL"; 267 status = "okay"; 268}; 269 270&gpio4 { 271 gpio-line-names = "", /* 0 */ 272 "", 273 "", 274 "", 275 "", 276 "", 277 "", 278 "", 279 "", 280 "", 281 "", /* 10 */ 282 "", 283 "", 284 "", 285 "SMARC_GPIO11", 286 "SMARC_GPIO10", 287 "", 288 "", 289 "", 290 "", 291 "", /* 20 */ 292 "", 293 "", 294 "", 295 "", 296 "", 297 "", 298 "", 299 "SMARC_SMB_ALERT#"; 300 status = "okay"; 301}; 302 303&gpio5 { 304 gpio-line-names = "SMARC_GPIO2", /* 0 */ 305 "SMARC_GPIO3", 306 "SMARC_GPIO4", 307 "SMARC_GPIO6", 308 "", 309 "", 310 "", 311 "", 312 "SMARC_GPIO9", 313 "SMARC_GPIO7", 314 "SMARC_GPIO8", /* 10 */ 315 "SMARC_SPI1_CS1#", 316 "", 317 "SPI1_TPM_CS#"; 318 status = "okay"; 319}; 320 321/* SMARC I2C_GP */ 322&lpi2c2 { 323 pinctrl-names = "default", "gpio"; 324 pinctrl-0 = <&pinctrl_lpi2c2>; 325 pinctrl-1 = <&pinctrl_lpi2c2_gpio>; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 clock-frequency = <400000>; 329 scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 330 sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 331 status = "okay"; 332 333 eeprom@50 { 334 compatible = "st,24c32", "atmel,24c32"; 335 reg = <0x50>; 336 pagesize = <32>; 337 }; 338}; 339 340/* SMARC I2C_PM */ 341&lpi2c3 { 342 pinctrl-names = "default", "gpio"; 343 pinctrl-0 = <&pinctrl_lpi2c3>; 344 pinctrl-1 = <&pinctrl_lpi2c3_gpio>; 345 #address-cells = <1>; 346 #size-cells = <0>; 347 clock-frequency = <400000>; 348 scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 349 sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 350}; 351 352/* I2C_SOM */ 353&lpi2c4 { 354 pinctrl-names = "default", "gpio"; 355 pinctrl-0 = <&pinctrl_lpi2c4>, <&pinctrl_ctrl_io_exp_int_b>; 356 pinctrl-1 = <&pinctrl_lpi2c4_gpio>, <&pinctrl_ctrl_io_exp_int_b>; 357 #address-cells = <1>; 358 #size-cells = <0>; 359 clock-frequency = <400000>; 360 scl-gpios = <&gpio2 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 361 sda-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 362 status = "okay"; 363 364 som_gpio_expander_0: gpio@20 { 365 compatible = "nxp,pcal6408"; 366 reg = <0x20>; 367 #interrupt-cells = <2>; 368 interrupt-controller; 369 interrupt-parent = <&gpio1>; 370 interrupts = <14 IRQ_TYPE_LEVEL_LOW>; 371 #gpio-cells = <2>; 372 gpio-controller; 373 gpio-line-names = 374 "SMARC_PCIE_WAKE#", /* 0 */ 375 "SMARC_PCIE_B_RST#", 376 "SMARC_PCIE_A_RST#", 377 "SMARC_USB0_OTG_ID", 378 "SMARC_USB0_EN", /* SMARC USB0_EN_OC# - Open Drain Output */ 379 "SMARC_USB0_OC#", /* SMARC USB0_EN_OC# - Over-Current Sense Input */ 380 "", 381 "SMARC_PCIE_C_RST#"; 382 }; 383 384 som_gpio_expander_1: gpio@21 { 385 compatible = "nxp,pcal6416"; 386 reg = <0x21>; 387 #interrupt-cells = <2>; 388 interrupt-controller; 389 interrupt-parent = <&gpio1>; 390 interrupts = <14 IRQ_TYPE_LEVEL_LOW>; 391 #gpio-cells = <2>; 392 gpio-controller; 393 gpio-line-names = 394 "SMARC_GPIO0", /* 0 */ 395 "SMARC_GPIO1", 396 "SMARC_LCD0_VDD_EN", 397 "SMARC_LCD0_BKLT_EN", 398 "SMARC_LCD1_VDD_EN", 399 "SMARC_LCD1_BKLT_EN", 400 "", 401 "", 402 "", 403 "", 404 "", /* 10 */ 405 "", 406 "", 407 "", 408 "", 409 "", 410 "", 411 "SMARC_SDIO_WP"; 412 }; 413 414 embedded-controller@28 { 415 compatible = "toradex,smarc-imx95-ec", "toradex,smarc-ec"; 416 reg = <0x28>; 417 }; 418 419 som_ec_gpio_expander: gpio@29 { 420 compatible = "toradex,ecgpiol16", "nxp,pcal6416"; 421 reg = <0x29>; 422 pinctrl-names = "default"; 423 pinctrl-0 = <&pinctrl_ec_int>; 424 #interrupt-cells = <2>; 425 interrupt-controller; 426 interrupt-parent = <&gpio1>; 427 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 428 #gpio-cells = <2>; 429 gpio-controller; 430 gpio-line-names = 431 "SMARC_CHARGER_PRSNT#", 432 "SMARC_CHARGING#", 433 "SMARC_LID#", 434 "SMARC_BATLOW#", 435 "SMARC_SLEEP#"; 436 }; 437 438 /* SMARC DP0 */ 439 som_dsi2dp_bridge: bridge@2c { 440 compatible = "ti,sn65dsi86"; 441 reg = <0x2c>; 442 clocks = <&clk_dsi2dp_bridge>; 443 clock-names = "refclk"; 444 vcc-supply = <®_module_dp_1p2v>; 445 vcca-supply = <®_module_dp_1p2v>; 446 vccio-supply = <®_module_1p8v>; 447 vpll-supply = <®_module_1p8v>; 448 status = "disabled"; 449 450 ports { 451 #address-cells = <1>; 452 #size-cells = <0>; 453 454 port@0 { 455 reg = <0>; 456 457 sn65dsi86_in: endpoint { 458 }; 459 }; 460 461 port@1 { 462 reg = <1>; 463 464 sn65dsi86_out: endpoint { 465 data-lanes = <3 2 1 0>; 466 }; 467 }; 468 }; 469 }; 470 471 rtc_i2c: rtc@32 { 472 compatible = "epson,rx8130"; 473 reg = <0x32>; 474 }; 475 476 temperature-sensor@48 { 477 compatible = "ti,tmp1075"; 478 reg = <0x48>; 479 }; 480 481 eeprom@50 { 482 compatible = "st,24c02", "atmel,24c02"; 483 reg = <0x50>; 484 pagesize = <16>; 485 }; 486}; 487 488/* SMARC I2C_LCD */ 489&lpi2c5 { 490 pinctrl-names = "default", "gpio"; 491 pinctrl-0 = <&pinctrl_lpi2c5>; 492 pinctrl-1 = <&pinctrl_lpi2c5_gpio>; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 clock-frequency = <100000>; 496 scl-gpios = <&gpio2 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 497 sda-gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 498}; 499 500/* I2C_CAM */ 501&lpi2c7 { 502 pinctrl-names = "default", "gpio"; 503 pinctrl-0 = <&pinctrl_lpi2c7>; 504 pinctrl-1 = <&pinctrl_lpi2c7_gpio>; 505 #address-cells = <1>; 506 #size-cells = <0>; 507 clock-frequency = <400000>; 508 scl-gpios = <&gpio2 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 509 sda-gpios = <&gpio2 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 510 status = "okay"; 511 512 i2c-mux@70 { 513 compatible = "nxp,pca9543"; 514 reg = <0x70>; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 518 /* SMARC I2C_CAM0 */ 519 i2c_cam0: i2c@0 { 520 reg = <0>; 521 #address-cells = <1>; 522 #size-cells = <0>; 523 }; 524 525 /* SMARC I2C_CAM1 */ 526 i2c_cam1: i2c@1 { 527 reg = <1>; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 }; 531 }; 532}; 533 534/* SMARC SPI1 */ 535&lpspi4 { 536 pinctrl-names = "default"; 537 pinctrl-0 = <&pinctrl_lpspi4>; 538 cs-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>, 539 <&gpio5 11 GPIO_ACTIVE_LOW>, 540 <&gpio5 13 GPIO_ACTIVE_LOW>; 541 status = "okay"; 542 543 som_tpm: tpm@2 { 544 compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; 545 reg = <0x2>; 546 spi-max-frequency = <18500000>; 547 }; 548}; 549 550/* SMARC SPI0 */ 551&lpspi6 { 552 pinctrl-names = "default"; 553 pinctrl-0 = <&pinctrl_lpspi6>; 554 cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>, 555 <&gpio2 24 GPIO_ACTIVE_LOW>; 556}; 557 558/* SMARC SER1, used as the Linux Console */ 559&lpuart1 { 560 pinctrl-names = "default"; 561 pinctrl-0 = <&pinctrl_uart1>; 562}; 563 564/* SMARC SER0 */ 565&lpuart2 { 566 pinctrl-names = "default"; 567 pinctrl-0 = <&pinctrl_uart2>; 568 uart-has-rtscts; 569}; 570 571/* SMARC SER3 */ 572&lpuart3 { 573 pinctrl-names = "default"; 574 pinctrl-0 = <&pinctrl_uart3>; 575}; 576 577/* SMARC MDIO, shared between all ethernet ports */ 578&netc_emdio { 579 pinctrl-names = "default"; 580 pinctrl-0 = <&pinctrl_emdio>; 581 582 ethphy1: ethernet-phy@1 { 583 reg = <1>; 584 interrupt-parent = <&som_gpio_expander_1>; 585 interrupts = <6 IRQ_TYPE_LEVEL_LOW>; 586 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 587 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 588 }; 589 590 ethphy2: ethernet-phy@2 { 591 reg = <2>; 592 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 593 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 594 }; 595}; 596 597&netcmix_blk_ctrl { 598 status = "okay"; 599}; 600 601&netc_blk_ctrl { 602 status = "okay"; 603}; 604 605&netc_timer { 606 status = "okay"; 607}; 608 609/* SMARC PCIE_A */ 610&pcie0 { 611 pinctrl-0 = <&pinctrl_pcie0>; 612 pinctrl-names = "default"; 613 reset-gpios = <&som_gpio_expander_0 2 GPIO_ACTIVE_LOW>; 614}; 615 616/* SMARC PCIE_B */ 617&pcie1 { 618 pinctrl-0 = <&pinctrl_pcie1>; 619 pinctrl-names = "default"; 620 reset-gpios = <&som_gpio_expander_0 1 GPIO_ACTIVE_LOW>; 621}; 622 623/* SMARC I2S0 */ 624&sai3 { 625 #sound-dai-cells = <0>; 626 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 627 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 628 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 629 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 630 <&scmi_clk IMX95_CLK_SAI3>; 631 assigned-clock-parents = <0>, <0>, <0>, <0>, 632 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 633 assigned-clock-rates = <3932160000>, 634 <3612672000>, <393216000>, 635 <361267200>, <12288000>; 636 fsl,sai-mclk-direction-output; 637}; 638 639&thermal_zones { 640 /* PF09 Main PMIC */ 641 pf09-thermal { 642 polling-delay = <2000>; 643 polling-delay-passive = <250>; 644 thermal-sensors = <&scmi_sensor 2>; 645 646 trips { 647 trip0 { 648 hysteresis = <2000>; 649 temperature = <155000>; 650 type = "critical"; 651 }; 652 }; 653 }; 654 655 /* PF53 VDD_ARM PMIC */ 656 pf53-arm-thermal { 657 polling-delay = <2000>; 658 polling-delay-passive = <250>; 659 thermal-sensors = <&scmi_sensor 4>; 660 661 trips { 662 trip0 { 663 hysteresis = <2000>; 664 temperature = <155000>; 665 type = "critical"; 666 }; 667 }; 668 }; 669 670 /* PF53 VDD_SOC PMIC */ 671 pf53-soc-thermal { 672 polling-delay = <2000>; 673 polling-delay-passive = <250>; 674 thermal-sensors = <&scmi_sensor 3>; 675 676 trips { 677 trip0 { 678 hysteresis = <2000>; 679 temperature = <155000>; 680 type = "critical"; 681 }; 682 }; 683 }; 684}; 685 686/* SMARC LCD0_BKLT_PWM */ 687&tpm3 { 688 pinctrl-names = "default"; 689 pinctrl-0 = <&pinctrl_lcd0_bklt_pwm>; 690}; 691 692/* SMARC LCD1_BKLT_PWM */ 693&tpm4 { 694 pinctrl-names = "default"; 695 pinctrl-0 = <&pinctrl_lcd1_bklt_pwm>; 696}; 697 698/* SMARC GPIO5 as PWM */ 699&tpm5 { 700 pinctrl-names = "default"; 701 pinctrl-0 = <&pinctrl_gpio5_pwm>; 702}; 703 704/* SMARC USB0 */ 705&usb2 { 706 adp-disable; 707 dr_mode = "otg"; 708 hnp-disable; 709 srp-disable; 710 usb-role-switch; 711 vbus-supply = <®_usb0_vbus>; 712 713 port { 714 usb0_otg_id: endpoint { 715 remote-endpoint = <&usb_dr_connector>; 716 }; 717 }; 718}; 719 720&usb3 { 721 fsl,disable-port-power-control; 722}; 723 724/* SMARC USB1..4 */ 725&usb3_dwc3 { 726 dr_mode = "host"; 727}; 728 729&usb3_phy { 730 vbus-supply = <®_usb1_vbus>; 731}; 732 733/* On-module eMMC */ 734&usdhc1 { 735 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 736 pinctrl-0 = <&pinctrl_usdhc1>; 737 pinctrl-1 = <&pinctrl_usdhc1>; 738 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 739 bus-width = <8>; 740 non-removable; 741 no-sdio; 742 no-sd; 743 status = "okay"; 744}; 745 746/* SMARC SDIO */ 747&usdhc2 { 748 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 749 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; 750 pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; 751 pinctrl-2 = <&pinctrl_usdhc2_200mhz>,<&pinctrl_usdhc2_cd>; 752 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd>; 753 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 754 vmmc-supply = <®_usdhc2_vmmc>; 755 vqmmc-supply = <®_usdhc2_vqmmc>; 756 wp-gpios = <&som_gpio_expander_1 15 GPIO_ACTIVE_HIGH>; 757}; 758 759/* On-module Wi-Fi */ 760&usdhc3 { 761 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 762 pinctrl-0 = <&pinctrl_usdhc3>; 763 pinctrl-1 = <&pinctrl_usdhc3>; 764 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 765 keep-power-in-suspend; 766 non-removable; 767 vmmc-supply = <®_wifi_en>; 768}; 769 770&scmi_bbm { 771 linux,code = <KEY_POWER>; 772}; 773 774&wdog3 { 775 fsl,ext-reset-output; 776 status = "okay"; 777}; 778 779&scmi_iomuxc { 780 /* SMARC CAM_MCK */ 781 pinctrl_cam_mck: cammckgrp { 782 fsl,pins = <IMX95_PAD_CCM_CLKO1__CCMSRCGPCMIX_TOP_CLKO_1 0x51e>; /* SMARC S6 - CAM_MCK */ 783 }; 784 785 pinctrl_ec_int: ecintgrp { 786 fsl,pins = <IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11 0x31e>; /* SAI1_TXFS - EC_MCU_INT# */ 787 }; 788 789 /* SMARC MDIO, shared between all ethernet ports */ 790 pinctrl_emdio: emdiogrp { 791 fsl,pins = <IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x50e>, /* SMARC S45 - MDIO_CLK */ 792 <IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e>; /* SMARC S46 - MDIO_DAT */ 793 }; 794 795 /* SMARC GBE0 */ 796 pinctrl_enetc0: enetc0grp { 797 fsl,pins = <IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e>, /* ENET1_TX_CTL */ 798 <IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e>, /* ENET1_TXC */ 799 <IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e>, /* ENET1_TDO */ 800 <IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e>, /* ENET1_TD1 */ 801 <IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e>, /* ENET1_TD2 */ 802 <IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e>, /* ENET1_TD3 */ 803 <IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e>, /* ENET1_RX_CTL */ 804 <IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e>, /* ENET1_RXC */ 805 <IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e>, /* ENET1_RD0 */ 806 <IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e>, /* ENET1_RD1 */ 807 <IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e>, /* ENET1_RD2 */ 808 <IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e>; /* ENET1_RD3 */ 809 }; 810 811 /* SMARC GBE0_SDP */ 812 pinctrl_enetc0_1588_tmr: enetc01588tmrgrp { 813 fsl,pins = <IMX95_PAD_CCM_CLKO2__NETCMIX_TOP_NETC_TMR_1588_PP1 0x51e>; /* SMARC P6 - GBE0_SDP */ 814 }; 815 816 /* SMARC GBE1 */ 817 pinctrl_enetc1: enetc1grp { 818 fsl,pins = <IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e>, /* ENET2_TX_CTL */ 819 <IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x58e>, /* ENET2_TXC */ 820 <IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x50e>, /* ENET2_TD0 */ 821 <IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x50e>, /* ENET2_TD1 */ 822 <IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x50e>, /* ENET2_TD2 */ 823 <IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x50e>, /* ENET2_TD3 */ 824 <IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e>, /* ENET2_RX_CTL */ 825 <IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x58e>, /* ENET2_RXC */ 826 <IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e>, /* ENET2_RD0 */ 827 <IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e>, /* ENET2_RD1 */ 828 <IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e>, /* ENET2_RD2 */ 829 <IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x57e>; /* ENET2_RD3 */ 830 }; 831 832 /* SMARC GBE1_SDP */ 833 pinctrl_enetc1_1588_tmr: enetc11588tmrgrp { 834 fsl,pins = <IMX95_PAD_CCM_CLKO4__NETCMIX_TOP_NETC_TMR_1588_PP2 0x51e>; /* SMARC P5 - GBE1_SDP */ 835 }; 836 837 /* SMARC CAN0 */ 838 pinctrl_flexcan1: flexcan1grp { 839 fsl,pins = <IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e>, /* SMARC P143 - CAN0_TX */ 840 <IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e>; /* SMARC P144 - CAN0_RX */ 841 }; 842 843 /* SMARC CAN1 */ 844 pinctrl_flexcan2: flexcan2grp { 845 fsl,pins = <IMX95_PAD_GPIO_IO25__CAN2_TX 0x39e>, /* SMARC P145 - CAN1_TX */ 846 <IMX95_PAD_GPIO_IO27__CAN2_RX 0x39e>; /* SMARC P146 - CAN1_RX */ 847 }; 848 849 /* SMARC GPIO2 */ 850 pinctrl_gpio2: gpio2grp { 851 fsl,pins = <IMX95_PAD_XSPI1_DATA0__GPIO5_IO_BIT0 0x31e>; /* SMARC P110 - GPIO2 */ 852 }; 853 854 /* SMARC GPIO3 */ 855 pinctrl_gpio3: gpio3grp { 856 fsl,pins = <IMX95_PAD_XSPI1_DATA1__GPIO5_IO_BIT1 0x31e>; /* SMARC P111 - GPIO3 */ 857 }; 858 859 /* SMARC GPIO4 */ 860 pinctrl_gpio4: gpio4grp { 861 fsl,pins = <IMX95_PAD_XSPI1_DATA2__GPIO5_IO_BIT2 0x31e>; /* SMARC P112 - GPIO4 */ 862 }; 863 864 /* SMARC GPIO5 */ 865 pinctrl_gpio5: gpio5grp { 866 fsl,pins = <IMX95_PAD_GPIO_IO06__GPIO2_IO_BIT6 0x31e>; /* SMARC P113 - GPIO5 */ 867 }; 868 869 /* SMARC GPIO5 as PWM */ 870 pinctrl_gpio5_pwm: gpio5pwmgrp { 871 fsl,pins = <IMX95_PAD_GPIO_IO06__TPM5_CH0 0x11e>; /* SMARC P113 - PWM_OUT */ 872 }; 873 874 /* SMARC GPIO6 */ 875 pinctrl_gpio6: gpio6grp { 876 fsl,pins = <IMX95_PAD_XSPI1_DATA3__GPIO5_IO_BIT3 0x31e>; /* SMARC P114 - GPIO6 */ 877 }; 878 879 /* SMARC GPIO7 */ 880 pinctrl_gpio7: gpio7grp { 881 fsl,pins = <IMX95_PAD_XSPI1_SCLK__GPIO5_IO_BIT9 0x31e>; /* SMARC P115 - GPIO7 */ 882 }; 883 884 /* SMARC GPIO8 */ 885 pinctrl_gpio8: gpio8grp { 886 fsl,pins = <IMX95_PAD_XSPI1_SS0_B__GPIO5_IO_BIT10 0x31e>; /* SMARC P116 - GPIO8 */ 887 }; 888 889 /* SMARC GPIO9 */ 890 pinctrl_gpio9: gpio9grp { 891 fsl,pins = <IMX95_PAD_XSPI1_DQS__GPIO5_IO_BIT8 0x31e>; /* SMARC P117 - GPIO9 */ 892 }; 893 894 /* SMARC GPIO10 */ 895 pinctrl_gpio10: gpio10grp { 896 fsl,pins = <IMX95_PAD_ENET2_MDIO__GPIO4_IO_BIT15 0x31e>; /* SMARC P118 - GPIO10 */ 897 }; 898 899 /* SMARC GPIO11 */ 900 pinctrl_gpio11: gpio11grp { 901 fsl,pins = <IMX95_PAD_ENET2_MDC__GPIO4_IO_BIT14 0x31e>; /* SMARC P119 - GPIO11 */ 902 }; 903 904 /* SMARC GPIO12 */ 905 pinctrl_gpio12: gpio12grp { 906 fsl,pins = <IMX95_PAD_GPIO_IO10__GPIO2_IO_BIT10 0x31e>; /* SMARC S142 - GPIO12 */ 907 }; 908 909 /* SMARC GPIO13 */ 910 pinctrl_gpio13: gpio13grp { 911 fsl,pins = <IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11 0x31e>; /* SMARC S123 - GPIO13 */ 912 }; 913 914 pinctrl_ctrl_io_exp_int_b: ioexpintgrp { 915 fsl,pins = <IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14 0x31e>; /* CTRL_IO_EXP_INT_B */ 916 }; 917 918 /* SMARC LCD0_BKLT_PWM */ 919 pinctrl_lcd0_bklt_pwm: lcd0bkltpwmgrp { 920 fsl,pins = <IMX95_PAD_GPIO_IO12__TPM3_CH2 0x51e>; /* SMARC S141 - LCD0_BKLT_PWM */ 921 }; 922 923 /* SMARC LCD1_BKLT_PWM */ 924 pinctrl_lcd1_bklt_pwm: lcd1bkltpwmgrp { 925 fsl,pins = <IMX95_PAD_GPIO_IO13__TPM4_CH2 0x51e>; /* SMARC S122 - LCD1_BKLT_PWM */ 926 }; 927 928 /* SMARC I2C_GP */ 929 pinctrl_lpi2c2: lpi2c2grp { 930 fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40001b9e>, /* SMARC S48 - I2C_GP_CK */ 931 <IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40001b9e>; /* SMARC S49 - I2C_GP_DAT */ 932 }; 933 934 /* SMARC I2C_GP as GPIOs */ 935 pinctrl_lpi2c2_gpio: lpi2c2gpiogrp { 936 fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_BIT2 0x40001b9e>, /* SMARC S48 - I2C_GP_CK */ 937 <IMX95_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_BIT3 0x40001b9e>; /* SMARC S49 - I2C_GP_DAT */ 938 }; 939 940 /* SMARC I2C_PM */ 941 pinctrl_lpi2c3: lpi2c3grp { 942 fsl,pins = <IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40001b9e>, /* SMARC P122 - I2C_PM_DAT */ 943 <IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40001b9e>; /* SMARC P121 - I2C_PM_CK */ 944 }; 945 946 /* SMARC I2C_PM as GPIOs */ 947 pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { 948 fsl,pins = <IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x40001b9e>, /* SMARC P122 - I2C_PM_DAT */ 949 <IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x40001b9e>; /* SMARC P121 - I2C_PM_CK */ 950 }; 951 952 /* I2C_SOM */ 953 pinctrl_lpi2c4: lpi2c4grp { 954 fsl,pins = <IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40001b9e>, /* I2C_SOM_CK */ 955 <IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40001b9e>; /* I2C_SOM_DAT */ 956 }; 957 958 /* I2C_SOM as GPIOs */ 959 pinctrl_lpi2c4_gpio: lpi2c4gpiogrp { 960 fsl,pins = <IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31 0x40001b9e>, /* I2C_SOM_CK */ 961 <IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30 0x40001b9e>; /* I2C_SOM_DAT */ 962 }; 963 964 /* SMARC I2C_LCD */ 965 pinctrl_lpi2c5: lpi2c5grp { 966 fsl,pins = <IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x40001b9e>, /* SMARC S140 - I2C_LCD_DAT */ 967 <IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x40001b9e>; /* SMARC S139 - I2C_LCD_CK */ 968 }; 969 970 /* SMARC I2C_LCD as GPIOs */ 971 pinctrl_lpi2c5_gpio: lpi2c5gpiogrp { 972 fsl,pins = <IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22 0x40001b9e>, /* SMARC S140 - I2C_LCD_DAT */ 973 <IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23 0x40001b9e>; /* SMARC S139 - I2C_LCD_CK */ 974 }; 975 976 /* I2C_CAM */ 977 pinctrl_lpi2c7: lpi2c7grp { 978 fsl,pins = <IMX95_PAD_GPIO_IO08__LPI2C7_SDA 0x40001b9e>, /* I2C_CAM_DAT */ 979 <IMX95_PAD_GPIO_IO09__LPI2C7_SCL 0x40001b9e>; /* I2C_CAM_CK */ 980 }; 981 982 /* I2C_CAM as GPIOs */ 983 pinctrl_lpi2c7_gpio: lpi2c7gpiogrp { 984 fsl,pins = <IMX95_PAD_GPIO_IO08__GPIO2_IO_BIT8 0x40001b9e>, /* I2C_CAM_DAT */ 985 <IMX95_PAD_GPIO_IO09__GPIO2_IO_BIT9 0x40001b9e>; /* I2C_CAM_CK */ 986 }; 987 988 /* SMARC SPI1 */ 989 pinctrl_lpspi4: lpspi4grp { 990 fsl,pins = <IMX95_PAD_GPIO_IO37__LPSPI4_SCK 0x3fe>, /* SMARC P56 - SPI1_CK */ 991 <IMX95_PAD_GPIO_IO36__LPSPI4_SOUT 0x3fe>, /* SMARC P58 - SPI1_DO */ 992 <IMX95_PAD_GPIO_IO19__LPSPI4_SIN 0x3fe>, /* SMARC P57 - SPI1_DIN */ 993 <IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x3fe>, /* SPI1_TPM_CS# */ 994 <IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x3fe>, /* SMARC P54 - SPI1_CS0# */ 995 <IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x3fe>; /* SMARC P55 - SPI1_CS1# */ 996 }; 997 998 /* SMARC SPI0 */ 999 pinctrl_lpspi6: lpspi6grp { 1000 fsl,pins = <IMX95_PAD_GPIO_IO00__GPIO2_IO_BIT0 0x3fe>, /* SMARC P43 - SPI0_CS0# */ 1001 <IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24 0x3fe>, /* SMARC P31 - SPI0_CS1# */ 1002 <IMX95_PAD_GPIO_IO01__LPSPI6_SIN 0x3fe>, /* SMARC P45 - SPI0_DIN */ 1003 <IMX95_PAD_GPIO_IO02__LPSPI6_SOUT 0x3fe>, /* SMARC P46 - SPI0_DO */ 1004 <IMX95_PAD_GPIO_IO03__LPSPI6_SCK 0x3fe>; /* SMARC P44 - SPI0_CK */ 1005 }; 1006 1007 /* SMARC PCIE_A */ 1008 pinctrl_pcie0: pcie0grp { 1009 fsl,pins = <IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x40001b1e>; /* SMARC P78 - PCIE_A_CKREQ# */ 1010 }; 1011 1012 /* SMARC PCIE_B */ 1013 pinctrl_pcie1: pcie1grp { 1014 fsl,pins = <IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x40001b1e>; /* SMARC P77 - PCIE_B_CKREQ# */ 1015 }; 1016 1017 /* SMARC I2S0 */ 1018 pinctrl_sai3: sai3grp { 1019 fsl,pins = <IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x11e>, /* SMARC S38 - I2S0_CK */ 1020 <IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x11e>, /* SMARC S41 - I2S0_SDIN */ 1021 <IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x11e>, /* SMARC S40 - I2S0_SDOUT */ 1022 <IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x11e>; /* SMARC S39 - I2S0_LRCK */ 1023 }; 1024 1025 /* SMARC AUDIO_MCK */ 1026 pinctrl_sai3_mclk: sai3mclkgrp { 1027 fsl,pins = <IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e>; /* SMARC S42 - AUDIO_MCK */ 1028 }; 1029 1030 /* SMARC I2S2 */ 1031 pinctrl_sai5: sai5grp { 1032 fsl,pins = <IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK 0x11e>, /* SMARC S53 - I2S2_CK */ 1033 <IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0 0x11e>, /* SMARC S51 - I2S2_SDOUT */ 1034 <IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0 0x11e>, /* SMARC S52 - I2S2_SDIN */ 1035 <IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC 0x11e>; /* SMARC S50 - I2S2_LRCK */ 1036 }; 1037 1038 /* SMARC SMB_ALERT# */ 1039 pinctrl_smb_alert_gpio: smbalertgrp { 1040 fsl,pins = <IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x31e>; /* SMARC P1 - SMB_ALERT# */ 1041 }; 1042 1043 /* SMARC SER1, used as the Linux Console */ 1044 pinctrl_uart1: uart1grp { 1045 fsl,pins = <IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e>, /* SMARC P134 - SER1_TX */ 1046 <IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e>; /* SMARC P135 - SER1_RX */ 1047 }; 1048 1049 /* SMARC SER0 */ 1050 pinctrl_uart2: uart2grp { 1051 fsl,pins = <IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPUART2_CTS_B 0x31e>, /* SMARC P132 - SER0_CTS# */ 1052 <IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPUART2_RTS_B 0x31e>, /* SMARC P131 - SER0_RTS# */ 1053 <IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x31e>, /* SMARC P130 - SER0_RX */ 1054 <IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x31e>; /* SMARC P129 - SER0_TX */ 1055 }; 1056 1057 /* SMARC SER3 */ 1058 pinctrl_uart3: uart3grp { 1059 fsl,pins = <IMX95_PAD_GPIO_IO14__LPUART3_TX 0x31e>, /* SMARC P140 - SER3_TX */ 1060 <IMX95_PAD_GPIO_IO15__LPUART3_RX 0x31e>; /* SMARC P141 - SER3_RX */ 1061 }; 1062 1063 /* On-module eMMC */ 1064 pinctrl_usdhc1: usdhc1grp { 1065 fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e>, /* SD1_CLK */ 1066 <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e>, /* SD1_CMD */ 1067 <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e>, /* SD1_DATA0 */ 1068 <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e>, /* SD1_DATA1 */ 1069 <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e>, /* SD1_DATA2 */ 1070 <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e>, /* SD1_DATA3 */ 1071 <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e>, /* SD1_DATA4 */ 1072 <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e>, /* SD1_DATA5 */ 1073 <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e>, /* SD1_DATA6 */ 1074 <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e>, /* SD1_DATA7 */ 1075 <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e>; /* SD1_STROBE */ 1076 }; 1077 1078 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1079 fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe>, /* SD1_CLK */ 1080 <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe>, /* SD1_CMD */ 1081 <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe>, /* SD1_DATA0 */ 1082 <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe>, /* SD1_DATA1 */ 1083 <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe>, /* SD1_DATA2 */ 1084 <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe>, /* SD1_DATA3 */ 1085 <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe>, /* SD1_DATA4 */ 1086 <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe>, /* SD1_DATA5 */ 1087 <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe>, /* SD1_DATA6 */ 1088 <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe>, /* SD1_DATA7 */ 1089 <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe>; /* SD1_STROBE */ 1090 }; 1091 1092 /* SMARC SDIO */ 1093 pinctrl_usdhc2: usdhc2grp { 1094 fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e>, /* SMARC P36 - SDIO_CK */ 1095 <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e>, /* SMARC P34 - SDIO_CMD */ 1096 <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e>, /* SMARC P39 - SDIO_D0 */ 1097 <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e>, /* SMARC P40 - SDIO_D1 */ 1098 <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e>, /* SMARC P41 - SDIO_D2 */ 1099 <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e>; /* SMARC P42 - SDIO_D3 */ 1100 }; 1101 1102 /* SMARC SDIO */ 1103 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1104 fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe>, /* SMARC P36 - SDIO_CK */ 1105 <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe>, /* SMARC P34 - SDIO_CMD */ 1106 <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe>, /* SMARC P39 - SDIO_D0 */ 1107 <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe>, /* SMARC P40 - SDIO_D1 */ 1108 <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe>, /* SMARC P41 - SDIO_D2 */ 1109 <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe>; /* SMARC P42 - SDIO_D3 */ 1110 }; 1111 1112 /* SMARC SDIO */ 1113 pinctrl_usdhc2_sleep: usdhc2-sleepgrp { 1114 fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x400>, /* SMARC P36 - SDIO_CK */ 1115 <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x400>, /* SMARC P34 - SDIO_CMD */ 1116 <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x400>, /* SMARC P39 - SDIO_D0 */ 1117 <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x400>, /* SMARC P40 - SDIO_D1 */ 1118 <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x400>, /* SMARC P41 - SDIO_D2 */ 1119 <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x400>; /* SMARC P42 - SDIO_D3 */ 1120 }; 1121 1122 /* SMARC SDIO_CD# */ 1123 pinctrl_usdhc2_cd: usdhc2-cdgrp { 1124 fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>; /* SMARC P35 - SDIO_CD# */ 1125 }; 1126 1127 /* SMARC SDIO_PWR_EN */ 1128 pinctrl_usdhc2_pwr_en: usdhc2-pwrengrp { 1129 fsl,pins = <IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x11e>; /* SMARC P37 - SDIO_PWR_EN */ 1130 }; 1131 1132 pinctrl_usdhc2_vsel: usdhc2-vselgrp { 1133 fsl,pins = <IMX95_PAD_SD2_VSELECT__GPIO3_IO_BIT19 0x4>; /* PMIC_SD2_VSEL */ 1134 }; 1135 1136 /* On-module Wi-Fi */ 1137 pinctrl_usdhc3: usdhc3grp { 1138 fsl,pins = <IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e>, /* SD3_CLK */ 1139 <IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e>, /* SD3_CMD */ 1140 <IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e>, /* SD3_DATA0 */ 1141 <IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e>, /* SD3_DATA1 */ 1142 <IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e>, /* SD3_DATA2 */ 1143 <IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e>; /* SD3_DATA3 */ 1144 }; 1145 1146 /* On-module Wi-Fi */ 1147 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1148 fsl,pins = <IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe>, /* SD3_CLK */ 1149 <IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe>, /* SD3_CMD */ 1150 <IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe>, /* SD3_DATA1 */ 1151 <IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe>, /* SD3_DATA2 */ 1152 <IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe>, /* SD3_DATA3 */ 1153 <IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe>; /* SD3_DATA4 */ 1154 }; 1155}; 1156