1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2025 PHYTEC Messtechnik GmbH 4 */ 5 6#include <dt-bindings/net/ti-dp83867.h> 7#include "imx95.dtsi" 8 9/ { 10 model = "PHYTEC phyCORE-i.MX95 FPSC"; 11 compatible = "phytec,imx95-phycore-fpsc", "fsl,imx95"; 12 13 aliases { 14 ethernet1 = &enetc_port1; 15 i2c1 = &lpi2c2; 16 i2c2 = &lpi2c5; 17 i2c3 = &lpi2c3; 18 i2c4 = &lpi2c4; 19 i2c5 = &lpi2c1; 20 rtc0 = &rv3028; 21 rtc1 = &scmi_bbm; 22 }; 23 24 memory@80000000 { 25 device_type = "memory"; 26 reg = <0x00000000 0x80000000 0x00000001 0x00000000>; 27 }; 28 29 reg_nvcc_aon: regulator-nvcc-aon { 30 compatible = "regulator-fixed"; 31 regulator-always-on; 32 regulator-boot-on; 33 regulator-max-microvolt = <1800000>; 34 regulator-min-microvolt = <1800000>; 35 regulator-name = "VDD_IO"; 36 }; 37 38 reg_usdhc2_vmmc: regulator-usdhc2 { 39 compatible = "regulator-fixed"; 40 off-on-delay-us = <12000>; 41 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 42 pinctrl-names = "default"; 43 regulator-max-microvolt = <3300000>; 44 regulator-min-microvolt = <3300000>; 45 regulator-name = "VDDSW_SD2"; 46 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 47 enable-active-high; 48 }; 49 50 reserved-memory { 51 ranges; 52 #address-cells = <2>; 53 #size-cells = <2>; 54 55 linux,cma { 56 compatible = "shared-dma-pool"; 57 alloc-ranges = <0 0x80000000 0 0x7f000000>; 58 reusable; 59 size = <0 0x3c000000>; 60 linux,cma-default; 61 }; 62 }; 63}; 64 65&enetc_port0 { /* FPSC RGMII2 */ 66 phy-mode = "rgmii-id"; 67 pinctrl-0 = <&pinctrl_enetc0>; 68 pinctrl-names = "default"; 69}; 70 71&enetc_port1 { 72 phy-handle = <ðphy1>; 73 phy-mode = "rgmii-id"; 74 pinctrl-0 = <&pinctrl_enetc1>; 75 pinctrl-names = "default"; 76 status = "okay"; 77}; 78 79&flexcan1 { /* FPSC CAN1 */ 80 pinctrl-0 = <&pinctrl_flexcan1>; 81 pinctrl-names = "default"; 82}; 83 84&flexcan2 { /* FPSC CAN2 */ 85 pinctrl-0 = <&pinctrl_flexcan2>; 86 pinctrl-names = "default"; 87}; 88 89&flexspi1 { /* FPSC QSPI */ 90 pinctrl-0 = <&pinctrl_flexspi>; 91 pinctrl-names = "default"; 92}; 93 94&gpio1 { /* FPSC GPIO */ 95 gpio-line-names = "", "", "", "", "GPIO2", 96 "GPIO1", "", "", "", "", 97 "PCIE1_nPERST", "USB1_PWR_EN", "GPIO3", "USB2_PWR_EN", "PCIE2_nPERST"; 98 pinctrl-0 = <&pinctrl_gpio1>; 99 pinctrl-names = "default"; 100 status = "okay"; 101}; 102 103&gpio2 { /* FPSC GPIO */ 104 gpio-line-names = "", "", "", "", "", 105 "", "", "", "", "", 106 "", "", "", "", "", 107 "", "RGMII2_nINT", "GPIO4"; 108 pinctrl-0 = <&pinctrl_gpio2>; 109 pinctrl-names = "default"; 110}; 111 112&gpio3 { 113 gpio-line-names = "", "", "", "", "", 114 "", "", "SD2_RESET_B"; 115}; 116 117&gpio4 { 118 gpio-line-names = "ENET2_nINT"; 119}; 120 121&gpio5 { 122 gpio-line-names = "", "", "", "", "", 123 "", "", "", "", "", 124 "", "", "", "USB1_OC", "USB2_OC"; 125}; 126 127&lpi2c1 { /* FPSC I2C5 */ 128 clock-frequency = <400000>; 129 pinctrl-0 = <&pinctrl_lpi2c1>; 130 pinctrl-names = "default"; 131 status = "okay"; 132 133 dram_sense: temperature-sensor@48 { 134 compatible = "ti,tmp102"; 135 reg = <0x48>; 136 #thermal-sensor-cells = <1>; 137 }; 138 139 emmc_sense: temperature-sensor@49 { 140 compatible = "ti,tmp102"; 141 reg = <0x49>; 142 #thermal-sensor-cells = <1>; 143 }; 144 145 ethphy_sense: temperature-sensor@4a { 146 compatible = "ti,tmp102"; 147 reg = <0x4a>; 148 #thermal-sensor-cells = <1>; 149 }; 150 151 pmic_sense: temperature-sensor@4b { 152 compatible = "ti,tmp102"; 153 reg = <0x4b>; 154 #thermal-sensor-cells = <1>; 155 }; 156 157 /* User EEPROM */ 158 eeprom@50 { 159 compatible = "st,24c32", "atmel,24c32"; 160 reg = <0x50>; 161 pagesize = <32>; 162 vcc-supply = <®_nvcc_aon>; 163 }; 164 165 /* Factory EEPROM */ 166 eeprom@51 { 167 compatible = "st,24c32", "atmel,24c32"; 168 reg = <0x51>; 169 pagesize = <32>; 170 vcc-supply = <®_nvcc_aon>; 171 }; 172 173 rv3028: rtc@52 { 174 compatible = "microcrystal,rv3028"; 175 reg = <0x52>; 176 }; 177 178 /* User EEPROM ID page */ 179 eeprom@58 { 180 compatible = "st,24c32", "atmel,24c32"; 181 reg = <0x58>; 182 pagesize = <32>; 183 vcc-supply = <®_nvcc_aon>; 184 }; 185}; 186 187&lpi2c2 { /* FPSC I2C1 */ 188 clock-frequency = <400000>; 189 pinctrl-0 = <&pinctrl_lpi2c2>; 190 pinctrl-names = "default"; 191}; 192 193&lpi2c3 { /* FPSC I2C3 */ 194 clock-frequency = <400000>; 195 pinctrl-0 = <&pinctrl_lpi2c3>; 196 pinctrl-names = "default"; 197}; 198 199&lpi2c4 { /* FPSC I2C4 */ 200 clock-frequency = <400000>; 201 pinctrl-0 = <&pinctrl_lpi2c4>; 202 pinctrl-names = "default"; 203}; 204 205&lpi2c5 { /* FPSC I2C2 */ 206 clock-frequency = <400000>; 207 pinctrl-0 = <&pinctrl_lpi2c5>; 208 pinctrl-names = "default"; 209}; 210 211&lpspi3 { /* FPSC SPI2 */ 212 pinctrl-0 = <&pinctrl_lpspi3>; 213 pinctrl-names = "default"; 214}; 215 216&lpspi4 { /* FPSC SPI3 */ 217 pinctrl-0 = <&pinctrl_lpspi4>; 218 pinctrl-names = "default"; 219}; 220 221&lpspi7 { /* FPSC SPI1 */ 222 pinctrl-0 = <&pinctrl_lpspi7>; 223 pinctrl-names = "default"; 224}; 225 226&lpuart5 { /* FPSC UART2 */ 227 pinctrl-0 = <&pinctrl_lpuart5>; 228 pinctrl-names = "default"; 229}; 230 231&lpuart7 { /* FPSC UART3 */ 232 pinctrl-0 = <&pinctrl_lpuart7>; 233 pinctrl-names = "default"; 234}; 235 236&lpuart8 { /* FPSC UART1 */ 237 pinctrl-0 = <&pinctrl_lpuart8>; 238 pinctrl-names = "default"; 239}; 240 241&netc_blk_ctrl { 242 status = "okay"; 243}; 244 245&netc_emdio { /* FPSC RGMII2 */ 246 pinctrl-0 = <&pinctrl_emdio>; 247 pinctrl-names = "default"; 248 status = "okay"; 249 250 ethphy1: ethernet-phy@0 { 251 compatible = "ethernet-phy-ieee802.3-c22"; 252 reg = <0x0>; 253 interrupt-parent = <&gpio4>; 254 interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 255 enet-phy-lane-no-swap; 256 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 257 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 258 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 259 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 260 }; 261}; 262 263&netcmix_blk_ctrl { 264 status = "okay"; 265}; 266 267&pcie0 { /* FPSC PCIE1 */ 268 pinctrl-0 = <&pinctrl_pcie0>; 269 pinctrl-names = "default"; 270}; 271 272&pcie1 { /* FPSC PCIE2 */ 273 pinctrl-0 = <&pinctrl_pcie1>; 274 pinctrl-names = "default"; 275}; 276 277&sai5 { /* FPSC SAI1 */ 278 pinctrl-0 = <&pinctrl_sai5>; 279 pintrc-names = "default"; 280}; 281 282&scmi_iomuxc { 283 pinctrl_emdio: emdiogrp { 284 fsl,pins = < 285 IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e /* RGMII2_MDIO */ 286 IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x502 /* RGMII2_MDC */ 287 >; 288 }; 289 290 pinctrl_enetc0: enetc0grp { 291 fsl,pins = < 292 IMX95_PAD_GPIO_IO16__GPIO2_IO_BIT16 0x31e /* RGMII2_nINT */ 293 IMX95_PAD_CCM_CLKO3__NETCMIX_TOP_NETC_TMR_1588_TRIG2 0x31e /* RGMII2_EVENT_IN */ 294 IMX95_PAD_CCM_CLKO4__NETCMIX_TOP_NETC_TMR_1588_PP2 0x31e /* RGMII2_EVENT_OUT */ 295 296 IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x57e /* RGMII2_TX_3 */ 297 IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x57e /* RGMII2_TX_2 */ 298 IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x57e /* RGMII2_TX_1 */ 299 IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x57e /* RGMII2_TX_0 */ 300 IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e /* RGMII2_TX_CTL */ 301 IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e /* RGMII2_TXC */ 302 IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e /* RGMII2_RX_3 */ 303 IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e /* RGMII2_RX_2 */ 304 IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e /* RGMII2_RX_1 */ 305 IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e /* RGMII2_RX_0 */ 306 IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e /* RGMII2_RX_CTL */ 307 IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e /* RGMII2_RXC */ 308 >; 309 }; 310 311 pinctrl_enetc1: enetc1grp { 312 fsl,pins = < 313 IMX95_PAD_ENET1_MDC__GPIO4_IO_BIT0 0x31e 314 IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x57e 315 IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x57e 316 IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x57e 317 IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x57e 318 IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e 319 IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x58e 320 IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e 321 IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e 322 IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e 323 IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x57e 324 IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e 325 IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x58e 326 >; 327 }; 328 329 pinctrl_flexcan1: flexcan1grp { 330 fsl,pins = < 331 IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x51e /* CAN1_TX */ 332 IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x51e /* CAN1_RX */ 333 >; 334 }; 335 336 pinctrl_flexcan2: flexcan2grp { 337 fsl,pins = < 338 IMX95_PAD_GPIO_IO25__CAN2_TX 0x51e /* CAN2_TX */ 339 IMX95_PAD_GPIO_IO27__CAN2_RX 0x51e /* CAN2_RX */ 340 >; 341 }; 342 343 pinctrl_flexspi: flexspigrp { 344 fsl,pins = < 345 IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x3fe /* QSPI_CE */ 346 IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 0x3fe /* QSPI_CLK */ 347 IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0 0x3fe /* QSPI_DATA_0 */ 348 IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1 0x3fe /* QSPI_DATA_1 */ 349 IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2 0x3fe /* QSPI_DATA_2 */ 350 IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3 0x3fe /* QSPI_DATA_3 */ 351 IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS 0x3fe /* QSPI_DQS */ 352 >; 353 }; 354 355 pinctrl_gpio1: gpio1grp { 356 fsl,pins = < 357 IMX95_PAD_UART1_TXD__AONMIX_TOP_GPIO1_IO_BIT5 0x31e /* GPIO1 */ 358 IMX95_PAD_UART1_RXD__AONMIX_TOP_GPIO1_IO_BIT4 0x31e /* GPIO2 */ 359 IMX95_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_BIT12 0x31e /* GPIO3 */ 360 >; 361 }; 362 363 pinctrl_gpio2: gpio2grp { 364 fsl,pins = < 365 IMX95_PAD_GPIO_IO17__GPIO2_IO_BIT17 0x31e /* GPIO4 */ 366 >; 367 }; 368 369 pinctrl_lpi2c1: lpi2c1grp { 370 fsl,pins = < 371 IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x40000b9e /* I2C5_SCL */ 372 IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x40000b9e /* I2C5_SDA */ 373 >; 374 }; 375 376 pinctrl_lpi2c2: lpi2c2grp { 377 fsl,pins = < 378 IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e /* I2C1_SDA_DNU */ 379 IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e /* I2C1_SCL_DNU */ 380 >; 381 }; 382 383 pinctrl_lpi2c3: lpi2c3grp { 384 fsl,pins = < 385 IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e /* I2C3_SDA */ 386 IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e /* I2C3_SCL */ 387 >; 388 }; 389 390 pinctrl_lpi2c4: lpi2c4grp { 391 fsl,pins = < 392 IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e /* I2C4_SDA */ 393 IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e /* I2C4_SDL */ 394 >; 395 }; 396 397 pinctrl_lpi2c5: lpi2c5grp { 398 fsl,pins = < 399 IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e /* I2C2_SDA */ 400 IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e /* I2C2_SCL */ 401 >; 402 }; 403 404 pinctrl_lpspi3: lpspi3grp { 405 fsl,pins = < 406 IMX95_PAD_GPIO_IO11__LPSPI3_SCK 0x51e /* SPI2_SCLK */ 407 IMX95_PAD_GPIO_IO10__LPSPI3_SOUT 0x51e /* SPI2_MOSI */ 408 IMX95_PAD_GPIO_IO09__LPSPI3_SIN 0x51e /* SPI2_MISO */ 409 IMX95_PAD_GPIO_IO08__LPSPI3_PCS0 0x51e /* SPI2_CS */ 410 >; 411 }; 412 413 pinctrl_lpspi4: lpspi4grp { 414 fsl,pins = < 415 IMX95_PAD_GPIO_IO21__LPSPI4_SCK 0x51e /* SPI3_SCLK */ 416 IMX95_PAD_GPIO_IO20__LPSPI4_SOUT 0x51e /* SPI3_MOSI */ 417 IMX95_PAD_GPIO_IO19__LPSPI4_SIN 0x51e /* SPI3_MISO */ 418 IMX95_PAD_GPIO_IO18__LPSPI4_PCS0 0x51e /* SPI3_CS */ 419 >; 420 }; 421 422 pinctrl_lpspi7: lpspi7grp { 423 fsl,pins = < 424 IMX95_PAD_GPIO_IO07__LPSPI7_SCK 0x51e /* SPI1_SCLK */ 425 IMX95_PAD_GPIO_IO06__LPSPI7_SOUT 0x51e /* SPI1_MOSI */ 426 IMX95_PAD_GPIO_IO05__LPSPI7_SIN 0x51e /* SPI1_MISO */ 427 IMX95_PAD_GPIO_IO04__LPSPI7_PCS0 0x51e /* SPI1_CS */ 428 >; 429 }; 430 431 pinctrl_lpuart5: lpuart5grp { 432 fsl,pins = < 433 IMX95_PAD_GPIO_IO01__LPUART5_RX 0x51e /* UART2_RXD */ 434 IMX95_PAD_GPIO_IO00__LPUART5_TX 0x51e /* UART2_TXD */ 435 IMX95_PAD_GPIO_IO03__LPUART5_RTS_B 0x51e /* UART2_RTS */ 436 IMX95_PAD_GPIO_IO02__LPUART5_CTS_B 0x51e /* UART2_CTS */ 437 >; 438 }; 439 440 pinctrl_lpuart7: lpuart7grp { 441 fsl,pins = < 442 IMX95_PAD_GPIO_IO37__LPUART7_RX 0x31e /* UART3_RXD */ 443 IMX95_PAD_GPIO_IO36__LPUART7_TX 0x31e /* UART3_TXD */ 444 >; 445 }; 446 447 pinctrl_lpuart8: lpuart8grp { 448 fsl,pins = < 449 IMX95_PAD_GPIO_IO13__LPUART8_RX 0x51e /* UART1_RXD */ 450 IMX95_PAD_GPIO_IO12__LPUART8_TX 0x51e /* UART1_TXD */ 451 IMX95_PAD_GPIO_IO15__LPUART8_RTS_B 0x51e /* UART1_RTS */ 452 IMX95_PAD_GPIO_IO14__LPUART8_CTS_B 0x51e /* UART1_CTS */ 453 >; 454 }; 455 456 pinctrl_pcie0: pcie0grp { 457 fsl,pins = < 458 IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x31e /* PCIE1_nCLKREQ */ 459 IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_BIT10 0x31e /* PCIE1_nPERST */ 460 >; 461 }; 462 463 pinctrl_pcie1: pcie1grp { 464 fsl,pins = < 465 IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x31e /* PCIE2_nCLKREQ */ 466 IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14 0x31e /* PCIE2_nPERST */ 467 >; 468 }; 469 470 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 471 fsl,pins = < 472 IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e 473 >; 474 }; 475 476 pinctrl_sai5: sai5grp { 477 fsl,pins = < 478 IMX95_PAD_XSPI1_DQS__SAI5_RX_SYNC 0x51e /* SAI1_RX_SYNC */ 479 IMX95_PAD_XSPI1_SS1_B__SAI5_RX_BCLK 0x51e /* SAI1_RX_BCLK */ 480 IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0 0x51e /* SAI1_RX_DATA */ 481 IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC 0x51e /* SAI1_TX_SYNC */ 482 IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK 0x51e /* SAI1_TX_BCLK */ 483 IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0 0x51e /* SAI1_TX_DATA */ 484 >; 485 }; 486 487 pinctrl_tpm3: tpm3grp { 488 fsl,pins = < 489 IMX95_PAD_GPIO_IO24__TPM3_CH3 0x51e /* PWM1 */ 490 >; 491 }; 492 493 pinctrl_tpm5: tpm5grp { 494 fsl,pins = < 495 IMX95_PAD_GPIO_IO26__TPM5_CH3 0x51e /* PWM2 */ 496 >; 497 }; 498 499 pinctrl_usbc: usbcgrp { 500 fsl,pins = < 501 IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11 0x51e /* USB1_PWR_EN */ 502 IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x51e /* USB1_OC */ 503 >; 504 }; 505 506 pinctrl_usb2: usb2grp { 507 fsl,pins = < 508 IMX95_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_BIT13 0x51e /* USB2_PWR_EN */ 509 IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x51e /* USB2_OC */ 510 >; 511 }; 512 513 pinctrl_usdhc1: usdhc1grp { 514 fsl,pins = < 515 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 516 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 517 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 518 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 519 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 520 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 521 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 522 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 523 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e 524 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e 525 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 526 >; 527 }; 528 529 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 530 fsl,pins = < 531 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 532 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 533 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 534 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 535 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 536 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 537 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 538 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 539 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e 540 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e 541 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 542 >; 543 }; 544 545 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 546 fsl,pins = < 547 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe 548 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe 549 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe 550 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe 551 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe 552 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe 553 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe 554 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe 555 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe 556 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe 557 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 558 >; 559 }; 560 561 pinctrl_usdhc2: usdhc2grp { 562 fsl,pins = < 563 IMX95_PAD_SD2_CD_B__USDHC2_CD_B 0x31e /* CD */ 564 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e /* CLK */ 565 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e /* CMD */ 566 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e /* DATA0 */ 567 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e /* DATA1 */ 568 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e /* DATA2 */ 569 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e /* DATA3 */ 570 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 571 572 >; 573 }; 574 575 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 576 fsl,pins = < 577 IMX95_PAD_SD2_CD_B__USDHC2_CD_B 0x31e /* CD */ 578 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e /* CLK */ 579 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e /* CMD */ 580 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e /* DATA0 */ 581 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e /* DATA1 */ 582 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e /* DATA2 */ 583 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e /* DATA3 */ 584 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 585 >; 586 }; 587 588 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 589 fsl,pins = < 590 IMX95_PAD_SD2_CD_B__USDHC2_CD_B 0x31e /* CD */ 591 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe /* CLK */ 592 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe /* CMD */ 593 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe /* DATA0 */ 594 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe /* DATA1 */ 595 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe /* DATA2 */ 596 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe /* DATA3 */ 597 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 598 >; 599 }; 600 601 pinctrl_usdhc3: usdhc3grp { 602 fsl,pins = < 603 IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e /* SDIO_CLK */ 604 IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e /* SDIO_CMD */ 605 IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e /* SDIO_DATA0 */ 606 IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e /* SDIO_DATA1 */ 607 IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e /* SDIO_DATA2 */ 608 IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e /* SDIO_DATA3 */ 609 >; 610 }; 611}; 612 613&tpm3 { /* FPSC PWM1 */ 614 pinctrl-0 = <&pinctrl_tpm3>; 615 pinctrl-names = "default"; 616}; 617 618&tpm5 { /* FPSC PWM2 */ 619 pinctrl-0 = <&pinctrl_tpm5>; 620 pinctrl-names = "default"; 621}; 622 623&usb3 { /* FPSC USB1 */ 624 pinctrl-0 = <&pinctrl_usbc>; 625 pinctrl-names = "default"; 626}; 627 628&usdhc1 { 629 bus-width = <8>; 630 non-removable; 631 no-sd; 632 no-sdio; 633 pinctrl-0 = <&pinctrl_usdhc1>; 634 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 635 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 636 pinctrl-3 = <&pinctrl_usdhc1>; 637 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 638 status = "okay"; 639}; 640 641&usdhc2 { /* FPSC SDCARD */ 642 bus-width = <4>; 643 disable-wp; 644 pinctrl-0 = <&pinctrl_usdhc2>; 645 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 646 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 647 pinctrl-3 = <&pinctrl_usdhc2>; 648 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 649 sd-uhs-sdr104; 650 vmmc-supply = <®_usdhc2_vmmc>; 651}; 652 653&usdhc3 { /* FPSC SDIO */ 654 pinctrl-0 = <&pinctrl_usdhc3>; 655 pinctrl-names = "default"; 656}; 657