1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2025 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/leds/common.h> 9#include <dt-bindings/phy/phy-imx8-pcie.h> 10#include <dt-bindings/pwm/pwm.h> 11#include <dt-bindings/usb/pd.h> 12#include "imx95.dtsi" 13 14#define BRD_SM_CTRL_SD3_WAKE 0x8000 /*!< PCAL6408A-0 */ 15#define BRD_SM_CTRL_PCIE1_WAKE 0x8001 /*!< PCAL6408A-4 */ 16#define BRD_SM_CTRL_BT_WAKE 0x8002 /*!< PCAL6408A-5 */ 17#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /*!< PCAL6408A-6 */ 18#define BRD_SM_CTRL_BUTTON 0x8004 /*!< PCAL6408A-7 */ 19 20/ { 21 compatible = "fsl,imx95-15x15-frdm", "fsl,imx95"; 22 model = "NXP i.MX95 15X15 FRDM board"; 23 24 aliases { 25 ethernet0 = &enetc_port0; 26 ethernet1 = &enetc_port1; 27 gpio0 = &gpio1; 28 gpio1 = &gpio2; 29 gpio2 = &gpio3; 30 gpio3 = &gpio4; 31 gpio4 = &gpio5; 32 i2c0 = &lpi2c1; 33 i2c1 = &lpi2c2; 34 i2c2 = &lpi2c3; 35 i2c3 = &lpi2c4; 36 i2c4 = &lpi2c5; 37 i2c5 = &lpi2c6; 38 i2c6 = &lpi2c7; 39 i2c7 = &lpi2c8; 40 mmc0 = &usdhc1; 41 mmc1 = &usdhc2; 42 mmc2 = &usdhc3; 43 serial0 = &lpuart1; 44 serial4 = &lpuart5; 45 }; 46 47 chosen { 48 #address-cells = <2>; 49 #size-cells = <2>; 50 stdout-path = &lpuart1; 51 }; 52 53 dmic: dmic { 54 compatible = "dmic-codec"; 55 #sound-dai-cells = <0>; 56 num-channels = <2>; 57 }; 58 59 flexcan2_phy: can-phy { 60 compatible = "nxp,tja1051"; 61 #phy-cells = <0>; 62 max-bitrate = <5000000>; 63 /* 64 * Shared SILENT GPIO: CAN PHYs enter silent mode 65 * together (hardware design). 66 */ 67 silent-gpios = <&pcal6524 7 GPIO_ACTIVE_HIGH>; 68 }; 69 70 flexcan5_phy: can-phy { 71 compatible = "nxp,tja1051"; 72 #phy-cells = <0>; 73 max-bitrate = <5000000>; 74 silent-gpios = <&pcal6524 7 GPIO_ACTIVE_HIGH>; 75 }; 76 77 reg_1p8v: regulator-1p8v { 78 compatible = "regulator-fixed"; 79 regulator-max-microvolt = <1800000>; 80 regulator-min-microvolt = <1800000>; 81 regulator-name = "+V1.8_SW"; 82 }; 83 84 reg_3p3v: regulator-3p3v { 85 compatible = "regulator-fixed"; 86 regulator-max-microvolt = <3300000>; 87 regulator-min-microvolt = <3300000>; 88 regulator-name = "+V3.3_SW"; 89 }; 90 91 reg_5p0v: regulator-5p0v { 92 compatible = "regulator-fixed"; 93 regulator-max-microvolt = <5000000>; 94 regulator-min-microvolt = <5000000>; 95 regulator-name = "+V5.0_SW"; 96 }; 97 98 reg_ext_3v3: regulator-ext-3v3 { 99 compatible = "regulator-fixed"; 100 regulator-max-microvolt = <3300000>; 101 regulator-min-microvolt = <3300000>; 102 regulator-name = "VCCEXT_3V3"; 103 }; 104 105 reg_ext_5v: regulator-ext-5v { 106 compatible = "regulator-fixed"; 107 regulator-always-on; 108 regulator-max-microvolt = <5000000>; 109 regulator-min-microvolt = <5000000>; 110 regulator-name = "VCCEXT_5V"; 111 gpio = <&pcal6524 12 GPIO_ACTIVE_HIGH>; 112 enable-active-high; 113 }; 114 115 reg_m2_ekey_pwr: regulator-m2-pwr { 116 compatible = "regulator-fixed"; 117 regulator-max-microvolt = <3300000>; 118 regulator-min-microvolt = <3300000>; 119 regulator-name = "M.2-power-ekey"; 120 gpio = <&pcal6524 16 GPIO_ACTIVE_HIGH>; 121 enable-active-high; 122 }; 123 124 reg_m2_mkey_pwr: regulator-m2-mkey-pwr { 125 compatible = "regulator-fixed"; 126 regulator-max-microvolt = <3300000>; 127 regulator-min-microvolt = <3300000>; 128 regulator-name = "M.2-mkey-power"; 129 gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>; 130 enable-active-high; 131 }; 132 133 reg_usdhc2_vmmc: regulator-usdhc2 { 134 compatible = "regulator-fixed"; 135 off-on-delay-us = <12000>; 136 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 137 pinctrl-names = "default"; 138 regulator-max-microvolt = <3300000>; 139 regulator-min-microvolt = <3300000>; 140 regulator-name = "VDD_SD2_3V3"; 141 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 142 enable-active-high; 143 }; 144 145 reg_usdhc3_vmmc: regulator-usdhc3 { 146 compatible = "regulator-fixed"; 147 regulator-max-microvolt = <3300000>; 148 regulator-min-microvolt = <3300000>; 149 regulator-name = "WLAN_EN"; 150 vin-supply = <®_m2_ekey_pwr>; 151 gpio = <&pcal6524 9 GPIO_ACTIVE_HIGH>; 152 enable-active-high; 153 /* 154 * IW612 wifi chip needs more delay than other wifi chips to complete 155 * the host interface initialization after power up, otherwise the 156 * internal state of IW612 may be unstable, resulting in the failure of 157 * the SDIO3.0 switch voltage. 158 */ 159 startup-delay-us = <20000>; 160 }; 161 162 reg_usb_vbus: regulator-vbus { 163 compatible = "regulator-fixed"; 164 regulator-max-microvolt = <5000000>; 165 regulator-min-microvolt = <5000000>; 166 regulator-name = "USB_VBUS"; 167 gpio = <&pcal6524 15 GPIO_ACTIVE_HIGH>; 168 enable-active-high; 169 }; 170 171 reg_vref_1v8: regulator-adc-vref { 172 compatible = "regulator-fixed"; 173 regulator-max-microvolt = <1800000>; 174 regulator-min-microvolt = <1800000>; 175 regulator-name = "vref_1v8"; 176 }; 177 178 reserved-memory { 179 ranges; 180 #address-cells = <2>; 181 #size-cells = <2>; 182 183 linux_cma: linux,cma { 184 compatible = "shared-dma-pool"; 185 alloc-ranges = <0 0x80000000 0 0x7F000000>; 186 reusable; 187 size = <0 0x3c000000>; 188 linux,cma-default; 189 }; 190 191 vdev0vring0: memory@88000000 { 192 reg = <0 0x88000000 0 0x8000>; 193 no-map; 194 }; 195 196 vdev0vring1: memory@88008000 { 197 reg = <0 0x88008000 0 0x8000>; 198 no-map; 199 }; 200 201 vdev1vring0: memory@88010000 { 202 reg = <0 0x88010000 0 0x8000>; 203 no-map; 204 }; 205 206 vdev1vring1: memory@88018000 { 207 reg = <0 0x88018000 0 0x8000>; 208 no-map; 209 }; 210 211 vdevbuffer: memory@88020000 { 212 compatible = "shared-dma-pool"; 213 reg = <0 0x88020000 0 0x100000>; 214 no-map; 215 }; 216 217 rsc_table: memory@88220000 { 218 reg = <0 0x88220000 0 0x1000>; 219 no-map; 220 }; 221 222 vpu_boot: memory@a0000000 { 223 reg = <0 0xa0000000 0 0x100000>; 224 no-map; 225 }; 226 }; 227 228 sound-micfil { 229 compatible = "fsl,imx-audio-card"; 230 model = "micfil-audio"; 231 232 pri-dai-link { 233 link-name = "micfil hifi"; 234 format = "i2s"; 235 236 cpu { 237 sound-dai = <&micfil>; 238 }; 239 240 codec { 241 sound-dai = <&dmic>; 242 }; 243 }; 244 }; 245 246 usdhc3_pwrseq: usdhc3-pwrseq { 247 compatible = "mmc-pwrseq-simple"; 248 reset-gpios = <&pcal6524 8 GPIO_ACTIVE_LOW>; 249 }; 250 251 memory@80000000 { 252 reg = <0x0 0x80000000 0 0x80000000>; 253 device_type = "memory"; 254 }; 255}; 256 257&adc1 { 258 vref-supply = <®_vref_1v8>; 259 status = "okay"; 260}; 261 262&enetc_port0 { 263 phy-handle = <ðphy0>; 264 phy-mode = "rgmii-id"; 265 pinctrl-0 = <&pinctrl_enetc0>; 266 pinctrl-names = "default"; 267 status = "okay"; 268}; 269 270&enetc_port1 { 271 phy-handle = <ðphy1>; 272 phy-mode = "rgmii-id"; 273 pinctrl-0 = <&pinctrl_enetc1>; 274 pinctrl-names = "default"; 275 status = "okay"; 276}; 277 278&flexcan2 { 279 pinctrl-0 = <&pinctrl_flexcan2>; 280 pinctrl-names = "default"; 281 phys = <&flexcan2_phy>; 282 status = "okay"; 283}; 284 285&flexcan5 { 286 pinctrl-0 = <&pinctrl_flexcan5>; 287 pinctrl-names = "default"; 288 phys = <&flexcan5_phy>; 289 status = "okay"; 290}; 291 292&lpi2c2 { 293 clock-frequency = <400000>; 294 pinctrl-0 = <&pinctrl_lpi2c2>; 295 pinctrl-names = "default"; 296 status = "okay"; 297 298 pcal6524: gpio@22 { 299 compatible = "nxp,pcal6524"; 300 reg = <0x22>; 301 #interrupt-cells = <2>; 302 interrupt-controller; 303 interrupt-parent = <&gpio5>; 304 interrupts = <14 IRQ_TYPE_LEVEL_LOW>; 305 #gpio-cells = <2>; 306 gpio-controller; 307 pinctrl-0 = <&pinctrl_pcal6524>; 308 pinctrl-names = "default"; 309 gpio-line-names = "ENET1 PHY reset", 310 "ENET2 PHY reset", 311 "SPI3/GPIO select", 312 "UART3/GPIO select", 313 "CAN2&5/GPIO select", 314 "PWM/GPIO select", 315 "Watch dog enable", 316 "CAN1&2&5 silent", 317 "SDIO_nRST", 318 "WL_nDISABLE1", 319 "WL_nDISABLE2", 320 "M.2 Mkey NC06", 321 "EXT_5V0_PWR_EN", 322 "EXT_3V3_PWR_EN", 323 "Mkey power control", 324 "USB2 power control", 325 "Ekey power control", 326 "MIPI-DSICSI reset", 327 "MIPI-DSI IO2", 328 "MIPI-CSI reset", 329 "LVDS TP reset", 330 "LVDS BL enable", 331 "LVDS BL power enable", 332 "IT6263 reset"; 333 334 lpspi-gpio-sel-hog { 335 gpio-hog; 336 gpios = <2 GPIO_ACTIVE_HIGH>; 337 output-low; 338 }; 339 340 lpuart-gpio-sel-hog { 341 gpio-hog; 342 gpios = <3 GPIO_ACTIVE_HIGH>; 343 output-low; 344 }; 345 346 can-gpio-sel-hog { 347 gpio-hog; 348 gpios = <4 GPIO_ACTIVE_HIGH>; 349 output-low; 350 }; 351 352 pwm-gpio-sel-hog { 353 gpio-hog; 354 gpios = <5 GPIO_ACTIVE_HIGH>; 355 output-high; 356 }; 357 }; 358}; 359 360&lpi2c3 { 361 clock-frequency = <400000>; 362 pinctrl-0 = <&pinctrl_lpi2c3>; 363 pinctrl-names = "default"; 364 status = "okay"; 365 366 ptn5110: tcpc@50 { 367 compatible = "nxp,ptn5110", "tcpci"; 368 reg = <0x50>; 369 interrupt-parent = <&gpio5>; 370 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 371 pinctrl-0 = <&pinctrl_ptn5110>; 372 pinctrl-names = "default"; 373 374 typec_con: connector { 375 compatible = "usb-c-connector"; 376 data-role = "dual"; 377 label = "USB-C"; 378 op-sink-microwatt = <15000000>; 379 power-role = "dual"; 380 self-powered; 381 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 382 PDO_VAR(5000, 20000, 3000)>; 383 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 384 try-power-role = "sink"; 385 386 ports { 387 #address-cells = <1>; 388 #size-cells = <0>; 389 390 port@0 { 391 reg = <0>; 392 393 typec_con_hs: endpoint { 394 remote-endpoint = <&usb3_data_hs>; 395 }; 396 }; 397 398 port@1 { 399 reg = <1>; 400 401 typec_con_ss: endpoint { 402 remote-endpoint = <&usb3_data_ss>; 403 }; 404 }; 405 }; 406 }; 407 }; 408}; 409 410&lpi2c4 { 411 clock-frequency = <400000>; 412 pinctrl-0 = <&pinctrl_lpi2c4>; 413 pinctrl-names = "default"; 414 status = "okay"; 415 416 pca9632: led-controller@62 { 417 compatible = "nxp,pca9632"; 418 reg = <0x62>; 419 #address-cells = <1>; 420 #size-cells = <0>; 421 nxp,inverted-out; 422 423 led_backlight0: led@0 { 424 reg = <0>; 425 color = <LED_COLOR_ID_WHITE>; 426 function = LED_FUNCTION_BACKLIGHT; 427 function-enumerator = <0>; 428 }; 429 430 led_backlight1: led@1 { 431 reg = <1>; 432 color = <LED_COLOR_ID_WHITE>; 433 function = LED_FUNCTION_BACKLIGHT; 434 function-enumerator = <1>; 435 }; 436 }; 437}; 438 439&lpuart1 { 440 pinctrl-0 = <&pinctrl_uart1>; 441 pinctrl-names = "default"; 442 status = "okay"; 443}; 444 445&lpuart5 { 446 pinctrl-0 = <&pinctrl_uart5>; 447 pinctrl-names = "default"; 448 status = "okay"; 449 450 bluetooth { 451 compatible = "nxp,88w8987-bt"; 452 }; 453}; 454 455&micfil { 456 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 457 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 458 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 459 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 460 <&scmi_clk IMX95_CLK_PDM>; 461 assigned-clock-parents = <0>, <0>, <0>, <0>, 462 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 463 assigned-clock-rates = <3932160000>, 464 <3612672000>, <393216000>, 465 <361267200>, <49152000>; 466 #sound-dai-cells = <0>; 467 pinctrl-0 = <&pinctrl_pdm>; 468 pinctrl-names = "default"; 469 status = "okay"; 470}; 471 472&mu7 { 473 status = "okay"; 474}; 475 476&netc_blk_ctrl { 477 status = "okay"; 478}; 479 480/* Configure MSI and IOMMU mappings specific to the i.MX95 15x15 FRDM board. */ 481&netc_bus0 { 482 msi-map = <0x0 &its 0x60 0x1>, //ENETC0 PF 483 <0x10 &its 0x61 0x1>, //ENETC0 VF0 484 <0x20 &its 0x62 0x1>, //ENETC0 VF1 485 <0x40 &its 0x63 0x1>, //ENETC1 PF 486 <0x50 &its 0x65 0x1>, //ENETC1 VF0 487 <0x60 &its 0x66 0x1>, //ENETC1 VF1 488 <0x80 &its 0x64 0x1>, //ENETC2 PF 489 <0xc0 &its 0x67 0x1>; //NETC Timer 490 iommu-map = <0x0 &smmu 0x20 0x1>, 491 <0x10 &smmu 0x21 0x1>, 492 <0x20 &smmu 0x22 0x1>, 493 <0x40 &smmu 0x23 0x1>, 494 <0x50 &smmu 0x25 0x1>, 495 <0x60 &smmu 0x26 0x1>, 496 <0x80 &smmu 0x24 0x1>, 497 <0xc0 &smmu 0x27 0x1>; 498}; 499 500&netc_emdio { 501 pinctrl-0 = <&pinctrl_emdio>; 502 pinctrl-names = "default"; 503 status = "okay"; 504 505 ethphy0: ethernet-phy@1 { 506 reg = <1>; 507 reset-assert-us = <10000>; 508 reset-deassert-us = <80000>; 509 reset-gpios = <&pcal6524 0 GPIO_ACTIVE_LOW>; 510 }; 511 512 ethphy1: ethernet-phy@2 { 513 reg = <2>; 514 reset-assert-us = <10000>; 515 reset-deassert-us = <80000>; 516 reset-gpios = <&pcal6524 1 GPIO_ACTIVE_LOW>; 517 }; 518}; 519 520&netc_timer { 521 status = "okay"; 522}; 523 524&netcmix_blk_ctrl { 525 status = "okay"; 526}; 527 528&pcie0 { 529 pinctrl-0 = <&pinctrl_pcie0>; 530 pinctrl-names = "default"; 531 reset-gpio = <&gpio5 13 GPIO_ACTIVE_LOW>; 532 supports-clkreq; 533 vpcie-supply = <®_m2_mkey_pwr>; 534 status = "okay"; 535}; 536 537&scmi_iomuxc { 538 pinctrl_emdio: emdiogrp { 539 fsl,pins = < 540 IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x50e 541 IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e 542 >; 543 }; 544 545 pinctrl_enetc0: enetc0grp { 546 fsl,pins = < 547 IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e 548 IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e 549 IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e 550 IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e 551 IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e 552 IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e 553 IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e 554 IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e 555 IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e 556 IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e 557 IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e 558 IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e 559 >; 560 }; 561 562 pinctrl_enetc1: enetc1grp { 563 fsl,pins = < 564 IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x50e 565 IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x50e 566 IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x50e 567 IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x50e 568 IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e 569 IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x58e 570 IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e 571 IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x58e 572 IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e 573 IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e 574 IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e 575 IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x57e 576 >; 577 }; 578 579 pinctrl_flexcan2: flexcan2grp { 580 fsl,pins = < 581 IMX95_PAD_GPIO_IO25__CAN2_TX 0x39e 582 IMX95_PAD_GPIO_IO27__CAN2_RX 0x39e 583 >; 584 }; 585 586 pinctrl_flexcan5: flexcan5grp { 587 fsl,pins = < 588 IMX95_PAD_GPIO_IO22__CAN5_TX 0x39e 589 IMX95_PAD_GPIO_IO23__CAN5_RX 0x39e 590 >; 591 }; 592 593 pinctrl_lpi2c1: lpi2c1grp { 594 fsl,pins = < 595 IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x40000b9e 596 IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x40000b9e 597 >; 598 }; 599 600 pinctrl_lpi2c2: lpi2c2grp { 601 fsl,pins = < 602 IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e 603 IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e 604 >; 605 }; 606 607 pinctrl_lpi2c3: lpi2c3grp { 608 fsl,pins = < 609 IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e 610 IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e 611 >; 612 }; 613 614 pinctrl_lpi2c4: lpi2c4grp { 615 fsl,pins = < 616 IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e 617 IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e 618 >; 619 }; 620 621 pinctrl_pcal6524: pcal6524grp { 622 fsl,pins = < 623 IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e 624 >; 625 }; 626 627 pinctrl_pcie0: pcie0grp { 628 fsl,pins = < 629 IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x40000b1e 630 IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x31e 631 >; 632 }; 633 634 pinctrl_pdm: pdmgrp { 635 fsl,pins = < 636 IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e 637 IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x31e 638 >; 639 }; 640 641 pinctrl_ptn5110: ptn5110grp { 642 fsl,pins = < 643 IMX95_PAD_XSPI1_DATA3__GPIO5_IO_BIT3 0x31e 644 >; 645 }; 646 647 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 648 fsl,pins = < 649 IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e 650 >; 651 }; 652 653 pinctrl_uart1: uart1grp { 654 fsl,pins = < 655 IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e 656 IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e 657 >; 658 }; 659 660 pinctrl_uart5: uart5grp { 661 fsl,pins = < 662 IMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e 663 IMX95_PAD_DAP_TDI__LPUART5_RX 0x31e 664 IMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e 665 IMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e 666 >; 667 }; 668 669 pinctrl_usdhc1: usdhc1grp { 670 fsl,pins = < 671 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e 672 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e 673 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 674 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 675 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 676 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 677 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 678 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 679 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 680 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 681 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 682 >; 683 }; 684 685 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 686 fsl,pins = < 687 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e 688 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e 689 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 690 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 691 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 692 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 693 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 694 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 695 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 696 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 697 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 698 >; 699 }; 700 701 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 702 fsl,pins = < 703 IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe 704 IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe 705 IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe 706 IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe 707 IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe 708 IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe 709 IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe 710 IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe 711 IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe 712 IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe 713 IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 714 >; 715 }; 716 717 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 718 fsl,pins = < 719 IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e 720 >; 721 }; 722 723 pinctrl_usdhc2: usdhc2grp { 724 fsl,pins = < 725 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e 726 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e 727 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 728 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 729 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 730 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 731 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 732 >; 733 }; 734 735 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 736 fsl,pins = < 737 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e 738 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e 739 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 740 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 741 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 742 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 743 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 744 >; 745 }; 746 747 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 748 fsl,pins = < 749 IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e 750 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e 751 IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 752 IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 753 IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 754 IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 755 IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 756 >; 757 }; 758 759 pinctrl_usdhc3: usdhc3grp { 760 fsl,pins = < 761 IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e 762 IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e 763 IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e 764 IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e 765 IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e 766 IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e 767 >; 768 }; 769 770 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 771 fsl,pins = < 772 IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e 773 IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e 774 IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e 775 IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e 776 IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e 777 IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e 778 >; 779 }; 780 781 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 782 fsl,pins = < 783 IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe 784 IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe 785 IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe 786 IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe 787 IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe 788 IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe 789 >; 790 }; 791}; 792 793&scmi_misc { 794 nxp,ctrl-ids = <BRD_SM_CTRL_SD3_WAKE 1 795 BRD_SM_CTRL_PCIE1_WAKE 1 796 BRD_SM_CTRL_BT_WAKE 1 797 BRD_SM_CTRL_PCIE2_WAKE 1 798 BRD_SM_CTRL_BUTTON 1>; 799}; 800 801&thermal_zones { 802 pf09-thermal { 803 polling-delay = <2000>; 804 polling-delay-passive = <250>; 805 thermal-sensors = <&scmi_sensor 2>; 806 807 trips { 808 pf09_alert: trip0 { 809 hysteresis = <2000>; 810 temperature = <140000>; 811 type = "passive"; 812 }; 813 814 pf09_crit: trip1 { 815 hysteresis = <2000>; 816 temperature = <155000>; 817 type = "critical"; 818 }; 819 }; 820 }; 821 822 pf53arm-thermal { 823 polling-delay = <2000>; 824 polling-delay-passive = <250>; 825 thermal-sensors = <&scmi_sensor 4>; 826 827 cooling-maps { 828 map0 { 829 cooling-device = <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 830 <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 831 <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 832 <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 833 <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 834 <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 835 trip = <&pf5301_alert>; 836 }; 837 }; 838 839 trips { 840 pf5301_alert: trip0 { 841 hysteresis = <2000>; 842 temperature = <140000>; 843 type = "passive"; 844 }; 845 846 pf5301_crit: trip1 { 847 hysteresis = <2000>; 848 temperature = <155000>; 849 type = "critical"; 850 }; 851 }; 852 }; 853 854 pf53soc-thermal { 855 polling-delay = <2000>; 856 polling-delay-passive = <250>; 857 thermal-sensors = <&scmi_sensor 3>; 858 859 trips { 860 pf5302_alert: trip0 { 861 hysteresis = <2000>; 862 temperature = <140000>; 863 type = "passive"; 864 }; 865 866 pf5302_crit: trip1 { 867 hysteresis = <2000>; 868 temperature = <155000>; 869 type = "critical"; 870 }; 871 }; 872 }; 873}; 874 875&usb2 { 876 disable-over-current; 877 dr_mode = "host"; 878 vbus-supply = <®_usb_vbus>; 879 status = "okay"; 880}; 881 882&usb3 { 883 status = "okay"; 884}; 885 886&usb3_dwc3 { 887 adp-disable; 888 dr_mode = "otg"; 889 hnp-disable; 890 role-switch-default-mode = "peripheral"; 891 srp-disable; 892 usb-role-switch; 893 snps,dis-u1-entry-quirk; 894 snps,dis-u2-entry-quirk; 895 status = "okay"; 896 897 port { 898 usb3_data_hs: endpoint { 899 remote-endpoint = <&typec_con_hs>; 900 }; 901 }; 902}; 903 904&usb3_phy { 905 orientation-switch; 906 fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <17>; 907 fsl,phy-pcs-tx-swing-full-percent = <100>; 908 fsl,phy-tx-preemp-amp-tune-microamp = <600>; 909 fsl,phy-tx-vboost-level-microvolt = <1156>; 910 fsl,phy-tx-vref-tune-percent = <100>; 911 status = "okay"; 912 913 port { 914 usb3_data_ss: endpoint { 915 remote-endpoint = <&typec_con_ss>; 916 }; 917 }; 918}; 919 920&usdhc1 { 921 bus-width = <8>; 922 non-removable; 923 no-sd; 924 no-sdio; 925 pinctrl-0 = <&pinctrl_usdhc1>; 926 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 927 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 928 pinctrl-3 = <&pinctrl_usdhc1>; 929 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 930 fsl,tuning-step = <1>; 931 status = "okay"; 932}; 933 934&usdhc2 { 935 bus-width = <4>; 936 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; 937 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 938 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 939 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 940 pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 941 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 942 vmmc-supply = <®_usdhc2_vmmc>; 943 fsl,tuning-step = <1>; 944 status = "okay"; 945}; 946 947&usdhc3 { 948 bus-width = <4>; 949 keep-power-in-suspend; 950 mmc-pwrseq = <&usdhc3_pwrseq>; 951 non-removable; 952 pinctrl-0 = <&pinctrl_usdhc3>; 953 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 954 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 955 pinctrl-3 = <&pinctrl_usdhc3>; 956 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 957 vmmc-supply = <®_usdhc3_vmmc>; 958 wakeup-source; 959 status = "okay"; 960}; 961 962&wdog3 { 963 status = "okay"; 964}; 965