1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Variscite Sonata carrier board for DART-MX93 4 * 5 * Link: https://variscite.com/carrier-boards/sonata-board/ 6 * 7 * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ 8 * 9 */ 10 11/dts-v1/; 12 13#include <dt-bindings/leds/common.h> 14#include "imx93-var-dart.dtsi" 15 16/ { 17 model = "Variscite DART-MX93 on Sonata-Board"; 18 compatible = "variscite,var-dart-mx93-sonata", 19 "variscite,var-dart-mx93", 20 "fsl,imx93"; 21 22 aliases { 23 ethernet0 = &eqos; 24 ethernet1 = &fec; 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 i2c0 = &lpi2c1; 29 i2c1 = &lpi2c2; 30 i2c2 = &lpi2c3; 31 i2c3 = &lpi2c4; 32 i2c4 = &lpi2c5; 33 mmc0 = &usdhc1; 34 mmc1 = &usdhc2; 35 serial0 = &lpuart1; 36 serial1 = &lpuart2; 37 serial2 = &lpuart3; 38 serial3 = &lpuart4; 39 serial4 = &lpuart5; 40 serial5 = &lpuart6; 41 serial6 = &lpuart7; 42 }; 43 44 chosen { 45 stdout-path = &lpuart1; 46 }; 47 48 gpio-keys { 49 compatible = "gpio-keys"; 50 51 button-home { 52 label = "Home"; 53 linux,code = <KEY_HOME>; 54 gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>; 55 wakeup-source; 56 }; 57 58 button-up { 59 label = "Up"; 60 linux,code = <KEY_UP>; 61 gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>; 62 wakeup-source; 63 }; 64 65 button-down { 66 label = "Down"; 67 linux,code = <KEY_DOWN>; 68 gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>; 69 wakeup-source; 70 }; 71 72 button-back { 73 label = "Back"; 74 linux,code = <KEY_BACK>; 75 gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>; 76 wakeup-source; 77 }; 78 }; 79 80 gpio-leds { 81 compatible = "gpio-leds"; 82 pinctrl-names = "default"; 83 pinctrl-0 = <&pinctrl_leds_gpio>; 84 85 led-emmc { 86 gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; 87 label = "eMMC"; 88 linux,default-trigger = "mmc0"; 89 }; 90 }; 91 92 clk40m: oscillator { 93 compatible = "fixed-clock"; 94 #clock-cells = <0>; 95 clock-frequency = <40000000>; 96 clock-output-names = "can_osc"; 97 }; 98 99 reg_vref_1v8: regulator-adc-vref { 100 compatible = "regulator-fixed"; 101 regulator-name = "vref_1v8"; 102 regulator-max-microvolt = <1800000>; 103 regulator-min-microvolt = <1800000>; 104 }; 105 106 reg_phy1_supply: regulator-phy1 { 107 compatible = "regulator-fixed"; 108 regulator-name = "SUPPLY_PHY1"; 109 regulator-min-microvolt = <3300000>; 110 regulator-max-microvolt = <3300000>; 111 gpio = <&pca6408_2 0 GPIO_ACTIVE_HIGH>; 112 enable-active-high; 113 startup-delay-us = <10000>; 114 regulator-always-on; 115 }; 116 117 reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { 118 compatible = "regulator-fixed"; 119 regulator-name = "VDD_SD2_3V3"; 120 off-on-delay-us = <20000>; 121 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 122 pinctrl-names = "default"; 123 regulator-max-microvolt = <3300000>; 124 regulator-min-microvolt = <3300000>; 125 gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>; 126 enable-active-high; 127 }; 128 129 reserved-memory { 130 #address-cells = <2>; 131 #size-cells = <2>; 132 ranges; 133 134 ethosu_mem: ethosu-region@88000000 { 135 compatible = "shared-dma-pool"; 136 reusable; 137 reg = <0x0 0x88000000 0x0 0x8000000>; 138 }; 139 140 vdev0vring0: vdev0vring0@87ee0000 { 141 reg = <0 0x87ee0000 0 0x8000>; 142 no-map; 143 }; 144 145 vdev0vring1: vdev0vring1@87ee8000 { 146 reg = <0 0x87ee8000 0 0x8000>; 147 no-map; 148 }; 149 150 vdev1vring0: vdev1vring0@87ef0000 { 151 reg = <0 0x87ef0000 0 0x8000>; 152 no-map; 153 }; 154 155 vdev1vring1: vdev1vring1@87ef8000 { 156 reg = <0 0x87ef8000 0 0x8000>; 157 no-map; 158 }; 159 160 rsc_table: rsc-table@2021e000 { 161 reg = <0 0x2021e000 0 0x1000>; 162 no-map; 163 }; 164 165 vdevbuffer: vdevbuffer@87f00000 { 166 compatible = "shared-dma-pool"; 167 reg = <0 0x87f00000 0 0x100000>; 168 no-map; 169 }; 170 171 ele_reserved: ele-reserved@87de0000 { 172 compatible = "shared-dma-pool"; 173 reg = <0 0x87de0000 0 0x100000>; 174 no-map; 175 }; 176 }; 177}; 178 179&adc1 { 180 vref-supply = <®_vref_1v8>; 181 status = "okay"; 182}; 183 184/* Use external instead of internal RTC */ 185&bbnsm_rtc { 186 status = "disabled"; 187}; 188 189&eqos { 190 mdio { 191 ethphy1: ethernet-phy@1 { 192 compatible = "ethernet-phy-ieee802.3-c22"; 193 reg = <1>; 194 195 leds { 196 #address-cells = <1>; 197 #size-cells = <0>; 198 199 led@0 { 200 reg = <0>; 201 color = <LED_COLOR_ID_YELLOW>; 202 function = LED_FUNCTION_LAN; 203 linux,default-trigger = "netdev"; 204 }; 205 206 led@1 { 207 reg = <1>; 208 color = <LED_COLOR_ID_GREEN>; 209 function = LED_FUNCTION_LAN; 210 linux,default-trigger = "netdev"; 211 }; 212 }; 213 }; 214 }; 215}; 216 217ðphy0 { 218 leds { 219 #address-cells = <1>; 220 #size-cells = <0>; 221 222 led@0 { 223 reg = <0>; 224 color = <LED_COLOR_ID_YELLOW>; 225 function = LED_FUNCTION_LAN; 226 linux,default-trigger = "netdev"; 227 }; 228 229 led@1 { 230 reg = <1>; 231 color = <LED_COLOR_ID_GREEN>; 232 function = LED_FUNCTION_LAN; 233 linux,default-trigger = "netdev"; 234 }; 235 }; 236}; 237 238&fec { 239 pinctrl-names = "default", "sleep"; 240 pinctrl-0 = <&pinctrl_fec>; 241 pinctrl-1 = <&pinctrl_fec_sleep>; 242 /* 243 * The required RGMII TX and RX 2ns delays are implemented directly 244 * in hardware via passive delay elements on the SOM PCB. 245 * No delay configuration is needed in software via PHY driver. 246 */ 247 phy-mode = "rgmii"; 248 phy-handle = <ðphy1>; 249 status = "okay"; 250}; 251 252&flexcan1 { 253 pinctrl-names = "default"; 254 pinctrl-0 = <&pinctrl_flexcan1>; 255 status = "okay"; 256}; 257 258&lpi2c1 { 259 clock-frequency = <400000>; 260 pinctrl-0 = <&pinctrl_lpi2c1>; 261 pinctrl-1 = <&pinctrl_lpi2c1_gpio>; 262 pinctrl-2 = <&pinctrl_lpi2c1_gpio>; 263 pinctrl-names = "default", "sleep", "gpio"; 264 scl-gpios = <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 265 sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 266 status = "okay"; 267 268 pca9534: gpio@22 { 269 compatible = "nxp,pca9534"; 270 reg = <0x22>; 271 gpio-controller; 272 #gpio-cells = <2>; 273 interrupt-parent = <&gpio1>; 274 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 275 }; 276 277 /* Capacitive touch controller */ 278 ft5x06_ts: touchscreen@38 { 279 compatible = "edt,edt-ft5206"; 280 reg = <0x38>; 281 interrupt-parent = <&gpio3>; 282 interrupts = <27 IRQ_TYPE_EDGE_FALLING>; 283 pinctrl-0 = <&pinctrl_captouch>; 284 pinctrl-names = "default"; 285 reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>; 286 touchscreen-inverted-x; 287 touchscreen-inverted-y; 288 touchscreen-size-x = <800>; 289 touchscreen-size-y = <480>; 290 wakeup-source; 291 }; 292 293 /* USB Type-C Controller */ 294 typec@3d { 295 compatible = "nxp,ptn5150"; 296 reg = <0x3d>; 297 interrupt-parent = <&gpio4>; 298 interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; 299 pinctrl-0 = <&pinctrl_extcon>; 300 pinctrl-names = "default"; 301 302 port { 303 typec1_dr_sw: endpoint { 304 remote-endpoint = <&usb1_drd_sw>; 305 }; 306 }; 307 }; 308 309 rtc@68 { 310 compatible = "dallas,ds1337"; 311 reg = <0x68>; 312 interrupt-parent = <&gpio2>; 313 interrupts = <2 IRQ_TYPE_EDGE_FALLING>; 314 pinctrl-names = "default"; 315 pinctrl-0 = <&pinctrl_rtc>; 316 wakeup-source; 317 }; 318}; 319 320&lpi2c5 { 321 clock-frequency = <400000>; 322 pinctrl-names = "default", "sleep", "gpio"; 323 pinctrl-0 = <&pinctrl_lpi2c5>; 324 pinctrl-1 = <&pinctrl_lpi2c5_gpio>; 325 pinctrl-2 = <&pinctrl_lpi2c5_gpio>; 326 scl-gpios = <&gpio2 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 327 sda-gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 328 status = "okay"; 329}; 330 331&lpi2c7 { 332 clock-frequency = <400000>; 333 pinctrl-names = "default", "sleep", "gpio"; 334 pinctrl-0 = <&pinctrl_lpi2c7>; 335 pinctrl-1 = <&pinctrl_lpi2c7_gpio>; 336 pinctrl-2 = <&pinctrl_lpi2c7_gpio>; 337 scl-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 338 sda-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 339 status = "okay"; 340 341 pca6408_1: gpio@20 { 342 compatible = "nxp,pcal6408"; 343 reg = <0x20>; 344 gpio-controller; 345 #gpio-cells = <2>; 346 interrupt-parent = <&gpio1>; 347 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 348 }; 349 350 pca6408_2: gpio@21 { 351 compatible = "nxp,pcal6408"; 352 reg = <0x21>; 353 gpio-controller; 354 #gpio-cells = <2>; 355 interrupt-parent = <&gpio1>; 356 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 357 }; 358 359 st33ktpm2xi2c: tpm@2e { 360 compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; 361 reg = <0x2e>; 362 }; 363}; 364 365&lpspi8 { 366 pinctrl-names = "default"; 367 pinctrl-0 = <&pinctrl_lpspi8>; 368 cs-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 369 status = "okay"; 370 371 /* CAN controller */ 372 can0: can@0 { 373 compatible = "microchip,mcp251xfd"; 374 reg = <0>; 375 clocks = <&clk40m>; 376 interrupt-parent = <&gpio2>; 377 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 378 pinctrl-names = "default"; 379 pinctrl-0 = <&pinctrl_can>; 380 spi-max-frequency = <1000000>; 381 }; 382}; 383 384/* Console (J10) */ 385&lpuart1 { 386 pinctrl-names = "default"; 387 pinctrl-0 = <&pinctrl_uart1>; 388 status = "okay"; 389}; 390 391/* Header (J12.4, J12.6) */ 392&lpuart6 { 393 pinctrl-names = "default"; 394 pinctrl-0 = <&pinctrl_uart6>; 395 status = "okay"; 396}; 397 398/* Header (J12.11, J12.13) */ 399&lpuart7 { 400 pinctrl-names = "default"; 401 pinctrl-0 = <&pinctrl_uart7>; 402 status = "okay"; 403}; 404 405&tpm3 { 406 pinctrl-0 = <&pinctrl_tpm3>; 407 pinctrl-names = "default"; 408 status = "okay"; 409}; 410 411&usbotg1 { 412 dr_mode = "otg"; 413 hnp-disable; 414 srp-disable; 415 adp-disable; 416 usb-role-switch; 417 disable-over-current; 418 samsung,picophy-pre-emp-curr-control = <3>; 419 samsung,picophy-dc-vol-level-adjust = <7>; 420 status = "okay"; 421 422 port { 423 usb1_drd_sw: endpoint { 424 remote-endpoint = <&typec1_dr_sw>; 425 }; 426 }; 427}; 428 429&usbotg2 { 430 disable-over-current; 431 dr_mode = "host"; 432 status = "okay"; 433}; 434 435/* SD */ 436&usdhc2 { 437 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 438 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 439 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 440 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 441 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 442 vmmc-supply = <®_usdhc2_vmmc>; 443 bus-width = <4>; 444 no-sdio; 445 no-mmc; 446 status = "okay"; 447}; 448 449&wdog3 { 450 status = "okay"; 451}; 452 453&iomuxc { 454 pinctrl-names = "default"; 455 pinctrl-0 = <&pinctrl_hog>; 456 457 pinctrl_can: cangrp { 458 fsl,pins = < 459 MX93_PAD_GPIO_IO03__GPIO2_IO03 0x31e 460 >; 461 }; 462 463 pinctrl_captouch: captouchgrp { 464 fsl,pins = < 465 MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e 466 >; 467 }; 468 469 pinctrl_extcon: extcongrp { 470 fsl,pins = < 471 MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x31e 472 >; 473 }; 474 475 pinctrl_fec: fecgrp { 476 fsl,pins = < 477 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e 478 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e 479 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e 480 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x37e 481 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e 482 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e 483 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e 484 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e 485 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e 486 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e 487 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e 488 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e 489 >; 490 }; 491 492 pinctrl_fec_sleep: fecsleepgrp { 493 fsl,pins = < 494 MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e 495 MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e 496 MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e 497 MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e 498 MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e 499 MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e 500 MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e 501 MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e 502 MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e 503 MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e 504 MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e 505 MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e 506 >; 507 }; 508 509 pinctrl_flexcan1: flexcan1grp { 510 fsl,pins = < 511 MX93_PAD_PDM_CLK__CAN1_TX 0x139e 512 MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e 513 >; 514 }; 515 516 pinctrl_hog: hoggrp { 517 fsl,pins = < 518 /* GPIO Expanders shared IRQ */ 519 MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e 520 >; 521 }; 522 523 pinctrl_leds_gpio: ledgrp { 524 fsl,pins = < 525 MX93_PAD_GPIO_IO11__GPIO2_IO11 0x31e 526 >; 527 }; 528 529 pinctrl_lpi2c1: lpi2c1grp { 530 fsl,pins = < 531 MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e 532 MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e 533 >; 534 }; 535 536 pinctrl_lpi2c1_gpio: lpi2c1-gpiogrp { 537 fsl,pins = < 538 MX93_PAD_I2C1_SCL__GPIO1_IO00 0x31e 539 MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e 540 >; 541 }; 542 543 pinctrl_lpi2c5: lpi2c5grp { 544 fsl,pins = < 545 MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e 546 MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e 547 >; 548 }; 549 550 pinctrl_lpi2c5_gpio: lpi2c5-gpiogrp { 551 fsl,pins = < 552 MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e 553 MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e 554 >; 555 }; 556 557 pinctrl_lpi2c7: lpi2c7grp { 558 fsl,pins = < 559 MX93_PAD_GPIO_IO07__LPI2C7_SCL 0x40000b9e 560 MX93_PAD_GPIO_IO06__LPI2C7_SDA 0x40000b9e 561 >; 562 }; 563 564 pinctrl_lpi2c7_gpio: lpi2c7-gpiogrp { 565 fsl,pins = < 566 MX93_PAD_GPIO_IO07__GPIO2_IO07 0x31e 567 MX93_PAD_GPIO_IO06__GPIO2_IO06 0x31e 568 >; 569 }; 570 571 pinctrl_lpspi8: lpspi8grp { 572 fsl,pins = < 573 MX93_PAD_GPIO_IO00__GPIO2_IO00 0x31e 574 MX93_PAD_GPIO_IO01__GPIO2_IO01 0x31e 575 MX93_PAD_GPIO_IO12__GPIO2_IO12 0x31e 576 MX93_PAD_GPIO_IO13__LPSPI8_SIN 0x31e 577 MX93_PAD_GPIO_IO14__LPSPI8_SOUT 0x31e 578 MX93_PAD_GPIO_IO15__LPSPI8_SCK 0x31e 579 >; 580 }; 581 582 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 583 fsl,pins = < 584 MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x31e 585 >; 586 }; 587 588 pinctrl_rtc: rtcgrp { 589 fsl,pins = < 590 MX93_PAD_GPIO_IO02__GPIO2_IO02 0x31e 591 >; 592 }; 593 594 pinctrl_tpm3: tpm3grp { 595 fsl,pins = < 596 MX93_PAD_GPIO_IO24__TPM3_CH3 0x51e 597 >; 598 }; 599 600 pinctrl_uart1: uart1grp { 601 fsl,pins = < 602 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 603 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e 604 >; 605 }; 606 607 pinctrl_uart6: uart6grp { 608 fsl,pins = < 609 MX93_PAD_GPIO_IO05__LPUART6_RX 0x31e 610 MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e 611 >; 612 }; 613 614 pinctrl_uart7: uart7grp { 615 fsl,pins = < 616 MX93_PAD_GPIO_IO09__LPUART7_RX 0x31e 617 MX93_PAD_GPIO_IO08__LPUART7_TX 0x31e 618 >; 619 }; 620 621 pinctrl_usdhc2: usdhc2grp { 622 fsl,pins = < 623 MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 624 MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 625 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 626 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 627 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 628 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 629 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 630 >; 631 }; 632 633 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 634 fsl,pins = < 635 MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e 636 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e 637 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e 638 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e 639 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e 640 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e 641 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 642 >; 643 }; 644 645 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 646 fsl,pins = < 647 MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe 648 MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe 649 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe 650 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe 651 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe 652 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe 653 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 654 >; 655 }; 656 657 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 658 fsl,pins = < 659 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 660 >; 661 }; 662}; 663