1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/dts-v1/; 3 4#include <dt-bindings/usb/pd.h> 5#include "imx93.dtsi" 6 7/ { 8 compatible = "fsl,imx93-11x11-frdm", "fsl,imx93"; 9 model = "NXP i.MX93 11X11 FRDM board"; 10 11 aliases { 12 can0 = &flexcan2; 13 ethernet0 = &fec; 14 ethernet1 = &eqos; 15 i2c0 = &lpi2c1; 16 i2c1 = &lpi2c2; 17 i2c2 = &lpi2c3; 18 mmc0 = &usdhc1; /* EMMC */ 19 mmc1 = &usdhc2; /* uSD */ 20 rtc0 = &pcf2131; 21 serial0 = &lpuart1; 22 serial4 = &lpuart5; 23 }; 24 25 chosen { 26 stdout-path = &lpuart1; 27 }; 28 29 flexcan2_phy: can-phy { 30 compatible = "nxp,tja1051"; 31 #phy-cells = <0>; 32 max-bitrate = <5000000>; 33 silent-gpios = <&pcal6524 23 GPIO_ACTIVE_HIGH>; 34 }; 35 36 gpio-keys { 37 compatible = "gpio-keys"; 38 39 button-k2 { 40 label = "Button K2"; 41 linux,code = <BTN_1>; 42 gpios = <&pcal6524 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; 43 interrupt-parent = <&pcal6524>; 44 interrupts = <5 IRQ_TYPE_EDGE_FALLING>; 45 }; 46 47 button-k3 { 48 label = "Button K3"; 49 linux,code = <BTN_2>; 50 gpios = <&pcal6524 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; 51 interrupt-parent = <&pcal6524>; 52 interrupts = <6 IRQ_TYPE_EDGE_FALLING>; 53 }; 54 }; 55 56 reg_usdhc2_vmmc: regulator-usdhc2 { 57 compatible = "regulator-fixed"; 58 off-on-delay-us = <12000>; 59 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 60 pinctrl-names = "default"; 61 regulator-min-microvolt = <3300000>; 62 regulator-max-microvolt = <3300000>; 63 regulator-name = "VSD_3V3"; 64 vin-supply = <&buck4>; 65 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 66 enable-active-high; 67 }; 68 69 reg_usdhc3_vmmc: regulator-usdhc3 { 70 compatible = "regulator-fixed"; 71 regulator-name = "VPCIe_3V3"; 72 regulator-min-microvolt = <3300000>; 73 regulator-max-microvolt = <3300000>; 74 startup-delay-us = <20000>; 75 gpio = <&pcal6524 13 GPIO_ACTIVE_HIGH>; 76 enable-active-high; 77 }; 78 79 reserved-memory { 80 ranges; 81 #address-cells = <2>; 82 #size-cells = <2>; 83 84 linux,cma { 85 compatible = "shared-dma-pool"; 86 alloc-ranges = <0 0x80000000 0 0x30000000>; 87 reusable; 88 size = <0 0x10000000>; 89 linux,cma-default; 90 }; 91 92 rsc_table: rsc-table@2021e000 { 93 reg = <0 0x2021e000 0 0x1000>; 94 no-map; 95 }; 96 97 vdev0vring0: vdev0vring0@a4000000 { 98 reg = <0 0xa4000000 0 0x8000>; 99 no-map; 100 }; 101 102 vdev0vring1: vdev0vring1@a4008000 { 103 reg = <0 0xa4008000 0 0x8000>; 104 no-map; 105 }; 106 107 vdev1vring0: vdev1vring0@a4010000 { 108 reg = <0 0xa4010000 0 0x8000>; 109 no-map; 110 }; 111 112 vdev1vring1: vdev1vring1@a4018000 { 113 reg = <0 0xa4018000 0 0x8000>; 114 no-map; 115 }; 116 117 vdevbuffer: vdevbuffer@a4020000 { 118 compatible = "shared-dma-pool"; 119 reg = <0 0xa4020000 0 0x100000>; 120 no-map; 121 }; 122 }; 123 124 sound-mqs { 125 compatible = "fsl,imx-audio-mqs"; 126 model = "mqs-audio"; 127 audio-cpu = <&sai1>; 128 audio-codec = <&mqs1>; 129 }; 130 131 usdhc3_pwrseq: mmc-pwrseq { 132 compatible = "mmc-pwrseq-simple"; 133 reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; 134 }; 135}; 136 137&adc1 { 138 vref-supply = <&buck5>; 139 status = "okay"; 140}; 141 142&mu1 { 143 status = "okay"; 144}; 145 146&cm33 { 147 mboxes = <&mu1 0 1>, 148 <&mu1 1 1>, 149 <&mu1 3 1>; 150 mbox-names = "tx", "rx", "rxdb"; 151 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 152 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; 153 status = "okay"; 154}; 155 156&eqos { 157 pinctrl-names = "default", "sleep"; 158 pinctrl-0 = <&pinctrl_eqos>; 159 pinctrl-1 = <&pinctrl_eqos_sleep>; 160 phy-handle = <ðphy1>; 161 phy-mode = "rgmii-id"; 162 status = "okay"; 163 164 mdio { 165 compatible = "snps,dwmac-mdio"; 166 #address-cells = <1>; 167 #size-cells = <0>; 168 clock-frequency = <5000000>; 169 170 ethphy1: ethernet-phy@1 { 171 reg = <1>; 172 reset-assert-us = <10000>; 173 reset-deassert-us = <80000>; 174 reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; 175 realtek,clkout-disable; 176 }; 177 }; 178}; 179 180&fec { 181 pinctrl-names = "default", "sleep"; 182 pinctrl-0 = <&pinctrl_fec>; 183 pinctrl-1 = <&pinctrl_fec_sleep>; 184 phy-mode = "rgmii-id"; 185 phy-handle = <ðphy2>; 186 fsl,magic-packet; 187 status = "okay"; 188 189 mdio { 190 #address-cells = <1>; 191 #size-cells = <0>; 192 clock-frequency = <5000000>; 193 194 ethphy2: ethernet-phy@2 { 195 reg = <2>; 196 reset-assert-us = <10000>; 197 reset-deassert-us = <80000>; 198 reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; 199 realtek,clkout-disable; 200 }; 201 }; 202}; 203 204&flexcan2 { 205 phys = <&flexcan2_phy>; 206 pinctrl-0 = <&pinctrl_flexcan2>; 207 pinctrl-1 = <&pinctrl_flexcan2_sleep>; 208 pinctrl-names = "default", "sleep"; 209 status = "okay"; 210}; 211 212&lpi2c1 { 213 clock-frequency = <400000>; 214 pinctrl-0 = <&pinctrl_lpi2c1>; 215 pinctrl-names = "default"; 216 status = "okay"; 217 218 pcal6408: gpio@20 { 219 compatible = "nxp,pcal6408"; 220 reg = <0x20>; 221 #gpio-cells = <2>; 222 gpio-controller; 223 reset-gpios = <&pcal6524 20 GPIO_ACTIVE_LOW>; 224 }; 225}; 226 227&lpi2c2 { 228 clock-frequency = <400000>; 229 pinctrl-0 = <&pinctrl_lpi2c2>; 230 pinctrl-names = "default"; 231 status = "okay"; 232 233 pcal6524: gpio@22 { 234 compatible = "nxp,pcal6524"; 235 reg = <0x22>; 236 #interrupt-cells = <2>; 237 interrupt-controller; 238 interrupt-parent = <&gpio3>; 239 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 240 #gpio-cells = <2>; 241 gpio-controller; 242 pinctrl-0 = <&pinctrl_pcal6524>; 243 pinctrl-names = "default"; 244 /* does not boot with supplier set, because it is the bucks interrupt parent */ 245 /* vcc-supply = <&buck4>; */ 246 }; 247 248 pmic@25 { 249 compatible = "nxp,pca9451a"; 250 reg = <0x25>; 251 interrupt-parent = <&pcal6524>; 252 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 253 254 regulators { 255 256 buck1: BUCK1 { 257 regulator-name = "VDD_SOC_0V8"; 258 regulator-min-microvolt = <610000>; 259 regulator-max-microvolt = <950000>; 260 regulator-always-on; 261 regulator-boot-on; 262 regulator-ramp-delay = <3125>; 263 }; 264 265 buck2: BUCK2 { 266 regulator-name = "LPD4_x_VDDQ_0V6"; 267 regulator-min-microvolt = <600000>; 268 regulator-max-microvolt = <670000>; 269 regulator-always-on; 270 regulator-boot-on; 271 regulator-ramp-delay = <3125>; 272 }; 273 274 buck4: BUCK4 { 275 regulator-name = "VDD_3V3"; 276 regulator-min-microvolt = <3300000>; 277 regulator-max-microvolt = <3300000>; 278 regulator-always-on; 279 regulator-boot-on; 280 }; 281 282 buck5: BUCK5 { 283 regulator-name = "VDD_1V8"; 284 regulator-min-microvolt = <1800000>; 285 regulator-max-microvolt = <1800000>; 286 regulator-always-on; 287 regulator-boot-on; 288 }; 289 290 buck6: BUCK6 { 291 regulator-name = "LPD4_x_VDD2_1V1"; 292 regulator-min-microvolt = <1060000>; 293 regulator-max-microvolt = <1140000>; 294 regulator-always-on; 295 regulator-boot-on; 296 }; 297 298 ldo1: LDO1 { 299 regulator-name = "NVCC_BBSM_1V8"; 300 regulator-min-microvolt = <1620000>; 301 regulator-max-microvolt = <1980000>; 302 regulator-always-on; 303 regulator-boot-on; 304 }; 305 306 ldo4: LDO4 { 307 regulator-name = "VDD_ANA_0V8"; 308 regulator-min-microvolt = <800000>; 309 regulator-max-microvolt = <840000>; 310 regulator-always-on; 311 regulator-boot-on; 312 }; 313 314 ldo5: LDO5 { 315 regulator-name = "NVCC_SD"; 316 regulator-min-microvolt = <1800000>; 317 regulator-max-microvolt = <3300000>; 318 regulator-always-on; 319 regulator-boot-on; 320 }; 321 }; 322 }; 323 324 eeprom: eeprom@50 { 325 compatible = "atmel,24c256"; 326 reg = <0x50>; 327 pagesize = <64>; 328 vcc-supply = <&buck4>; 329 }; 330}; 331 332&lpi2c3 { 333 clock-frequency = <400000>; 334 pinctrl-0 = <&pinctrl_lpi2c3>; 335 pinctrl-names = "default"; 336 status = "okay"; 337 338 ptn5110: tcpc@50 { 339 compatible = "nxp,ptn5110", "tcpci"; 340 reg = <0x50>; 341 interrupt-parent = <&gpio3>; 342 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 343 344 typec1_con: connector { 345 compatible = "usb-c-connector"; 346 data-role = "dual"; 347 label = "USB-C"; 348 op-sink-microwatt = <15000000>; 349 power-role = "dual"; 350 self-powered; 351 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 352 PDO_VAR(5000, 20000, 3000)>; 353 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 354 try-power-role = "sink"; 355 356 ports { 357 #address-cells = <1>; 358 #size-cells = <0>; 359 360 port@0 { 361 reg = <0>; 362 363 typec1_dr_sw: endpoint { 364 remote-endpoint = <&usb1_drd_sw>; 365 }; 366 }; 367 }; 368 }; 369 }; 370 371 pcf2131: rtc@53 { 372 compatible = "nxp,pcf2131"; 373 reg = <0x53>; 374 interrupt-parent = <&pcal6524>; 375 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 376 }; 377}; 378 379&lpuart1 { /* console */ 380 pinctrl-0 = <&pinctrl_uart1>; 381 pinctrl-names = "default"; 382 status = "okay"; 383}; 384 385&lpuart5 { 386 pinctrl-0 = <&pinctrl_uart5>; 387 pinctrl-names = "default"; 388 status = "okay"; 389 390 uart-has-rtscts; 391 392 bluetooth { 393 compatible = "nxp,88w8987-bt"; 394 device-wakeup-gpios = <&pcal6408 3 GPIO_ACTIVE_HIGH>; 395 reset-gpios = <&pcal6524 19 GPIO_ACTIVE_LOW>; 396 vcc-supply = <®_usdhc3_vmmc>; 397 }; 398}; 399 400&mqs1 { 401 pinctrl-names = "default"; 402 pinctrl-0 = <&pinctrl_mqs1>; 403 clocks = <&clk IMX93_CLK_MQS1_GATE>; 404 clock-names = "mclk"; 405 status = "okay"; 406}; 407 408&sai1 { 409 #sound-dai-cells = <0>; 410 clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, 411 <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, 412 <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUDIO_PLL>; 413 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k"; 414 assigned-clocks = <&clk IMX93_CLK_SAI1>; 415 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 416 assigned-clock-rates = <24576000>; 417 fsl,sai-mclk-direction-output; 418 status = "okay"; 419}; 420 421&usbotg1 { 422 adp-disable; 423 disable-over-current; 424 dr_mode = "otg"; 425 hnp-disable; 426 srp-disable; 427 usb-role-switch; 428 samsung,picophy-dc-vol-level-adjust = <7>; 429 samsung,picophy-pre-emp-curr-control = <3>; 430 status = "okay"; 431 432 port { 433 usb1_drd_sw: endpoint { 434 remote-endpoint = <&typec1_dr_sw>; 435 }; 436 }; 437}; 438 439&usbotg2 { 440 disable-over-current; 441 dr_mode = "host"; 442 samsung,picophy-dc-vol-level-adjust = <7>; 443 samsung,picophy-pre-emp-curr-control = <3>; 444 status = "okay"; 445}; 446 447&usdhc1 { 448 bus-width = <8>; 449 non-removable; 450 pinctrl-0 = <&pinctrl_usdhc1>; 451 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 452 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 453 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 454 vmmc-supply = <&buck4>; 455 status = "okay"; 456}; 457 458&usdhc2 { 459 bus-width = <4>; 460 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; 461 no-mmc; 462 no-sdio; 463 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 464 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 465 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 466 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; 467 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 468 vmmc-supply = <®_usdhc2_vmmc>; 469 status = "okay"; 470}; 471 472&usdhc3 { 473 bus-width = <4>; 474 keep-power-in-suspend; 475 mmc-pwrseq = <&usdhc3_pwrseq>; 476 non-removable; 477 pinctrl-0 = <&pinctrl_usdhc3>; 478 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 479 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 480 pinctrl-3 = <&pinctrl_usdhc3_sleep>; 481 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 482 vmmc-supply = <®_usdhc3_vmmc>; 483 status = "okay"; 484}; 485 486&wdog3 { 487 pinctrl-names = "default"; 488 pinctrl-0 = <&pinctrl_wdog>; 489 fsl,ext-reset-output; 490 status = "okay"; 491}; 492 493&iomuxc { 494 495 pinctrl_eqos: eqosgrp { 496 fsl,pins = < 497 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e 498 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e 499 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 500 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 501 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e 502 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e 503 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e 504 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 505 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e 506 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e 507 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e 508 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e 509 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e 510 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e 511 >; 512 }; 513 514 pinctrl_eqos_sleep: eqossleepgrp { 515 fsl,pins = < 516 MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e 517 MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e 518 MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e 519 MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e 520 MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e 521 MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e 522 MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e 523 MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e 524 MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e 525 MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e 526 MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e 527 MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e 528 MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e 529 MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e 530 >; 531 }; 532 533 pinctrl_fec: fecgrp { 534 fsl,pins = < 535 MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e 536 MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e 537 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e 538 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e 539 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e 540 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e 541 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e 542 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e 543 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e 544 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e 545 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e 546 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e 547 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e 548 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e 549 >; 550 }; 551 552 pinctrl_fec_sleep: fecsleepgrp { 553 fsl,pins = < 554 MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e 555 MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e 556 MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e 557 MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e 558 MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e 559 MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e 560 MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e 561 MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e 562 MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e 563 MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e 564 MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e 565 MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e 566 MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e 567 MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e 568 >; 569 }; 570 571 pinctrl_flexcan2: flexcan2grp { 572 fsl,pins = < 573 MX93_PAD_GPIO_IO25__CAN2_TX 0x139e 574 MX93_PAD_GPIO_IO27__CAN2_RX 0x139e 575 >; 576 }; 577 578 pinctrl_flexcan2_sleep: flexcan2sleepgrp { 579 fsl,pins = < 580 MX93_PAD_GPIO_IO25__GPIO2_IO25 0x31e 581 MX93_PAD_GPIO_IO27__GPIO2_IO27 0x31e 582 >; 583 }; 584 585 pinctrl_lpi2c1: lpi2c1grp { 586 fsl,pins = < 587 MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e 588 MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e 589 >; 590 }; 591 592 pinctrl_lpi2c2: lpi2c2grp { 593 fsl,pins = < 594 MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e 595 MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e 596 >; 597 }; 598 599 pinctrl_lpi2c3: lpi2c3grp { 600 fsl,pins = < 601 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e 602 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e 603 >; 604 }; 605 606 pinctrl_mqs1: mqs1grp { 607 fsl,pins = < 608 MX93_PAD_PDM_CLK__MQS1_LEFT 0x31e 609 MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x31e 610 >; 611 }; 612 613 pinctrl_pcal6524: pcal6524grp { 614 fsl,pins = < 615 MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e 616 >; 617 }; 618 619 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 620 fsl,pins = < 621 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e 622 >; 623 }; 624 625 pinctrl_uart1: uart1grp { 626 fsl,pins = < 627 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 628 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e 629 >; 630 }; 631 632 pinctrl_uart5: uart5grp { 633 fsl,pins = < 634 MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e 635 MX93_PAD_DAP_TDI__LPUART5_RX 0x31e 636 MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e 637 MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e 638 >; 639 }; 640 641 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 642 pinctrl_usdhc1: usdhc1grp { 643 fsl,pins = < 644 MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 645 MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 646 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 647 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 648 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 649 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 650 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 651 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 652 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 653 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 654 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 655 >; 656 }; 657 658 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 659 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 660 fsl,pins = < 661 MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e 662 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e 663 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e 664 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e 665 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e 666 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e 667 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e 668 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e 669 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e 670 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e 671 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 672 >; 673 }; 674 675 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 676 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 677 fsl,pins = < 678 MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe 679 MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe 680 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe 681 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe 682 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe 683 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe 684 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe 685 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe 686 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe 687 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe 688 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 689 >; 690 }; 691 692 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 693 fsl,pins = < 694 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 695 >; 696 }; 697 698 pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { 699 fsl,pins = < 700 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e 701 >; 702 }; 703 704 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 705 pinctrl_usdhc2: usdhc2grp { 706 fsl,pins = < 707 MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 708 MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 709 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 710 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 711 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 712 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 713 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 714 >; 715 }; 716 717 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 718 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 719 fsl,pins = < 720 MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e 721 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e 722 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e 723 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e 724 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e 725 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e 726 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 727 >; 728 }; 729 730 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 731 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 732 fsl,pins = < 733 MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe 734 MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe 735 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe 736 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe 737 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe 738 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe 739 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 740 >; 741 }; 742 743 pinctrl_usdhc2_sleep: usdhc2-sleepgrp { 744 fsl,pins = < 745 MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e 746 MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e 747 MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e 748 MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e 749 MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e 750 MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e 751 MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e 752 >; 753 }; 754 755 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 756 pinctrl_usdhc3: usdhc3grp { 757 fsl,pins = < 758 MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582 759 MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382 760 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382 761 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382 762 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382 763 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382 764 >; 765 }; 766 767 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 768 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 769 fsl,pins = < 770 MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e 771 MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e 772 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e 773 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e 774 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e 775 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e 776 >; 777 }; 778 779 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 780 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 781 fsl,pins = < 782 MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe 783 MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe 784 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe 785 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe 786 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe 787 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe 788 >; 789 }; 790 791 pinctrl_usdhc3_sleep: usdhc3grpsleepgrp { 792 fsl,pins = < 793 MX93_PAD_SD3_CLK__GPIO3_IO20 0x31e 794 MX93_PAD_SD3_CMD__GPIO3_IO21 0x31e 795 MX93_PAD_SD3_DATA0__GPIO3_IO22 0x31e 796 MX93_PAD_SD3_DATA1__GPIO3_IO23 0x31e 797 MX93_PAD_SD3_DATA2__GPIO3_IO24 0x31e 798 MX93_PAD_SD3_DATA3__GPIO3_IO25 0x31e 799 >; 800 }; 801 802 pinctrl_wdog: wdoggrp { 803 fsl,pins = < 804 MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e 805 >; 806 }; 807}; 808