1*b0830e7eSJoy Zou// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*b0830e7eSJoy Zou/* 3*b0830e7eSJoy Zou * Copyright 2025 NXP 4*b0830e7eSJoy Zou */ 5*b0830e7eSJoy Zou 6*b0830e7eSJoy Zou#include "imx91-pinfunc.h" 7*b0830e7eSJoy Zou#include "imx91_93_common.dtsi" 8*b0830e7eSJoy Zou 9*b0830e7eSJoy Zou&clk { 10*b0830e7eSJoy Zou compatible = "fsl,imx91-ccm"; 11*b0830e7eSJoy Zou}; 12*b0830e7eSJoy Zou 13*b0830e7eSJoy Zou&ddr_pmu { 14*b0830e7eSJoy Zou compatible = "fsl,imx91-ddr-pmu", "fsl,imx93-ddr-pmu"; 15*b0830e7eSJoy Zou}; 16*b0830e7eSJoy Zou 17*b0830e7eSJoy Zou&eqos { 18*b0830e7eSJoy Zou clocks = <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>, 19*b0830e7eSJoy Zou <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>, 20*b0830e7eSJoy Zou <&clk IMX91_CLK_ENET_TIMER>, 21*b0830e7eSJoy Zou <&clk IMX91_CLK_ENET1_QOS_TSN>, 22*b0830e7eSJoy Zou <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>; 23*b0830e7eSJoy Zou assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>, 24*b0830e7eSJoy Zou <&clk IMX91_CLK_ENET1_QOS_TSN>; 25*b0830e7eSJoy Zou assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 26*b0830e7eSJoy Zou <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; 27*b0830e7eSJoy Zou assigned-clock-rates = <100000000>, <250000000>; 28*b0830e7eSJoy Zou}; 29*b0830e7eSJoy Zou 30*b0830e7eSJoy Zou&fec { 31*b0830e7eSJoy Zou clocks = <&clk IMX91_CLK_ENET2_REGULAR_GATE>, 32*b0830e7eSJoy Zou <&clk IMX91_CLK_ENET2_REGULAR_GATE>, 33*b0830e7eSJoy Zou <&clk IMX91_CLK_ENET_TIMER>, 34*b0830e7eSJoy Zou <&clk IMX91_CLK_ENET2_REGULAR>, 35*b0830e7eSJoy Zou <&clk IMX93_CLK_DUMMY>; 36*b0830e7eSJoy Zou assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>, 37*b0830e7eSJoy Zou <&clk IMX91_CLK_ENET2_REGULAR>; 38*b0830e7eSJoy Zou assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 39*b0830e7eSJoy Zou <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; 40*b0830e7eSJoy Zou assigned-clock-rates = <100000000>, <250000000>; 41*b0830e7eSJoy Zou}; 42*b0830e7eSJoy Zou 43*b0830e7eSJoy Zou&i3c1 { 44*b0830e7eSJoy Zou clocks = <&clk IMX93_CLK_BUS_AON>, 45*b0830e7eSJoy Zou <&clk IMX93_CLK_I3C1_GATE>, 46*b0830e7eSJoy Zou <&clk IMX93_CLK_DUMMY>; 47*b0830e7eSJoy Zou}; 48*b0830e7eSJoy Zou 49*b0830e7eSJoy Zou&i3c2 { 50*b0830e7eSJoy Zou clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 51*b0830e7eSJoy Zou <&clk IMX93_CLK_I3C2_GATE>, 52*b0830e7eSJoy Zou <&clk IMX93_CLK_DUMMY>; 53*b0830e7eSJoy Zou}; 54*b0830e7eSJoy Zou 55*b0830e7eSJoy Zou&iomuxc { 56*b0830e7eSJoy Zou compatible = "fsl,imx91-iomuxc"; 57*b0830e7eSJoy Zou}; 58*b0830e7eSJoy Zou 59*b0830e7eSJoy Zou&media_blk_ctrl { 60*b0830e7eSJoy Zou compatible = "fsl,imx91-media-blk-ctrl", "syscon"; 61*b0830e7eSJoy Zou clocks = <&clk IMX93_CLK_MEDIA_APB>, 62*b0830e7eSJoy Zou <&clk IMX93_CLK_MEDIA_AXI>, 63*b0830e7eSJoy Zou <&clk IMX93_CLK_NIC_MEDIA_GATE>, 64*b0830e7eSJoy Zou <&clk IMX93_CLK_MEDIA_DISP_PIX>, 65*b0830e7eSJoy Zou <&clk IMX93_CLK_CAM_PIX>, 66*b0830e7eSJoy Zou <&clk IMX93_CLK_LCDIF_GATE>, 67*b0830e7eSJoy Zou <&clk IMX93_CLK_ISI_GATE>, 68*b0830e7eSJoy Zou <&clk IMX93_CLK_MIPI_CSI_GATE>; 69*b0830e7eSJoy Zou clock-names = "apb", "axi", "nic", "disp", "cam", 70*b0830e7eSJoy Zou "lcdif", "isi", "csi"; 71*b0830e7eSJoy Zou}; 72