1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2025 NXP 4 */ 5 6#include "imx91-pinfunc.h" 7#include "imx91_93_common.dtsi" 8 9&clk { 10 compatible = "fsl,imx91-ccm"; 11}; 12 13&ddr_pmu { 14 compatible = "fsl,imx91-ddr-pmu", "fsl,imx93-ddr-pmu"; 15}; 16 17&eqos { 18 clocks = <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>, 19 <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>, 20 <&clk IMX91_CLK_ENET_TIMER>, 21 <&clk IMX91_CLK_ENET1_QOS_TSN>, 22 <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>; 23 assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>, 24 <&clk IMX91_CLK_ENET1_QOS_TSN>; 25 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 26 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; 27 assigned-clock-rates = <100000000>, <250000000>; 28}; 29 30&fec { 31 clocks = <&clk IMX91_CLK_ENET2_REGULAR_GATE>, 32 <&clk IMX91_CLK_ENET2_REGULAR_GATE>, 33 <&clk IMX91_CLK_ENET_TIMER>, 34 <&clk IMX91_CLK_ENET2_REGULAR>, 35 <&clk IMX93_CLK_DUMMY>; 36 assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>, 37 <&clk IMX91_CLK_ENET2_REGULAR>; 38 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 39 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; 40 assigned-clock-rates = <100000000>, <250000000>; 41}; 42 43&i3c1 { 44 clocks = <&clk IMX93_CLK_BUS_AON>, 45 <&clk IMX93_CLK_I3C1_GATE>, 46 <&clk IMX93_CLK_DUMMY>; 47}; 48 49&i3c2 { 50 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 51 <&clk IMX93_CLK_I3C2_GATE>, 52 <&clk IMX93_CLK_DUMMY>; 53}; 54 55&iomuxc { 56 compatible = "fsl,imx91-iomuxc"; 57}; 58 59&media_blk_ctrl { 60 compatible = "fsl,imx91-media-blk-ctrl", "syscon"; 61 clocks = <&clk IMX93_CLK_MEDIA_APB>, 62 <&clk IMX93_CLK_MEDIA_AXI>, 63 <&clk IMX93_CLK_NIC_MEDIA_GATE>, 64 <&clk IMX93_CLK_MEDIA_DISP_PIX>, 65 <&clk IMX93_CLK_CAM_PIX>, 66 <&clk IMX93_CLK_LCDIF_GATE>, 67 <&clk IMX93_CLK_ISI_GATE>, 68 <&clk IMX93_CLK_MIPI_CSI_GATE>; 69 clock-names = "apb", "axi", "nic", "disp", "cam", 70 "lcdif", "isi", "csi"; 71}; 72