1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Common dtsi for Variscite DART-MX91 4 * 5 * Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-91/dart-mx91/ 6 * 7 * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ 8 * 9 */ 10 11/dts-v1/; 12 13#include <dt-bindings/leds/common.h> 14#include <dt-bindings/usb/pd.h> 15#include "imx91.dtsi" 16 17/ { 18 model = "Variscite DART-MX91 Module"; 19 compatible = "variscite,var-dart-mx91", "fsl,imx91"; 20 21 sound-wm8904 { 22 compatible = "simple-audio-card"; 23 simple-audio-card,bitclock-master = <&codec_dai>; 24 simple-audio-card,format = "i2s"; 25 simple-audio-card,frame-master = <&codec_dai>; 26 simple-audio-card,mclk-fs = <256>; 27 simple-audio-card,name = "wm8904-audio"; 28 simple-audio-card,routing = 29 "Headphone Jack", "HPOUTL", 30 "Headphone Jack", "HPOUTR", 31 "IN2L", "Line In Jack", 32 "IN2R", "Line In Jack", 33 "IN1L", "Microphone Jack", 34 "IN1R", "Microphone Jack"; 35 simple-audio-card,widgets = 36 "Microphone", "Microphone Jack", 37 "Headphone", "Headphone Jack", 38 "Line", "Line In Jack"; 39 40 codec_dai: simple-audio-card,codec { 41 sound-dai = <&wm8904>; 42 }; 43 44 simple-audio-card,cpu { 45 sound-dai = <&sai1>; 46 }; 47 }; 48 49 wifi_pwrseq: wifi-pwrseq { 50 compatible = "mmc-pwrseq-simple"; 51 post-power-on-delay-ms = <100>; 52 power-off-delay-us = <10000>; 53 reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ 54 <&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ 55 }; 56}; 57 58&eqos { 59 pinctrl-names = "default", "sleep"; 60 pinctrl-0 = <&pinctrl_eqos>; 61 pinctrl-1 = <&pinctrl_eqos_sleep>; 62 /* 63 * The required RGMII TX and RX 2ns delays are implemented directly 64 * in hardware via passive delay elements on the SOM PCB. 65 * No delay configuration is needed in software via PHY driver. 66 */ 67 phy-mode = "rgmii"; 68 phy-handle = <ðphy0>; 69 snps,clk-csr = <5>; 70 status = "okay"; 71 72 mdio { 73 compatible = "snps,dwmac-mdio"; 74 clock-frequency = <1000000>; 75 #address-cells = <1>; 76 #size-cells = <0>; 77 78 ethphy0: ethernet-phy@0 { 79 compatible = "ethernet-phy-ieee802.3-c22"; 80 reg = <0>; 81 reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; 82 reset-assert-us = <15000>; 83 reset-deassert-us = <100000>; 84 85 leds { 86 #address-cells = <1>; 87 #size-cells = <0>; 88 89 led@0 { 90 reg = <0>; 91 color = <LED_COLOR_ID_YELLOW>; 92 function = LED_FUNCTION_LAN; 93 linux,default-trigger = "netdev"; 94 }; 95 96 led@1 { 97 reg = <1>; 98 color = <LED_COLOR_ID_GREEN>; 99 function = LED_FUNCTION_LAN; 100 linux,default-trigger = "netdev"; 101 }; 102 }; 103 }; 104 }; 105}; 106 107&lpi2c3 { 108 clock-frequency = <400000>; 109 pinctrl-names = "default", "sleep", "gpio"; 110 pinctrl-0 = <&pinctrl_lpi2c3>; 111 pinctrl-1 = <&pinctrl_lpi2c3_gpio>; 112 pinctrl-2 = <&pinctrl_lpi2c3_gpio>; 113 scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 114 sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 115 status = "okay"; 116 117 wm8904: audio-codec@1a { 118 compatible = "wlf,wm8904"; 119 reg = <0x1a>; 120 #sound-dai-cells = <0>; 121 clocks = <&clk IMX93_CLK_SAI1_GATE>; 122 clock-names = "mclk"; 123 AVDD-supply = <&buck5>; 124 CPVDD-supply = <&buck5>; 125 DBVDD-supply = <&buck4>; 126 DCVDD-supply = <&buck5>; 127 MICVDD-supply = <&buck5>; 128 wlf,drc-cfg-names = "default", "peaklimiter", "tradition", 129 "soft", "music"; 130 /* 131 * Config registers per name, respectively: 132 * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 133 * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 134 * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 135 * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 136 * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 137 */ 138 wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, 139 /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, 140 /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, 141 /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, 142 /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; 143 /* GPIO1 = DMIC_CLK, don't touch others */ 144 wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; 145 /* DMIC is connected to IN1L */ 146 wlf,in1l-as-dmicdat1; 147 }; 148 149 pmic@25 { 150 compatible = "nxp,pca9451a"; 151 reg = <0x25>; 152 153 regulators { 154 buck1: BUCK1 { 155 regulator-name = "BUCK1"; 156 regulator-min-microvolt = <650000>; 157 regulator-max-microvolt = <2237500>; 158 regulator-boot-on; 159 regulator-always-on; 160 regulator-ramp-delay = <3125>; 161 }; 162 163 buck2: BUCK2 { 164 regulator-name = "BUCK2"; 165 regulator-min-microvolt = <600000>; 166 regulator-max-microvolt = <2187500>; 167 regulator-boot-on; 168 regulator-always-on; 169 regulator-ramp-delay = <3125>; 170 }; 171 172 buck4: BUCK4 { 173 regulator-name = "BUCK4"; 174 regulator-min-microvolt = <600000>; 175 regulator-max-microvolt = <3400000>; 176 regulator-boot-on; 177 regulator-always-on; 178 }; 179 180 buck5: BUCK5 { 181 regulator-name = "BUCK5"; 182 regulator-min-microvolt = <600000>; 183 regulator-max-microvolt = <3400000>; 184 regulator-boot-on; 185 regulator-always-on; 186 }; 187 188 buck6: BUCK6 { 189 regulator-name = "BUCK6"; 190 regulator-min-microvolt = <600000>; 191 regulator-max-microvolt = <3400000>; 192 regulator-boot-on; 193 regulator-always-on; 194 }; 195 196 ldo1: LDO1 { 197 regulator-name = "LDO1"; 198 regulator-min-microvolt = <1600000>; 199 regulator-max-microvolt = <3300000>; 200 regulator-boot-on; 201 regulator-always-on; 202 }; 203 204 ldo4: LDO4 { 205 regulator-name = "LDO4"; 206 regulator-min-microvolt = <800000>; 207 regulator-max-microvolt = <3300000>; 208 regulator-boot-on; 209 regulator-always-on; 210 }; 211 212 ldo5: LDO5 { 213 regulator-name = "LDO5"; 214 regulator-min-microvolt = <1800000>; 215 regulator-max-microvolt = <3300000>; 216 regulator-boot-on; 217 regulator-always-on; 218 }; 219 }; 220 }; 221}; 222 223/* BT module */ 224&lpuart5 { 225 pinctrl-names = "default"; 226 pinctrl-0 = <&pinctrl_uart5>, <&pinctrl_bt>; 227 uart-has-rtscts; 228 status = "okay"; 229 230 bluetooth { 231 compatible = "nxp,88w8987-bt"; 232 }; 233}; 234 235&sai1 { 236 pinctrl-names = "default", "sleep"; 237 pinctrl-0 = <&pinctrl_sai1>; 238 pinctrl-1 = <&pinctrl_sai1_sleep>; 239 assigned-clocks = <&clk IMX93_CLK_SAI1>; 240 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 241 assigned-clock-rates = <12288000>; 242 #sound-dai-cells = <0>; 243 fsl,sai-mclk-direction-output; 244 status = "okay"; 245}; 246 247/* eMMC */ 248&usdhc1 { 249 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 250 pinctrl-0 = <&pinctrl_usdhc1>; 251 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 252 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 253 bus-width = <8>; 254 non-removable; 255 status = "okay"; 256}; 257 258/* WiFi */ 259&usdhc3 { 260 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 261 pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; 262 pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>; 263 pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>; 264 pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>; 265 mmc-pwrseq = <&wifi_pwrseq>; 266 keep-power-in-suspend; 267 bus-width = <4>; 268 non-removable; 269 wakeup-source; 270 status = "okay"; 271}; 272 273&wdog3 { 274 status = "okay"; 275}; 276 277&iomuxc { 278 pinctrl_bt: btgrp { 279 fsl,pins = < 280 MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e 281 >; 282 }; 283 284 pinctrl_eqos: eqosgrp { 285 fsl,pins = < 286 MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e 287 MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e 288 MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 289 MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 290 MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e 291 MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e 292 MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe 293 MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 294 MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e 295 MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e 296 MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e 297 MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e 298 MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe 299 MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e 300 MX91_PAD_UART2_TXD__GPIO1_IO7 0x51e 301 >; 302 }; 303 304 pinctrl_eqos_sleep: eqos-sleepgrp { 305 fsl,pins = < 306 MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e 307 MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e 308 MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e 309 MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e 310 MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e 311 MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e 312 MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e 313 MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e 314 MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e 315 MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e 316 MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e 317 MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e 318 MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e 319 MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e 320 >; 321 }; 322 323 pinctrl_lpi2c3: lpi2c3grp { 324 fsl,pins = < 325 MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e 326 MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e 327 >; 328 }; 329 330 pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { 331 fsl,pins = < 332 MX91_PAD_GPIO_IO28__GPIO2_IO28 0x40000b9e 333 MX91_PAD_GPIO_IO29__GPIO2_IO29 0x40000b9e 334 >; 335 }; 336 337 pinctrl_sai1: sai1grp { 338 fsl,pins = < 339 MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e 340 MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e 341 MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x31e 342 MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x31e 343 MX91_PAD_I2C2_SDA__SAI1_RX_BCLK 0x31e 344 MX91_PAD_I2C2_SCL__SAI1_RX_SYNC 0x31e 345 MX91_PAD_UART2_RXD__SAI1_MCLK 0x31e 346 >; 347 }; 348 349 pinctrl_sai1_sleep: sai1-sleepgrp { 350 fsl,pins = < 351 MX91_PAD_SAI1_TXC__GPIO1_IO12 0x31e 352 MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x31e 353 MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x31e 354 MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x31e 355 MX91_PAD_UART2_RXD__GPIO1_IO6 0x31e 356 MX91_PAD_I2C2_SDA__GPIO1_IO3 0x31e 357 MX91_PAD_I2C2_SCL__GPIO1_IO2 0x31e 358 >; 359 }; 360 361 pinctrl_uart5: uart5grp { 362 fsl,pins = < 363 MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e 364 MX91_PAD_DAP_TDI__LPUART5_RX 0x31e 365 MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e 366 MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e 367 >; 368 }; 369 370 pinctrl_usdhc1: usdhc1grp { 371 fsl,pins = < 372 MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582 373 MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382 374 MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382 375 MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382 376 MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382 377 MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382 378 MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382 379 MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382 380 MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382 381 MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382 382 MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 383 >; 384 }; 385 386 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 387 fsl,pins = < 388 MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e 389 MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e 390 MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 391 MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 392 MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 393 MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 394 MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 395 MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 396 MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 397 MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 398 MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 399 >; 400 }; 401 402 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 403 fsl,pins = < 404 MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe 405 MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe 406 MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe 407 MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe 408 MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe 409 MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe 410 MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe 411 MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe 412 MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe 413 MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe 414 MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 415 >; 416 }; 417 418 pinctrl_usdhc3: usdhc3grp { 419 fsl,pins = < 420 MX91_PAD_SD3_CLK__USDHC3_CLK 0x1582 421 MX91_PAD_SD3_CMD__USDHC3_CMD 0x1382 422 MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x1382 423 MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x1382 424 MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x1382 425 MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x1382 426 >; 427 }; 428 429 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 430 fsl,pins = < 431 MX91_PAD_SD3_CLK__USDHC3_CLK 0x158e 432 MX91_PAD_SD3_CMD__USDHC3_CMD 0x138e 433 MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x138e 434 MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x138e 435 MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x138e 436 MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x138e 437 >; 438 }; 439 440 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 441 fsl,pins = < 442 MX91_PAD_SD3_CLK__USDHC3_CLK 0x15fe 443 MX91_PAD_SD3_CMD__USDHC3_CMD 0x13fe 444 MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe 445 MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe 446 MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe 447 MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe 448 >; 449 }; 450 451 pinctrl_usdhc3_sleep: usdhc3-sleepgrp { 452 fsl,pins = < 453 MX91_PAD_SD3_CLK__GPIO3_IO20 0x31e 454 MX91_PAD_SD3_CMD__GPIO3_IO21 0x31e 455 MX91_PAD_SD3_DATA0__GPIO3_IO22 0x31e 456 MX91_PAD_SD3_DATA1__GPIO3_IO23 0x31e 457 MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e 458 MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e 459 >; 460 }; 461 462 pinctrl_usdhc3_wlan: usdhc3wlangrp { 463 fsl,pins = < 464 MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e 465 MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x51e 466 >; 467 }; 468}; 469