1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Variscite Sonata carrier board for DART-MX91 4 * 5 * Link: https://variscite.com/carrier-boards/sonata-board/ 6 * 7 * Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/ 8 * 9 */ 10 11/dts-v1/; 12 13#include "imx91-var-dart.dtsi" 14 15/ { 16 model = "Variscite DART-MX91 on Sonata-Board"; 17 compatible = "variscite,var-dart-mx91-sonata", 18 "variscite,var-dart-mx91", 19 "fsl,imx91"; 20 21 aliases { 22 ethernet0 = &eqos; 23 ethernet1 = &fec; 24 gpio0 = &gpio1; 25 gpio1 = &gpio2; 26 gpio2 = &gpio3; 27 i2c0 = &lpi2c1; 28 i2c1 = &lpi2c2; 29 i2c2 = &lpi2c3; 30 mmc0 = &usdhc1; 31 mmc1 = &usdhc2; 32 serial0 = &lpuart1; 33 serial1 = &lpuart2; 34 serial2 = &lpuart3; 35 serial3 = &lpuart4; 36 serial4 = &lpuart5; 37 serial5 = &lpuart6; 38 }; 39 40 chosen { 41 stdout-path = &lpuart1; 42 }; 43 44 gpio-keys { 45 compatible = "gpio-keys"; 46 47 button-home { 48 label = "Home"; 49 linux,code = <KEY_HOME>; 50 gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>; 51 wakeup-source; 52 }; 53 54 button-up { 55 label = "Up"; 56 linux,code = <KEY_UP>; 57 gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>; 58 wakeup-source; 59 }; 60 61 button-down { 62 label = "Down"; 63 linux,code = <KEY_DOWN>; 64 gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>; 65 wakeup-source; 66 }; 67 68 button-back { 69 label = "Back"; 70 linux,code = <KEY_BACK>; 71 gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>; 72 wakeup-source; 73 }; 74 }; 75 76 gpio-leds { 77 compatible = "gpio-leds"; 78 79 led-emmc { 80 label = "eMMC"; 81 gpios = <&pca6408_2 7 GPIO_ACTIVE_HIGH>; 82 linux,default-trigger = "mmc0"; 83 }; 84 }; 85 86 reg_vref_1v8: regulator-adc-vref { 87 compatible = "regulator-fixed"; 88 regulator-name = "vref_1v8"; 89 regulator-min-microvolt = <1800000>; 90 regulator-max-microvolt = <1800000>; 91 }; 92 93 reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { 94 compatible = "regulator-fixed"; 95 pinctrl-names = "default"; 96 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 97 regulator-name = "VDD_SD2_3V3"; 98 regulator-min-microvolt = <3300000>; 99 regulator-max-microvolt = <3300000>; 100 gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; 101 enable-active-high; 102 off-on-delay-us = <20000>; 103 }; 104 105 reserved-memory { 106 ranges; 107 #address-cells = <2>; 108 #size-cells = <2>; 109 110 linux,cma { 111 compatible = "shared-dma-pool"; 112 alloc-ranges = <0 0x80000000 0 0x40000000>; 113 reusable; 114 size = <0 0x10000000>; 115 linux,cma-default; 116 }; 117 }; 118}; 119 120&adc1 { 121 vref-supply = <®_vref_1v8>; 122 status = "okay"; 123}; 124 125/* Use external instead of internal RTC */ 126&bbnsm_rtc { 127 status = "disabled"; 128}; 129 130&eqos { 131 mdio { 132 ethphy1: ethernet-phy@1 { 133 compatible = "ethernet-phy-ieee802.3-c22"; 134 reg = <1>; 135 reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; 136 reset-assert-us = <15000>; 137 reset-deassert-us = <100000>; 138 139 leds { 140 #address-cells = <1>; 141 #size-cells = <0>; 142 143 led@0 { 144 reg = <0>; 145 color = <LED_COLOR_ID_YELLOW>; 146 function = LED_FUNCTION_LAN; 147 linux,default-trigger = "netdev"; 148 }; 149 150 led@1 { 151 reg = <1>; 152 color = <LED_COLOR_ID_GREEN>; 153 function = LED_FUNCTION_LAN; 154 linux,default-trigger = "netdev"; 155 }; 156 }; 157 }; 158 }; 159}; 160 161&fec { 162 pinctrl-names = "default", "sleep"; 163 pinctrl-0 = <&pinctrl_fec>; 164 pinctrl-1 = <&pinctrl_fec_sleep>; 165 /* 166 * The required RGMII TX and RX 2ns delays are implemented directly 167 * in hardware via passive delay elements on the SOM PCB. 168 * No delay configuration is needed in software via PHY driver. 169 */ 170 phy-mode = "rgmii"; 171 phy-handle = <ðphy1>; 172 status = "okay"; 173}; 174 175&flexcan1 { 176 pinctrl-names = "default"; 177 pinctrl-0 = <&pinctrl_flexcan1>; 178 status = "okay"; 179}; 180 181&lpi2c1 { 182 clock-frequency = <400000>; 183 pinctrl-names = "default", "sleep", "gpio"; 184 pinctrl-0 = <&pinctrl_lpi2c1>; 185 pinctrl-1 = <&pinctrl_lpi2c1_gpio>; 186 pinctrl-2 = <&pinctrl_lpi2c1_gpio>; 187 scl-gpios = <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 188 sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 189 status = "okay"; 190 191 pca6408_1: gpio@20 { 192 compatible = "nxp,pcal6408"; 193 reg = <0x20>; 194 gpio-controller; 195 #gpio-cells = <2>; 196 interrupt-parent = <&gpio1>; 197 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 198 }; 199 200 pca6408_2: gpio@21 { 201 compatible = "nxp,pcal6408"; 202 reg = <0x21>; 203 gpio-controller; 204 #gpio-cells = <2>; 205 interrupt-parent = <&gpio1>; 206 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 207 }; 208 209 pca9534: gpio@22 { 210 compatible = "nxp,pca9534"; 211 reg = <0x22>; 212 gpio-controller; 213 #gpio-cells = <2>; 214 interrupt-parent = <&gpio1>; 215 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 216 }; 217 218 st33ktpm2xi2c: tpm@2e { 219 compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; 220 reg = <0x2e>; 221 }; 222 223 /* Capacitive touch controller */ 224 ft5x06_ts: touchscreen@38 { 225 compatible = "edt,edt-ft5206"; 226 reg = <0x38>; 227 pinctrl-names = "default"; 228 pinctrl-0 = <&pinctrl_captouch>; 229 reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>; 230 interrupt-parent = <&gpio3>; 231 interrupts = <27 IRQ_TYPE_EDGE_FALLING>; 232 touchscreen-size-x = <800>; 233 touchscreen-size-y = <480>; 234 touchscreen-inverted-x; 235 touchscreen-inverted-y; 236 wakeup-source; 237 }; 238 239 /* USB Type-C Controller */ 240 typec@3d { 241 compatible = "nxp,ptn5150"; 242 reg = <0x3d>; 243 pinctrl-names = "default"; 244 pinctrl-0 = <&pinctrl_extcon>; 245 interrupt-parent = <&gpio4>; 246 interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; 247 248 port { 249 typec1_dr_sw: endpoint { 250 remote-endpoint = <&usb1_drd_sw>; 251 }; 252 }; 253 }; 254 255 rtc@68 { 256 compatible = "dallas,ds1337"; 257 reg = <0x68>; 258 }; 259}; 260 261/* Console (J10) */ 262&lpuart1 { 263 pinctrl-names = "default"; 264 pinctrl-0 = <&pinctrl_uart1>; 265 status = "okay"; 266}; 267 268/* Header (J12.4, J12.6) */ 269&lpuart6 { 270 pinctrl-names = "default"; 271 pinctrl-0 = <&pinctrl_uart6>; 272 status = "okay"; 273}; 274 275&usbotg1 { 276 dr_mode = "otg"; 277 hnp-disable; 278 srp-disable; 279 adp-disable; 280 usb-role-switch; 281 disable-over-current; 282 samsung,picophy-pre-emp-curr-control = <3>; 283 samsung,picophy-dc-vol-level-adjust = <7>; 284 status = "okay"; 285 286 port { 287 usb1_drd_sw: endpoint { 288 remote-endpoint = <&typec1_dr_sw>; 289 }; 290 }; 291}; 292 293&usbotg2 { 294 disable-over-current; 295 dr_mode = "host"; 296 status = "okay"; 297}; 298 299/* SD */ 300&usdhc2 { 301 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 302 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 303 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 304 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 305 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; 306 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 307 vmmc-supply = <®_usdhc2_vmmc>; 308 bus-width = <4>; 309 no-sdio; 310 no-mmc; 311 status = "okay"; 312}; 313 314&iomuxc { 315 pinctrl-names = "default"; 316 pinctrl-0 = <&pinctrl_hog>; 317 318 pinctrl_hog: hoggrp { 319 fsl,pins = < 320 /* GPIO Expanders shared IRQ */ 321 MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e 322 >; 323 }; 324 325 pinctrl_captouch: captouchgrp { 326 fsl,pins = < 327 MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e 328 >; 329 }; 330 331 pinctrl_extcon: extcongrp { 332 fsl,pins = < 333 MX91_PAD_CCM_CLKO4__GPIO4_IO29 0x31e 334 >; 335 }; 336 337 pinctrl_fec: fecgrp { 338 fsl,pins = < 339 MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e 340 MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e 341 MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e 342 MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x37e 343 MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe 344 MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e 345 MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e 346 MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e 347 MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e 348 MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e 349 MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe 350 MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e 351 >; 352 }; 353 354 pinctrl_fec_sleep: fecsleepgrp { 355 fsl,pins = < 356 MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e 357 MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e 358 MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e 359 MX91_PAD_ENET2_RD3__GPIO4_IO27 0x31e 360 MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e 361 MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e 362 MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e 363 MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e 364 MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e 365 MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e 366 MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e 367 MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e 368 >; 369 }; 370 371 pinctrl_flexcan1: flexcan1grp { 372 fsl,pins = < 373 MX91_PAD_PDM_CLK__CAN1_TX 0x139e 374 MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e 375 >; 376 }; 377 378 pinctrl_lpi2c1: lpi2c1grp { 379 fsl,pins = < 380 MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e 381 MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e 382 >; 383 }; 384 385 pinctrl_lpi2c1_gpio: lpi2c1-gpiogrp { 386 fsl,pins = < 387 MX91_PAD_I2C1_SCL__GPIO1_IO0 0x31e 388 MX91_PAD_I2C1_SDA__GPIO1_IO1 0x31e 389 >; 390 }; 391 392 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 393 fsl,pins = < 394 MX91_PAD_CCM_CLKO3__GPIO4_IO28 0x31e 395 >; 396 }; 397 398 pinctrl_uart1: uart1grp { 399 fsl,pins = < 400 MX91_PAD_UART1_RXD__LPUART1_RX 0x31e 401 MX91_PAD_UART1_TXD__LPUART1_TX 0x31e 402 >; 403 }; 404 405 pinctrl_uart6: uart6grp { 406 fsl,pins = < 407 MX91_PAD_GPIO_IO05__LPUART6_RX 0x31e 408 MX91_PAD_GPIO_IO04__LPUART6_TX 0x31e 409 >; 410 }; 411 412 pinctrl_usdhc2: usdhc2grp { 413 fsl,pins = < 414 MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582 415 MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382 416 MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382 417 MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382 418 MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382 419 MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382 420 MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 421 >; 422 }; 423 424 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 425 fsl,pins = < 426 MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e 427 MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e 428 MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 429 MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 430 MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 431 MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 432 MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 433 >; 434 }; 435 436 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 437 fsl,pins = < 438 MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe 439 MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe 440 MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe 441 MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe 442 MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe 443 MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe 444 MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 445 >; 446 }; 447 448 pinctrl_usdhc2_sleep: usdhc2sleepgrp { 449 fsl,pins = < 450 MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e 451 MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e 452 MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e 453 MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e 454 MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e 455 MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e 456 MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e 457 >; 458 }; 459 460 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 461 fsl,pins = < 462 MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e 463 >; 464 }; 465 466 pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { 467 fsl,pins = < 468 MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e 469 >; 470 }; 471}; 472