1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2/* 3 * Copyright (c) 2022-2026 TQ-Systems GmbH <linux@ew.tq-group.com>, 4 * D-82229 Seefeld, Germany. 5 * Author: Markus Niebel 6 * Author: Alexander Stein 7 */ 8/dts-v1/; 9 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/leds/common.h> 12#include <dt-bindings/net/ti-dp83867.h> 13#include <dt-bindings/pwm/pwm.h> 14 15#include "imx91-tqma9131.dtsi" 16 17/{ 18 model = "TQ-Systems i.MX91 TQMa91xxLA/TQMa91xxCA on MBa93xxCA starter kit"; 19 compatible = "tq,imx91-tqma9131-mba93xxca", 20 "tq,imx91-tqma9131", "fsl,imx91"; 21 chassis-type = "embedded"; 22 23 chosen { 24 stdout-path = &lpuart1; 25 }; 26 27 aliases { 28 eeprom0 = &eeprom0; 29 ethernet0 = &eqos; 30 ethernet1 = &fec; 31 gpio0 = &gpio1; 32 gpio1 = &gpio2; 33 gpio2 = &gpio3; 34 gpio3 = &gpio4; 35 i2c0 = &lpi2c1; 36 i2c1 = &lpi2c2; 37 i2c2 = &lpi2c3; 38 mmc0 = &usdhc1; 39 mmc1 = &usdhc2; 40 rtc0 = &pcf85063; 41 rtc1 = &bbnsm_rtc; 42 serial0 = &lpuart1; 43 serial1 = &lpuart2; 44 serial2 = &lpuart3; 45 serial5 = &lpuart6; 46 serial7 = &lpuart8; 47 }; 48 49 clk_dp: clk-dp { 50 compatible = "fixed-clock"; 51 #clock-cells = <0>; 52 clock-frequency = <26000000>; 53 status = "disabled"; 54 }; 55 56 fan0: pwm-fan { 57 compatible = "pwm-fan"; 58 pinctrl-names = "default"; 59 pinctrl-0 = <&pinctrl_pwmfan>; 60 fan-supply = <®_pwm_fan>; 61 #cooling-cells = <2>; 62 /* typical 25 kHz -> 40.000 nsec */ 63 pwms = <&tpm6 0 40000 PWM_POLARITY_INVERTED>; 64 cooling-levels = <0 32 64 128 196 240>; 65 pulses-per-revolution = <2>; 66 interrupt-parent = <&gpio2>; 67 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 68 status = "disabled"; 69 }; 70 71 gpio-keys { 72 compatible = "gpio-keys"; 73 autorepeat; 74 75 switch-a { 76 label = "switcha"; 77 linux,code = <BTN_0>; 78 gpios = <&expander0 6 GPIO_ACTIVE_LOW>; 79 wakeup-source; 80 }; 81 82 switch-b { 83 label = "switchb"; 84 linux,code = <BTN_1>; 85 gpios = <&expander0 7 GPIO_ACTIVE_LOW>; 86 wakeup-source; 87 }; 88 }; 89 90 gpio-leds { 91 compatible = "gpio-leds"; 92 93 led-1 { 94 color = <LED_COLOR_ID_GREEN>; 95 function = LED_FUNCTION_STATUS; 96 gpios = <&expander2 6 GPIO_ACTIVE_HIGH>; 97 linux,default-trigger = "default-on"; 98 }; 99 100 led-2 { 101 color = <LED_COLOR_ID_AMBER>; 102 function = LED_FUNCTION_HEARTBEAT; 103 gpios = <&expander2 7 GPIO_ACTIVE_HIGH>; 104 linux,default-trigger = "heartbeat"; 105 }; 106 }; 107 108 iio-hwmon { 109 compatible = "iio-hwmon"; 110 io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>; 111 }; 112 113 reg_3v3: regulator-3v3 { 114 compatible = "regulator-fixed"; 115 regulator-name = "V_3V3_MB"; 116 regulator-min-microvolt = <3300000>; 117 regulator-max-microvolt = <3300000>; 118 }; 119 120 reg_5v0: regulator-5v0 { 121 compatible = "regulator-fixed"; 122 regulator-name = "V_5V0_MB"; 123 regulator-min-microvolt = <5000000>; 124 regulator-max-microvolt = <5000000>; 125 }; 126 127 reg_12v0: regulator-12v0 { 128 compatible = "regulator-fixed"; 129 regulator-name = "V_12V"; 130 regulator-min-microvolt = <12000000>; 131 regulator-max-microvolt = <12000000>; 132 gpio = <&expander1 7 GPIO_ACTIVE_HIGH>; 133 enable-active-high; 134 }; 135 136 reg_mpcie_1v5: regulator-mpcie-1v5 { 137 compatible = "regulator-fixed"; 138 regulator-name = "V_1V5_MPCIE"; 139 regulator-min-microvolt = <1500000>; 140 regulator-max-microvolt = <1500000>; 141 gpio = <&expander0 2 GPIO_ACTIVE_HIGH>; 142 enable-active-high; 143 regulator-always-on; 144 }; 145 146 reg_mpcie_3v3: regulator-mpcie-3v3 { 147 compatible = "regulator-fixed"; 148 regulator-name = "V_3V3_MPCIE"; 149 regulator-min-microvolt = <3300000>; 150 regulator-max-microvolt = <3300000>; 151 gpio = <&expander0 3 GPIO_ACTIVE_HIGH>; 152 enable-active-high; 153 regulator-always-on; 154 }; 155 156 reg_pwm_fan: regulator-pwm-fan { 157 compatible = "regulator-fixed"; 158 regulator-name = "FAN_PWR"; 159 regulator-min-microvolt = <12000000>; 160 regulator-max-microvolt = <12000000>; 161 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; 162 enable-active-high; 163 vin-supply = <®_12v0>; 164 }; 165 166 thermal-zones { 167 cpu-thermal { 168 trips { 169 cpu_active0: trip-active0 { 170 temperature = <40000>; 171 hysteresis = <5000>; 172 type = "active"; 173 }; 174 175 cpu_active1: trip-active1 { 176 temperature = <48000>; 177 hysteresis = <3000>; 178 type = "active"; 179 }; 180 181 cpu_active2: trip-active2 { 182 temperature = <60000>; 183 hysteresis = <10000>; 184 type = "active"; 185 }; 186 }; 187 188 cooling-maps { 189 map1 { 190 trip = <&cpu_active0>; 191 cooling-device = <&fan0 1 1>; 192 }; 193 194 map2 { 195 trip = <&cpu_active1>; 196 cooling-device = <&fan0 2 2>; 197 }; 198 199 map3 { 200 trip = <&cpu_active2>; 201 cooling-device = <&fan0 3 3>; 202 }; 203 }; 204 }; 205 }; 206}; 207 208&adc1 { 209 status = "okay"; 210}; 211 212&eqos { 213 pinctrl-names = "default"; 214 pinctrl-0 = <&pinctrl_eqos>; 215 phy-mode = "rgmii-id"; 216 phy-handle = <ðphy_eqos>; 217 status = "okay"; 218 219 mdio { 220 compatible = "snps,dwmac-mdio"; 221 #address-cells = <1>; 222 #size-cells = <0>; 223 224 ethphy_eqos: ethernet-phy@0 { 225 compatible = "ethernet-phy-ieee802.3-c22"; 226 reg = <0>; 227 pinctrl-names = "default"; 228 pinctrl-0 = <&pinctrl_eqos_phy>; 229 reset-gpios = <&expander1 0 GPIO_ACTIVE_LOW>; 230 reset-assert-us = <500000>; 231 reset-deassert-us = <50000>; 232 interrupt-parent = <&gpio3>; 233 interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 234 enet-phy-lane-no-swap; 235 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 236 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 237 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 238 ti,dp83867-rxctrl-strap-quirk; 239 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 240 }; 241 }; 242}; 243 244&fec { 245 pinctrl-names = "default"; 246 pinctrl-0 = <&pinctrl_fec>; 247 phy-mode = "rgmii-id"; 248 phy-handle = <ðphy_fec>; 249 fsl,magic-packet; 250 status = "okay"; 251 252 mdio { 253 #address-cells = <1>; 254 #size-cells = <0>; 255 clock-frequency = <5000000>; 256 257 ethphy_fec: ethernet-phy@0 { 258 compatible = "ethernet-phy-ieee802.3-c22"; 259 reg = <0>; 260 pinctrl-names = "default"; 261 pinctrl-0 = <&pinctrl_fec_phy>; 262 reset-gpios = <&expander1 1 GPIO_ACTIVE_LOW>; 263 reset-assert-us = <500000>; 264 reset-deassert-us = <50000>; 265 interrupt-parent = <&gpio3>; 266 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 267 enet-phy-lane-no-swap; 268 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 269 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 270 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 271 ti,dp83867-rxctrl-strap-quirk; 272 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 273 }; 274 }; 275}; 276 277&flexcan1 { 278 pinctrl-names = "default"; 279 pinctrl-0 = <&pinctrl_flexcan1>; 280 xceiver-supply = <®_3v3>; 281 status = "okay"; 282}; 283 284&flexcan2 { 285 pinctrl-names = "default"; 286 pinctrl-0 = <&pinctrl_flexcan2>; 287 xceiver-supply = <®_3v3>; 288 status = "okay"; 289}; 290 291&gpio1 { 292 gpio-line-names = 293 /* 00 */ "", "", "USB_C_ALERT#", "PMIC_IRQ#", 294 /* 04 */ "", "", "", "", 295 /* 08 */ "", "", "", "BM2_TEMP_EVENT_MOD#", 296 /* 12 */ "PEX_INT#", "", "RTC_EVENT#", "", 297 /* 16 */ "", "", "", "", 298 /* 20 */ "", "", "", "", 299 /* 24 */ "", "", "", "", 300 /* 28 */ "", "", "", ""; 301}; 302 303&gpio2 { 304 pinctrl-names = "default"; 305 pinctrl-0 = <&pinctrl_gpio2>; 306 307 gpio-line-names = 308 /* 00 */ "SPI6_PCS0#", "", "", "", 309 /* 04 */ "", "", "", "SPI_CS#", 310 /* 08 */ "", "FAN_RPM", "MIPI_CSI_TRIGGER", "MIPI_CSI_SYNC", 311 /* 12 */ "", "", "", "", 312 /* 16 */ "X1_11", "X1_21", "X1_17", "X1_13", 313 /* 20 */ "X1_15", "X1_9", "", "", 314 /* 24 */ "", "", "X1_7", "", 315 /* 28 */ "", "", "", ""; 316}; 317 318&gpio3 { 319 gpio-line-names = 320 /* 00 */ "SD2_CD#", "", "", "", 321 /* 04 */ "", "", "", "SD2_RST#", 322 /* 08 */ "", "", "", "", 323 /* 12 */ "", "", "", "", 324 /* 16 */ "", "", "", "", 325 /* 20 */ "", "", "", "", 326 /* 24 */ "", "", "ENET1_INT#", "ENET2_INT#", 327 /* 28 */ "", "", "", ""; 328}; 329 330&gpio4 { 331 gpio-line-names = 332 /* 00 */ "", "", "", "", 333 /* 04 */ "", "", "", "", 334 /* 08 */ "", "", "", "", 335 /* 12 */ "", "", "", "", 336 /* 16 */ "", "", "", "", 337 /* 20 */ "", "", "", "", 338 /* 24 */ "", "", "", "", 339 /* 28 */ "", "DP_INT", "", ""; 340}; 341 342&lpi2c3 { 343 #address-cells = <1>; 344 #size-cells = <0>; 345 clock-frequency = <400000>; 346 pinctrl-names = "default", "sleep"; 347 pinctrl-0 = <&pinctrl_lpi2c3>; 348 pinctrl-1 = <&pinctrl_lpi2c3>; 349 status = "okay"; 350 351 temperature-sensor@1c { 352 compatible = "nxp,se97b", "jedec,jc-42.4-temp"; 353 reg = <0x1c>; 354 }; 355 356 ptn5110: usb-typec@50 { 357 compatible = "nxp,ptn5110", "tcpci"; 358 reg = <0x50>; 359 pinctrl-names = "default"; 360 pinctrl-0 = <&pinctrl_typec>; 361 interrupt-parent = <&gpio1>; 362 interrupts = <2 IRQ_TYPE_EDGE_FALLING>; 363 364 connector { 365 compatible = "usb-c-connector"; 366 label = "X17"; 367 power-role = "dual"; 368 data-role = "dual"; 369 try-power-role = "sink"; 370 typec-power-opmode = "default"; 371 pd-disable; 372 self-powered; 373 374 port { 375 typec_con_hs: endpoint { 376 remote-endpoint = <&typec_hs>; 377 }; 378 }; 379 }; 380 }; 381 382 eeprom2: eeprom@54 { 383 compatible = "nxp,se97b", "atmel,24c02"; 384 reg = <0x54>; 385 pagesize = <16>; 386 vcc-supply = <®_3v3>; 387 }; 388 389 expander0: gpio@70 { 390 compatible = "nxp,pca9538"; 391 reg = <0x70>; 392 pinctrl-names = "default"; 393 pinctrl-0 = <&pinctrl_pexp_irq>; 394 gpio-controller; 395 #gpio-cells = <2>; 396 interrupt-controller; 397 #interrupt-cells = <2>; 398 interrupt-parent = <&gpio1>; 399 interrupts = <12 IRQ_TYPE_LEVEL_LOW>; 400 vcc-supply = <®_3v3>; 401 gpio-line-names = "FAN_PWR_EN", "MPCIE_WAKE#", 402 "MPCIE_1V5_EN", "MPCIE_3V3_EN", 403 "MPCIE_PERST#", "MPCIE_WDISABLE#", 404 "BUTTON_A#", "BUTTON_B#"; 405 406 mpcie-wake-hog { 407 gpio-hog; 408 gpios = <1 GPIO_ACTIVE_LOW>; 409 input; 410 line-name = "MPCIE_WAKE#"; 411 }; 412 413 /* 414 * Controls the mPCIE slot reset which is low active as 415 * reset signal. The output-low states, the signal is 416 * inactive, e.g. not in reset 417 */ 418 mpcie_rst_hog: mpcie-rst-hog { 419 gpio-hog; 420 gpios = <4 GPIO_ACTIVE_LOW>; 421 output-low; 422 line-name = "MPCIE_PERST#"; 423 }; 424 425 /* 426 * Controls the mPCIE slot WDISABLE pin which is low active 427 * as disable signal. The output-low states, the signal is 428 * inactive, e.g. not disabled 429 */ 430 mpcie_wdisable_hog: mpcie-wdisable-hog { 431 gpio-hog; 432 gpios = <5 GPIO_ACTIVE_LOW>; 433 output-low; 434 line-name = "MPCIE_WDISABLE#"; 435 }; 436 }; 437 438 expander1: gpio@71 { 439 compatible = "nxp,pca9538"; 440 reg = <0x71>; 441 gpio-controller; 442 #gpio-cells = <2>; 443 vcc-supply = <®_3v3>; 444 gpio-line-names = "ENET1_RESET#", "ENET2_RESET#", 445 "USB_RESET#", "", 446 "WLAN_PD#", "WLAN_W_DISABLE#", 447 "WLAN_PERST#", "12V_EN"; 448 449 /* 450 * Controls the WiFi card's low-active power down pin. 451 * The output-low states, the signal is inactive, 452 * resulting in high signal at power-down pin 453 */ 454 wlan-pd-hog { 455 gpio-hog; 456 gpios = <4 GPIO_ACTIVE_LOW>; 457 output-low; 458 line-name = "WLAN_PD#"; 459 }; 460 461 /* 462 * Controls the WiFi card's low-active disable pin. 463 * The output-low states, the signal is inactive, 464 * resulting in high signal at power-down pin 465 */ 466 wlan-wdisable-hog { 467 gpio-hog; 468 gpios = <5 GPIO_ACTIVE_LOW>; 469 output-low; 470 line-name = "WLAN_W_DISABLE#"; 471 }; 472 473 /* 474 * Controls the WiFi card's reset pin. 475 * The output-low states, the signal is inactive, 476 * resulting in high signal at power-down pin 477 */ 478 wlan-perst-hog { 479 gpio-hog; 480 gpios = <6 GPIO_ACTIVE_LOW>; 481 output-low; 482 line-name = "WLAN_PERST#"; 483 }; 484 }; 485 486 expander2: gpio@72 { 487 compatible = "nxp,pca9538"; 488 reg = <0x72>; 489 gpio-controller; 490 #gpio-cells = <2>; 491 vcc-supply = <®_3v3>; 492 gpio-line-names = "LCD_RESET#", "LCD_PWR_EN", 493 "LCD_BLT_EN", "DP_EN", 494 "MIPI_CSI_EN", "MIPI_CSI_RST#", 495 "USER_LED1", "USER_LED2"; 496 }; 497}; 498 499&lpi2c5 { 500 #address-cells = <1>; 501 #size-cells = <0>; 502 clock-frequency = <400000>; 503 pinctrl-names = "default", "sleep"; 504 pinctrl-0 = <&pinctrl_lpi2c5>; 505 pinctrl-1 = <&pinctrl_lpi2c5>; 506 status = "okay"; 507 508 dp_bridge: dp-bridge@f { 509 compatible = "toshiba,tc9595", "toshiba,tc358767"; 510 reg = <0x0f>; 511 pinctrl-names = "default"; 512 pinctrl-0 = <&pinctrl_tc9595>; 513 clock-names = "ref"; 514 clocks = <&clk_dp>; 515 reset-gpios = <&expander2 3 GPIO_ACTIVE_HIGH>; 516 interrupt-parent = <&gpio4>; 517 interrupts = <29 IRQ_TYPE_EDGE_RISING>; 518 toshiba,hpd-pin = <0>; 519 status = "disabled"; 520 521 ports { 522 #address-cells = <1>; 523 #size-cells = <0>; 524 525 port@0 { 526 reg = <0>; 527 528 dp_dsi_in: endpoint { 529 data-lanes = <1 2 3 4>; 530 }; 531 }; 532 }; 533 }; 534}; 535 536&lpspi6 { 537 pinctrl-names = "default"; 538 pinctrl-0 = <&pinctrl_lpspi6>, <&pinctrl_lpspi6_cs>; 539 cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>, <&gpio2 7 GPIO_ACTIVE_LOW>; 540 status = "okay"; 541}; 542 543&lpuart1 { 544 pinctrl-names = "default"; 545 pinctrl-0 = <&pinctrl_uart1>; 546 status = "okay"; 547}; 548 549&lpuart2 { 550 pinctrl-names = "default"; 551 pinctrl-0 = <&pinctrl_uart2>; 552 linux,rs485-enabled-at-boot-time; 553 status = "okay"; 554}; 555 556&lpuart3 { 557 pinctrl-names = "default"; 558 pinctrl-0 = <&pinctrl_uart3>; 559 status = "okay"; 560}; 561 562&lpuart6 { 563 pinctrl-names = "default"; 564 pinctrl-0 = <&pinctrl_uart6>; 565 status = "okay"; 566}; 567 568&lpuart8 { 569 pinctrl-names = "default"; 570 pinctrl-0 = <&pinctrl_uart8>; 571 status = "okay"; 572}; 573 574&pcf85063 { 575 /* RTC_EVENT# from SoM is connected on mainboard */ 576 pinctrl-names = "default"; 577 pinctrl-0 = <&pinctrl_pcf85063>; 578 interrupt-parent = <&gpio1>; 579 interrupts = <14 IRQ_TYPE_EDGE_FALLING>; 580}; 581 582&se97_som { 583 /* TEMP_EVENT# from SoM is connected on mainboard */ 584 pinctrl-names = "default"; 585 pinctrl-0 = <&pinctrl_temp_sensor_som>; 586 interrupt-parent = <&gpio1>; 587 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 588}; 589 590/* on LVDS connector, not usable */ 591&tpm5 { 592 pinctrl-names = "default"; 593 pinctrl-0 = <&pinctrl_tpm5>; 594}; 595 596&tpm6 { 597 pinctrl-names = "default"; 598 pinctrl-0 = <&pinctrl_tpm6>; 599 status = "okay"; 600}; 601 602&usbotg1 { 603 dr_mode = "otg"; 604 hnp-disable; 605 srp-disable; 606 adp-disable; 607 usb-role-switch; 608 disable-over-current; 609 samsung,picophy-pre-emp-curr-control = <3>; 610 samsung,picophy-dc-vol-level-adjust = <7>; 611 status = "okay"; 612 613 port { 614 typec_hs: endpoint { 615 remote-endpoint = <&typec_con_hs>; 616 }; 617 }; 618}; 619 620&usbotg2 { 621 dr_mode = "host"; 622 #address-cells = <1>; 623 #size-cells = <0>; 624 disable-over-current; 625 samsung,picophy-pre-emp-curr-control = <3>; 626 samsung,picophy-dc-vol-level-adjust = <7>; 627 status = "okay"; 628 629 hub_2_0: hub@1 { 630 compatible = "usb424,2517"; 631 reg = <1>; 632 reset-gpios = <&expander1 2 GPIO_ACTIVE_LOW>; 633 vdd-supply = <®_3v3>; 634 }; 635}; 636 637&usdhc2 { 638 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 639 pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>; 640 pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; 641 pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; 642 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 643 vmmc-supply = <®_usdhc2_vmmc>; 644 bus-width = <4>; 645 no-sdio; 646 no-mmc; 647 disable-wp; 648 status = "okay"; 649}; 650 651&iomuxc { 652 pinctrl_eqos: eqosgrp { 653 fsl,pins = < 654 /* PD | FSEL_2 | DSE X4 */ 655 MX91_PAD_ENET1_MDC__ENET1_MDC 0x51e 656 /* SION | HYS | FSEL_2 | DSE X4 */ 657 MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000111e 658 /* HYS | FSEL_0 | DSE no drive */ 659 MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x1000 660 MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x1000 661 MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x1000 662 MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x1000 663 MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x1000 664 /* HYS | PD | FSEL_0 | DSE no drive */ 665 MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x1400 666 /* PD | FSEL_2 | DSE X4 */ 667 MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e 668 MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x51e 669 MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x51e 670 MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x51e 671 MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x51e 672 /* PD | FSEL_3 | DSE X3 */ 673 MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e 674 >; 675 }; 676 677 pinctrl_eqos_phy: eqosphygrp { 678 fsl,pins = < 679 /* HYS | FSEL_0 | DSE no drive */ 680 MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x1000 681 >; 682 }; 683 684 pinctrl_fec: fecgrp { 685 fsl,pins = < 686 /* PD | FSEL_2 | DSE X4 */ 687 MX91_PAD_ENET2_MDC__ENET2_MDC 0x51e 688 /* SION | HYS | FSEL_2 | DSE X4 */ 689 MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x4000111e 690 /* HYS | FSEL_0 | DSE no drive */ 691 MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x1000 692 MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x1000 693 MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x1000 694 MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x1000 695 MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x1000 696 /* HYS | PD | FSEL_0 | DSE no drive */ 697 MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x1400 698 /* PD | FSEL_2 | DSE X4 */ 699 MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x51e 700 MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x51e 701 MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x51e 702 MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x51e 703 MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x51e 704 /* PD | FSEL_3 | DSE X3 */ 705 MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x58e 706 >; 707 }; 708 709 pinctrl_fec_phy: fecphygrp { 710 fsl,pins = < 711 /* HYS | FSEL_0 | DSE no drive */ 712 MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x1000 713 >; 714 }; 715 716 pinctrl_flexcan1: flexcan1grp { 717 fsl,pins = < 718 /* HYS | PU | FSEL_0 | DSE no drive */ 719 MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x1200 720 /* PU | FSEL_3 | DSE X4 */ 721 MX91_PAD_PDM_CLK__CAN1_TX 0x039e 722 >; 723 }; 724 725 pinctrl_flexcan2: flexcan2grp { 726 fsl,pins = < 727 /* HYS | PU | FSEL_0 | DSE no drive */ 728 MX91_PAD_GPIO_IO27__CAN2_RX 0x1200 729 /* PU | FSEL_3 | DSE X4 */ 730 MX91_PAD_GPIO_IO25__CAN2_TX 0x039e 731 >; 732 }; 733 734 pinctrl_gpio2: gpio2grp { 735 fsl,pins = < 736 /* HYS | PD | FSEL_2 | DSE X4 */ 737 MX91_PAD_GPIO_IO16__GPIO2_IO16 0x151e 738 MX91_PAD_GPIO_IO17__GPIO2_IO17 0x151e 739 MX91_PAD_GPIO_IO18__GPIO2_IO18 0x151e 740 MX91_PAD_GPIO_IO19__GPIO2_IO19 0x151e 741 MX91_PAD_GPIO_IO20__GPIO2_IO20 0x151e 742 MX91_PAD_GPIO_IO21__GPIO2_IO21 0x151e 743 MX91_PAD_GPIO_IO26__GPIO2_IO26 0x151e 744 >; 745 }; 746 747 pinctrl_jtag: jtaggrp { 748 fsl,pins = < 749 MX91_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x051e 750 MX91_PAD_DAP_TDI__JTAG_MUX_TDI 0x1200 751 MX91_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x031e 752 MX91_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x1200 753 >; 754 }; 755 756 pinctrl_lpi2c3: lpi2c3grp { 757 fsl,pins = < 758 /* SION | HYS | OD | FSEL_3 | DSE X4 */ 759 MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x4000199e 760 MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x4000199e 761 >; 762 }; 763 764 pinctrl_lpi2c5: lpi2c5grp { 765 fsl,pins = < 766 /* SION | HYS | OD | FSEL_3 | DSE X4 */ 767 MX91_PAD_GPIO_IO22__LPI2C5_SDA 0x4000199e 768 MX91_PAD_GPIO_IO23__LPI2C5_SCL 0x4000199e 769 >; 770 }; 771 772 pinctrl_lpspi6: lpspi6grp { 773 fsl,pins = < 774 /* HYS | PD | FSEL_0 | DSE no drive */ 775 MX91_PAD_GPIO_IO01__LPSPI6_SIN 0x1400 776 /* PD | FSEL_2 | DSE X4 */ 777 MX91_PAD_GPIO_IO02__LPSPI6_SOUT 0x051e 778 MX91_PAD_GPIO_IO03__LPSPI6_SCK 0x051e 779 >; 780 }; 781 782 pinctrl_lpspi6_cs: lpspi6csgrp { 783 fsl,pins = < 784 /* FSEL_2 | DSE X4 */ 785 MX91_PAD_GPIO_IO00__GPIO2_IO0 0x011e 786 MX91_PAD_GPIO_IO07__GPIO2_IO7 0x011e 787 >; 788 }; 789 790 pinctrl_mipi_csi: mipicsigrp { 791 fsl,pins = < 792 MX91_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x051e /* MCLK */ 793 MX91_PAD_GPIO_IO10__GPIO2_IO10 0x051e /* TRIGGER */ 794 MX91_PAD_GPIO_IO11__GPIO2_IO11 0x1400 /* SYNC */ 795 >; 796 }; 797 798 pinctrl_pcf85063: pcf85063grp { 799 fsl,pins = < 800 MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x1000 801 >; 802 }; 803 804 pinctrl_pexp_irq: pexpirqgrp { 805 fsl,pins = < 806 /* HYS | FSEL_0 | No DSE */ 807 MX91_PAD_SAI1_TXC__GPIO1_IO12 0x1000 808 >; 809 }; 810 811 pinctrl_pwmfan: pwmfangrp { 812 fsl,pins = < 813 /* HYS | PU | FSEL_0 | no DSE */ 814 MX91_PAD_GPIO_IO09__GPIO2_IO9 0x1200 815 >; 816 }; 817 818 pinctrl_tc9595: tc9595-grp { 819 fsl,pins = < 820 /* HYS | PD | FSEL_0 | no DSE */ 821 MX91_PAD_CCM_CLKO4__GPIO4_IO29 0x1400 822 >; 823 }; 824 825 pinctrl_temp_sensor_som: tempsensorsomgrp { 826 fsl,pins = < 827 /* HYS | FSEL_0 | no DSE */ 828 MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x1000 829 >; 830 }; 831 832 pinctrl_tpm5: tpm5grp { 833 fsl,pins = < 834 MX91_PAD_GPIO_IO06__TPM5_CH0 0x57e 835 >; 836 }; 837 838 pinctrl_tpm6: tpm6grp { 839 fsl,pins = < 840 MX91_PAD_GPIO_IO08__TPM6_CH0 0x57e 841 >; 842 }; 843 844 pinctrl_typec: typecgrp { 845 fsl,pins = < 846 /* HYS | FSEL_0 | No DSE */ 847 MX91_PAD_I2C2_SCL__GPIO1_IO2 0x1000 848 >; 849 }; 850 851 pinctrl_uart1: uart1grp { 852 fsl,pins = < 853 /* HYS | FSEL_0 | No DSE */ 854 MX91_PAD_UART1_RXD__LPUART1_RX 0x1000 855 /* FSEL_2 | DSE X4 */ 856 MX91_PAD_UART1_TXD__LPUART1_TX 0x011e 857 >; 858 }; 859 860 pinctrl_uart2: uart2grp { 861 fsl,pins = < 862 /* HYS | FSEL_0 | No DSE */ 863 MX91_PAD_UART2_RXD__LPUART2_RX 0x1000 864 /* FSEL_2 | DSE X4 */ 865 MX91_PAD_UART2_TXD__LPUART2_TX 0x011e 866 /* FSEL_2 | DSE X4 */ 867 MX91_PAD_SAI1_TXD0__LPUART2_RTS_B 0x011e 868 >; 869 }; 870 871 pinctrl_uart3: uart3grp { 872 fsl,pins = < 873 /* HYS | FSEL_0 | No DSE */ 874 MX91_PAD_GPIO_IO15__LPUART3_RX 0x1000 875 /* FSEL_2 | DSE X4 */ 876 MX91_PAD_GPIO_IO14__LPUART3_TX 0x011e 877 >; 878 }; 879 880 pinctrl_uart6: uart6grp { 881 fsl,pins = < 882 /* HYS | FSEL_0 | No DSE */ 883 MX91_PAD_GPIO_IO05__LPUART6_RX 0x1000 884 /* FSEL_2 | DSE X4 */ 885 MX91_PAD_GPIO_IO04__LPUART6_TX 0x011e 886 >; 887 }; 888 889 pinctrl_uart8: uart8grp { 890 fsl,pins = < 891 /* HYS | FSEL_0 | No DSE */ 892 MX91_PAD_GPIO_IO13__LPUART8_RX 0x1000 893 /* FSEL_2 | DSE X4 */ 894 MX91_PAD_GPIO_IO12__LPUART8_TX 0x011e 895 >; 896 }; 897 898 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 899 fsl,pins = < 900 /* HYS | FSEL_0 | No DSE */ 901 MX91_PAD_SD2_CD_B__GPIO3_IO0 0x1000 902 >; 903 }; 904 905 /* enable SION for data and cmd pad due to ERR052021 */ 906 pinctrl_usdhc2_hs: usdhc2hsgrp { 907 fsl,pins = < 908 /* PD | FSEL_3 | DSE X5 */ 909 MX91_PAD_SD2_CLK__USDHC2_CLK 0x05be 910 /* HYS | PU | FSEL_3 | DSE X4 */ 911 MX91_PAD_SD2_CMD__USDHC2_CMD 0x4000139e 912 /* HYS | PU | FSEL_3 | DSE X3 */ 913 MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e 914 MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e 915 MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e 916 MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e 917 /* FSEL_2 | DSE X3 */ 918 MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e 919 >; 920 }; 921 922 /* enable SION for data and cmd pad due to ERR052021 */ 923 pinctrl_usdhc2_uhs: usdhc2uhsgrp { 924 fsl,pins = < 925 /* PD | FSEL_3 | DSE X6 */ 926 MX91_PAD_SD2_CLK__USDHC2_CLK 0x05fe 927 /* HYS | PU | FSEL_3 | DSE X4 */ 928 MX91_PAD_SD2_CMD__USDHC2_CMD 0x4000139e 929 MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e 930 MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e 931 MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e 932 MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e 933 /* FSEL_2 | DSE X3 */ 934 MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e 935 >; 936 }; 937}; 938