1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2025 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/usb/pd.h> 9#include "imx91.dtsi" 10 11/ { 12 compatible = "fsl,imx91-11x11-frdm", "fsl,imx91"; 13 model = "NXP i.MX91 11x11 FRDM Board"; 14 15 aliases { 16 ethernet0 = &fec; 17 ethernet1 = &eqos; 18 gpio0 = &gpio1; 19 gpio1 = &gpio2; 20 gpio2 = &gpio3; 21 gpio3 = &gpio4; 22 i2c0 = &lpi2c1; 23 i2c1 = &lpi2c2; 24 i2c2 = &lpi2c3; 25 mmc0 = &usdhc1; 26 mmc1 = &usdhc2; 27 mmc2 = &usdhc3; 28 rtc0 = &bbnsm_rtc; 29 rtc1 = &pcf2131; 30 serial0 = &lpuart1; 31 serial4 = &lpuart5; 32 }; 33 34 chosen { 35 stdout-path = &lpuart1; 36 }; 37 38 flexcan_phy: can-phy { 39 compatible = "nxp,tja1051"; 40 #phy-cells = <0>; 41 max-bitrate = <5000000>; 42 silent-gpios = <&pcal6524 23 GPIO_ACTIVE_HIGH>; 43 }; 44 45 gpio-keys { 46 compatible = "gpio-keys"; 47 48 button-k2 { 49 interrupt-parent = <&pcal6524>; 50 interrupts = <5 IRQ_TYPE_EDGE_FALLING>; 51 label = "Button K2"; 52 gpios = <&pcal6524 5 GPIO_PULL_UP>; 53 linux,code = <BTN_1>; 54 }; 55 56 button-k3 { 57 interrupt-parent = <&pcal6524>; 58 interrupts = <6 IRQ_TYPE_EDGE_FALLING>; 59 label = "Button K3"; 60 gpios = <&pcal6524 6 GPIO_PULL_UP>; 61 linux,code = <BTN_2>; 62 }; 63 }; 64 65 reg_vref_1v8: regulator-adc-vref { 66 compatible = "regulator-fixed"; 67 regulator-max-microvolt = <1800000>; 68 regulator-min-microvolt = <1800000>; 69 regulator-name = "vref_1v8"; 70 }; 71 72 reg_m2_pwr: regulator-m2-pwr { 73 compatible = "regulator-fixed"; 74 regulator-max-microvolt = <3300000>; 75 regulator-min-microvolt = <3300000>; 76 regulator-name = "M.2-power"; 77 gpio = <&pcal6524 13 GPIO_ACTIVE_HIGH>; 78 enable-active-high; 79 }; 80 81 reg_usdhc2_vmmc: regulator-usdhc2 { 82 compatible = "regulator-fixed"; 83 off-on-delay-us = <12000>; 84 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 85 pinctrl-names = "default"; 86 regulator-max-microvolt = <3300000>; 87 regulator-min-microvolt = <3300000>; 88 regulator-name = "VSD_3V3"; 89 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 90 enable-active-high; 91 bootph-pre-ram; 92 bootph-some-ram; 93 }; 94 95 reg_usdhc3_vmmc: regulator-usdhc3 { 96 compatible = "regulator-fixed"; 97 regulator-max-microvolt = <3300000>; 98 regulator-min-microvolt = <3300000>; 99 regulator-name = "WLAN_EN"; 100 vin-supply = <®_m2_pwr>; 101 gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>; 102 enable-active-high; 103 /* 104 * This regulator defined as PDn pin of the IW610 wifi module. 105 * IW610 wifi chip needs more delay than other wifi chips to complete 106 * the host interface initialization after power up, otherwise the 107 * internal state of IW610 may be unstable, resulting in the failure of 108 * the SDIO3.0 switch voltage. 109 */ 110 startup-delay-us = <20000>; 111 }; 112 113 reg_vdd_12v: regulator-vdd-12v { 114 compatible = "regulator-fixed"; 115 regulator-max-microvolt = <12000000>; 116 regulator-min-microvolt = <12000000>; 117 regulator-name = "reg_vdd_12v"; 118 gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>; 119 enable-active-high; 120 }; 121 122 reg_vexp_3v3: regulator-vexp-3v3 { 123 compatible = "regulator-fixed"; 124 regulator-max-microvolt = <3300000>; 125 regulator-min-microvolt = <3300000>; 126 regulator-name = "VEXP_3V3"; 127 vin-supply = <&buck4>; 128 gpio = <&pcal6524 2 GPIO_ACTIVE_HIGH>; 129 enable-active-high; 130 }; 131 132 reg_vexp_5v: regulator-vexp-5v { 133 compatible = "regulator-fixed"; 134 regulator-max-microvolt = <5000000>; 135 regulator-min-microvolt = <5000000>; 136 regulator-name = "VEXP_5V"; 137 gpio = <&pcal6524 8 GPIO_ACTIVE_HIGH>; 138 enable-active-high; 139 }; 140 141 reserved-memory { 142 ranges; 143 #address-cells = <2>; 144 #size-cells = <2>; 145 146 linux,cma { 147 compatible = "shared-dma-pool"; 148 alloc-ranges = <0 0x80000000 0 0x30000000>; 149 reusable; 150 size = <0 0x10000000>; 151 linux,cma-default; 152 }; 153 }; 154 155 soc@0 { 156 bootph-all; 157 bootph-pre-ram; 158 }; 159 160 sound-mqs { 161 compatible = "fsl,imx6sx-sdb-mqs", 162 "fsl,imx-audio-mqs"; 163 audio-codec = <&mqs1>; 164 audio-cpu = <&sai1>; 165 model = "mqs-audio"; 166 }; 167 168 usdhc3_pwrseq: usdhc3-pwrseq { 169 compatible = "mmc-pwrseq-simple"; 170 reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; 171 }; 172}; 173 174&adc1 { 175 vref-supply = <®_vref_1v8>; 176 status = "okay"; 177}; 178 179&aips1 { 180 bootph-pre-ram; 181 bootph-all; 182}; 183 184&aips2 { 185 bootph-pre-ram; 186 bootph-some-ram; 187}; 188 189&aips3 { 190 bootph-pre-ram; 191 bootph-some-ram; 192}; 193 194&clk { 195 bootph-all; 196 bootph-pre-ram; 197}; 198 199&clk_ext1 { 200 bootph-all; 201 bootph-pre-ram; 202}; 203 204&eqos { 205 phy-handle = <ðphy1>; 206 phy-mode = "rgmii-id"; 207 pinctrl-0 = <&pinctrl_eqos>; 208 pinctrl-1 = <&pinctrl_eqos_sleep>; 209 pinctrl-names = "default", "sleep"; 210 status = "okay"; 211 212 mdio { 213 compatible = "snps,dwmac-mdio"; 214 #address-cells = <1>; 215 #size-cells = <0>; 216 clock-frequency = <5000000>; 217 218 ethphy1: ethernet-phy@1 { 219 reg = <1>; 220 reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; 221 reset-assert-us = <15000>; 222 reset-deassert-us = <100000>; 223 }; 224 }; 225}; 226 227&fec { 228 phy-handle = <ðphy2>; 229 phy-mode = "rgmii-id"; 230 pinctrl-0 = <&pinctrl_fec>; 231 pinctrl-1 = <&pinctrl_fec_sleep>; 232 pinctrl-names = "default", "sleep"; 233 fsl,magic-packet; 234 status = "okay"; 235 236 mdio { 237 #address-cells = <1>; 238 #size-cells = <0>; 239 clock-frequency = <5000000>; 240 241 ethphy2: ethernet-phy@2 { 242 reg = <2>; 243 reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; 244 reset-assert-us = <15000>; 245 reset-deassert-us = <100000>; 246 }; 247 }; 248}; 249 250&flexcan2 { 251 pinctrl-0 = <&pinctrl_flexcan2>; 252 pinctrl-1 = <&pinctrl_flexcan2_sleep>; 253 pinctrl-names = "default", "sleep"; 254 phys = <&flexcan_phy>; 255 status = "okay"; 256}; 257 258&gpio1 { 259 bootph-pre-ram; 260 bootph-some-ram; 261}; 262 263&gpio2 { 264 bootph-pre-ram; 265 bootph-some-ram; 266}; 267 268&gpio3 { 269 bootph-pre-ram; 270 bootph-some-ram; 271}; 272 273&gpio4 { 274 bootph-pre-ram; 275 bootph-some-ram; 276}; 277 278&lpi2c1 { 279 clock-frequency = <400000>; 280 pinctrl-0 = <&pinctrl_lpi2c1>; 281 pinctrl-names = "default"; 282 bootph-pre-ram; 283 bootph-some-ram; 284 status = "okay"; 285 286 pcal6408: gpio@20 { 287 compatible = "nxp,pcal9554b"; 288 reg = <0x20>; 289 #gpio-cells = <2>; 290 gpio-controller; 291 vcc-supply = <®_usdhc3_vmmc>; 292 status = "okay"; 293 }; 294}; 295 296&lpi2c2 { 297 #address-cells = <1>; 298 #size-cells = <0>; 299 clock-frequency = <400000>; 300 pinctrl-0 = <&pinctrl_lpi2c2>; 301 pinctrl-names = "default"; 302 bootph-pre-ram; 303 bootph-some-ram; 304 status = "okay"; 305 306 pcal6524: gpio@22 { 307 compatible = "nxp,pcal6524"; 308 reg = <0x22>; 309 #interrupt-cells = <2>; 310 interrupt-controller; 311 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 312 #gpio-cells = <2>; 313 gpio-controller; 314 interrupt-parent = <&gpio3>; 315 pinctrl-0 = <&pinctrl_pcal6524>; 316 pinctrl-names = "default"; 317 }; 318 319 pmic@25 { 320 compatible = "nxp,pca9451a"; 321 reg = <0x25>; 322 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 323 interrupt-parent = <&pcal6524>; 324 bootph-pre-ram; 325 bootph-some-ram; 326 327 regulators { 328 bootph-pre-ram; 329 bootph-some-ram; 330 331 buck1: BUCK1 { 332 regulator-always-on; 333 regulator-boot-on; 334 regulator-max-microvolt = <2237500>; 335 regulator-min-microvolt = <650000>; 336 regulator-name = "BUCK1"; 337 regulator-ramp-delay = <3125>; 338 }; 339 340 buck2: BUCK2 { 341 regulator-always-on; 342 regulator-boot-on; 343 regulator-max-microvolt = <2187500>; 344 regulator-min-microvolt = <600000>; 345 regulator-name = "BUCK2"; 346 regulator-ramp-delay = <3125>; 347 }; 348 349 buck4: BUCK4 { 350 regulator-always-on; 351 regulator-boot-on; 352 regulator-max-microvolt = <3400000>; 353 regulator-min-microvolt = <600000>; 354 regulator-name = "BUCK4"; 355 }; 356 357 buck5: BUCK5 { 358 regulator-always-on; 359 regulator-boot-on; 360 regulator-max-microvolt = <3400000>; 361 regulator-min-microvolt = <600000>; 362 regulator-name = "BUCK5"; 363 }; 364 365 buck6: BUCK6 { 366 regulator-always-on; 367 regulator-boot-on; 368 regulator-max-microvolt = <3400000>; 369 regulator-min-microvolt = <600000>; 370 regulator-name = "BUCK6"; 371 }; 372 373 ldo1: LDO1 { 374 regulator-always-on; 375 regulator-boot-on; 376 regulator-max-microvolt = <3300000>; 377 regulator-min-microvolt = <1600000>; 378 regulator-name = "LDO1"; 379 }; 380 381 ldo4: LDO4 { 382 regulator-always-on; 383 regulator-boot-on; 384 regulator-max-microvolt = <3300000>; 385 regulator-min-microvolt = <800000>; 386 regulator-name = "LDO4"; 387 }; 388 389 ldo5: LDO5 { 390 regulator-always-on; 391 regulator-boot-on; 392 regulator-max-microvolt = <3300000>; 393 regulator-min-microvolt = <1800000>; 394 regulator-name = "LDO5"; 395 }; 396 }; 397 }; 398}; 399 400&lpi2c3 { 401 #address-cells = <1>; 402 #size-cells = <0>; 403 clock-frequency = <400000>; 404 pinctrl-0 = <&pinctrl_lpi2c3>; 405 pinctrl-names = "default"; 406 bootph-pre-ram; 407 bootph-some-ram; 408 status = "okay"; 409 410 ptn5110: tcpc@50 { 411 compatible = "nxp,ptn5110", "tcpci"; 412 reg = <0x50>; 413 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 414 interrupt-parent = <&gpio3>; 415 416 typec1_con: connector { 417 compatible = "usb-c-connector"; 418 data-role = "dual"; 419 label = "USB-C"; 420 op-sink-microwatt = <15000000>; 421 power-role = "dual"; 422 self-powered; 423 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 424 PDO_VAR(5000, 20000, 3000)>; 425 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 426 try-power-role = "sink"; 427 428 ports { 429 #address-cells = <1>; 430 #size-cells = <0>; 431 432 port@0 { 433 reg = <0>; 434 435 typec1_dr_sw: endpoint { 436 remote-endpoint = <&usb1_drd_sw>; 437 }; 438 }; 439 }; 440 }; 441 }; 442 443 pcf2131: rtc@53 { 444 compatible = "nxp,pcf2131"; 445 reg = <0x53>; 446 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 447 interrupt-parent = <&pcal6524>; 448 status = "okay"; 449 }; 450}; 451 452&lpuart1 { 453 pinctrl-0 = <&pinctrl_uart1>; 454 pinctrl-names = "default"; 455 bootph-pre-ram; 456 bootph-some-ram; 457 status = "okay"; 458}; 459 460&lpuart5 { 461 pinctrl-0 = <&pinctrl_uart5>; 462 pinctrl-names = "default"; 463 status = "okay"; 464 465 bluetooth { 466 compatible = "nxp,88w8987-bt"; 467 }; 468}; 469 470&mqs1 { 471 clocks = <&clk IMX93_CLK_MQS1_GATE>; 472 clock-names = "mclk"; 473 pinctrl-0 = <&pinctrl_mqs1>; 474 pinctrl-names = "default"; 475 status = "okay"; 476}; 477 478&osc_32k { 479 bootph-all; 480 bootph-pre-ram; 481}; 482 483&osc_24m { 484 bootph-all; 485 bootph-pre-ram; 486}; 487 488&sai1 { 489 clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, 490 <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, 491 <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUDIO_PLL>; 492 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k"; 493 assigned-clocks = <&clk IMX93_CLK_SAI1>; 494 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 495 assigned-clock-rates = <24576000>; 496 #sound-dai-cells = <0>; 497 fsl,sai-mclk-direction-output; 498 status = "okay"; 499}; 500 501&usbotg1 { 502 adp-disable; 503 disable-over-current; 504 dr_mode = "otg"; 505 hnp-disable; 506 srp-disable; 507 usb-role-switch; 508 samsung,picophy-dc-vol-level-adjust = <7>; 509 samsung,picophy-pre-emp-curr-control = <3>; 510 status = "okay"; 511 512 port { 513 usb1_drd_sw: endpoint { 514 remote-endpoint = <&typec1_dr_sw>; 515 }; 516 }; 517}; 518 519&usbotg2 { 520 disable-over-current; 521 dr_mode = "host"; 522 samsung,picophy-dc-vol-level-adjust = <7>; 523 samsung,picophy-pre-emp-curr-control = <3>; 524 status = "okay"; 525}; 526 527&usdhc1 { 528 bus-width = <8>; 529 non-removable; 530 pinctrl-0 = <&pinctrl_usdhc1>; 531 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 532 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 533 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 534 bootph-pre-ram; 535 bootph-some-ram; 536 status = "okay"; 537}; 538 539&usdhc2 { 540 bus-width = <4>; 541 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; 542 no-mmc; 543 no-sdio; 544 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 545 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 546 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 547 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; 548 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 549 vmmc-supply = <®_usdhc2_vmmc>; 550 bootph-pre-ram; 551 bootph-some-ram; 552 status = "okay"; 553}; 554 555&usdhc3 { 556 bus-width = <4>; 557 keep-power-in-suspend; 558 mmc-pwrseq = <&usdhc3_pwrseq>; 559 non-removable; 560 pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; 561 pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>; 562 pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>; 563 pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>; 564 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 565 vmmc-supply = <®_usdhc3_vmmc>; 566 wakeup-source; 567 status = "okay"; 568}; 569 570&wdog3 { 571 fsl,ext-reset-output; 572 status = "okay"; 573}; 574 575&iomuxc { 576 bootph-pre-ram; 577 bootph-some-ram; 578 579 pinctrl_eqos: eqosgrp { 580 fsl,pins = < 581 MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e 582 MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e 583 MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 584 MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 585 MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e 586 MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e 587 MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe 588 MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 589 MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e 590 MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e 591 MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e 592 MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e 593 MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe 594 MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e 595 >; 596 }; 597 598 pinctrl_eqos_sleep: eqossleepgrp { 599 fsl,pins = < 600 MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e 601 MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e 602 MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e 603 MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e 604 MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e 605 MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e 606 MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e 607 MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e 608 MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e 609 MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e 610 MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e 611 MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e 612 MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e 613 MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e 614 >; 615 }; 616 617 pinctrl_fec: fecgrp { 618 fsl,pins = < 619 MX91_PAD_ENET2_MDC__ENET2_MDC 0x57e 620 MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x57e 621 MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e 622 MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e 623 MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e 624 MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x57e 625 MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe 626 MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e 627 MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e 628 MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e 629 MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e 630 MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e 631 MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe 632 MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e 633 >; 634 }; 635 636 pinctrl_fec_sleep: fecsleepgrp { 637 fsl,pins = < 638 MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e 639 MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e 640 MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e 641 MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e 642 MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e 643 MX91_PAD_ENET2_RD3__GPIO4_IO27 0x51e 644 MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e 645 MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e 646 MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e 647 MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e 648 MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e 649 MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e 650 MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e 651 MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e 652 >; 653 }; 654 655 pinctrl_flexcan2: flexcan2grp { 656 fsl,pins = < 657 MX91_PAD_GPIO_IO25__CAN2_TX 0x139e 658 MX91_PAD_GPIO_IO27__CAN2_RX 0x139e 659 >; 660 }; 661 662 pinctrl_flexcan2_sleep: flexcan2sleepgrp { 663 fsl,pins = < 664 MX91_PAD_GPIO_IO25__GPIO2_IO25 0x31e 665 MX91_PAD_GPIO_IO27__GPIO2_IO27 0x31e 666 >; 667 }; 668 669 pinctrl_lpi2c1: lpi2c1grp { 670 fsl,pins = < 671 MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e 672 MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e 673 >; 674 bootph-pre-ram; 675 bootph-some-ram; 676 }; 677 678 pinctrl_lpi2c2: lpi2c2grp { 679 fsl,pins = < 680 MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e 681 MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e 682 >; 683 bootph-pre-ram; 684 bootph-some-ram; 685 }; 686 687 pinctrl_lpi2c3: lpi2c3grp { 688 fsl,pins = < 689 MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e 690 MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e 691 >; 692 bootph-pre-ram; 693 bootph-some-ram; 694 }; 695 696 pinctrl_lpspi3: lpspi3grp { 697 fsl,pins = < 698 MX91_PAD_GPIO_IO08__GPIO2_IO8 0x3fe 699 MX91_PAD_GPIO_IO09__LPSPI3_SIN 0x3fe 700 MX91_PAD_GPIO_IO10__LPSPI3_SOUT 0x3fe 701 MX91_PAD_GPIO_IO11__LPSPI3_SCK 0x3fe 702 >; 703 }; 704 705 pinctrl_mqs1: mqs1grp { 706 fsl,pins = < 707 MX91_PAD_PDM_CLK__MQS1_LEFT 0x31e 708 MX91_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x31e 709 >; 710 }; 711 712 pinctrl_pcal6524: pcal6524grp { 713 fsl,pins = < 714 MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e 715 >; 716 }; 717 718 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 719 fsl,pins = < 720 MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e 721 >; 722 bootph-pre-ram; 723 }; 724 725 pinctrl_uart1: uart1grp { 726 fsl,pins = < 727 MX91_PAD_UART1_RXD__LPUART1_RX 0x31e 728 MX91_PAD_UART1_TXD__LPUART1_TX 0x31e 729 >; 730 bootph-pre-ram; 731 bootph-some-ram; 732 }; 733 734 pinctrl_uart5: uart5grp { 735 fsl,pins = < 736 MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e 737 MX91_PAD_DAP_TDI__LPUART5_RX 0x31e 738 MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e 739 MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e 740 >; 741 }; 742 743 pinctrl_usdhc1: usdhc1grp { 744 fsl,pins = < 745 MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582 746 MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382 747 MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382 748 MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382 749 MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382 750 MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382 751 MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382 752 MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382 753 MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382 754 MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382 755 MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 756 >; 757 bootph-pre-ram; 758 bootph-some-ram; 759 }; 760 761 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 762 fsl,pins = < 763 MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e 764 MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e 765 MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 766 MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 767 MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 768 MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 769 MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 770 MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 771 MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 772 MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 773 MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 774 >; 775 }; 776 777 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 778 fsl,pins = < 779 MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe 780 MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe 781 MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe 782 MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe 783 MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe 784 MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe 785 MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe 786 MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe 787 MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe 788 MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe 789 MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 790 >; 791 }; 792 793 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 794 fsl,pins = < 795 MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e 796 >; 797 bootph-pre-ram; 798 bootph-some-ram; 799 }; 800 801 pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { 802 fsl,pins = < 803 MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e 804 >; 805 }; 806 807 pinctrl_usdhc2: usdhc2grp { 808 fsl,pins = < 809 MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582 810 MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382 811 MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382 812 MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382 813 MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382 814 MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382 815 MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 816 >; 817 bootph-pre-ram; 818 bootph-some-ram; 819 }; 820 821 pinctrl_usdhc2_sleep: usdhc2sleepgrp { 822 fsl,pins = < 823 MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e 824 MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e 825 MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e 826 MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e 827 MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e 828 MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e 829 MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e 830 >; 831 }; 832 833 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 834 fsl,pins = < 835 MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e 836 MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e 837 MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 838 MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 839 MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 840 MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 841 MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 842 >; 843 }; 844 845 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 846 fsl,pins = < 847 MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe 848 MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe 849 MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe 850 MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe 851 MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe 852 MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe 853 MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 854 >; 855 }; 856 857 pinctrl_usdhc3: usdhc3grp { 858 fsl,pins = < 859 MX91_PAD_SD3_CLK__USDHC3_CLK 0x1582 860 MX91_PAD_SD3_CMD__USDHC3_CMD 0x1382 861 MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x1382 862 MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x1382 863 MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x1382 864 MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x1382 865 >; 866 }; 867 868 pinctrl_usdhc3_sleep: usdhc3sleepgrp { 869 fsl,pins = < 870 MX91_PAD_SD3_CLK__GPIO3_IO20 0x31e 871 MX91_PAD_SD3_CMD__GPIO3_IO21 0x31e 872 MX91_PAD_SD3_DATA0__GPIO3_IO22 0x31e 873 MX91_PAD_SD3_DATA1__GPIO3_IO23 0x31e 874 MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e 875 MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e 876 >; 877 }; 878 879 pinctrl_usdhc3_wlan: usdhc3wlangrp { 880 fsl,pins = < 881 MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x31e 882 >; 883 }; 884 885 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 886 fsl,pins = < 887 MX91_PAD_SD3_CLK__USDHC3_CLK 0x158e 888 MX91_PAD_SD3_CMD__USDHC3_CMD 0x138e 889 MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x138e 890 MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x138e 891 MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x138e 892 MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x138e 893 >; 894 }; 895 896 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 897 fsl,pins = < 898 MX91_PAD_SD3_CLK__USDHC3_CLK 0x15fe 899 MX91_PAD_SD3_CMD__USDHC3_CMD 0x13fe 900 MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe 901 MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe 902 MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe 903 MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe 904 >; 905 }; 906}; 907