1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2025 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/usb/pd.h> 9#include "imx91.dtsi" 10 11/ { 12 compatible = "fsl,imx91-11x11-evk", "fsl,imx91"; 13 model = "NXP i.MX91 11X11 EVK board"; 14 15 aliases { 16 ethernet0 = &fec; 17 ethernet1 = &eqos; 18 gpio0 = &gpio1; 19 gpio1 = &gpio2; 20 gpio2 = &gpio3; 21 i2c0 = &lpi2c1; 22 i2c1 = &lpi2c2; 23 i2c2 = &lpi2c3; 24 mmc0 = &usdhc1; 25 mmc1 = &usdhc2; 26 rtc0 = &bbnsm_rtc; 27 serial0 = &lpuart1; 28 serial1 = &lpuart2; 29 serial2 = &lpuart3; 30 serial3 = &lpuart4; 31 serial4 = &lpuart5; 32 }; 33 34 chosen { 35 stdout-path = &lpuart1; 36 }; 37 38 reg_vref_1v8: regulator-adc-vref { 39 compatible = "regulator-fixed"; 40 regulator-max-microvolt = <1800000>; 41 regulator-min-microvolt = <1800000>; 42 regulator-name = "vref_1v8"; 43 }; 44 45 reg_audio_pwr: regulator-audio-pwr { 46 compatible = "regulator-fixed"; 47 regulator-always-on; 48 regulator-max-microvolt = <3300000>; 49 regulator-min-microvolt = <3300000>; 50 regulator-name = "audio-pwr"; 51 gpio = <&adp5585 1 GPIO_ACTIVE_HIGH>; 52 enable-active-high; 53 }; 54 55 reg_usdhc2_vmmc: regulator-usdhc2 { 56 compatible = "regulator-fixed"; 57 off-on-delay-us = <12000>; 58 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 59 pinctrl-names = "default"; 60 regulator-max-microvolt = <3300000>; 61 regulator-min-microvolt = <3300000>; 62 regulator-name = "VSD_3V3"; 63 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 64 enable-active-high; 65 }; 66 67 reserved-memory { 68 ranges; 69 #address-cells = <2>; 70 #size-cells = <2>; 71 72 linux,cma { 73 compatible = "shared-dma-pool"; 74 alloc-ranges = <0 0x80000000 0 0x40000000>; 75 reusable; 76 size = <0 0x10000000>; 77 linux,cma-default; 78 }; 79 }; 80}; 81 82&adc1 { 83 vref-supply = <®_vref_1v8>; 84 status = "okay"; 85}; 86 87&eqos { 88 phy-handle = <ðphy1>; 89 phy-mode = "rgmii-id"; 90 pinctrl-0 = <&pinctrl_eqos>; 91 pinctrl-1 = <&pinctrl_eqos_sleep>; 92 pinctrl-names = "default", "sleep"; 93 status = "okay"; 94 95 mdio { 96 compatible = "snps,dwmac-mdio"; 97 #address-cells = <1>; 98 #size-cells = <0>; 99 clock-frequency = <5000000>; 100 101 ethphy1: ethernet-phy@1 { 102 reg = <1>; 103 realtek,clkout-disable; 104 }; 105 }; 106}; 107 108&fec { 109 phy-handle = <ðphy2>; 110 phy-mode = "rgmii-id"; 111 pinctrl-0 = <&pinctrl_fec>; 112 pinctrl-1 = <&pinctrl_fec_sleep>; 113 pinctrl-names = "default", "sleep"; 114 fsl,magic-packet; 115 status = "okay"; 116 117 mdio { 118 #address-cells = <1>; 119 #size-cells = <0>; 120 clock-frequency = <5000000>; 121 122 ethphy2: ethernet-phy@2 { 123 reg = <2>; 124 realtek,clkout-disable; 125 }; 126 }; 127}; 128 129&lpi2c1 { 130 clock-frequency = <400000>; 131 pinctrl-0 = <&pinctrl_lpi2c1>; 132 pinctrl-names = "default"; 133 status = "okay"; 134 135 audio_codec: wm8962@1a { 136 compatible = "wlf,wm8962"; 137 reg = <0x1a>; 138 clocks = <&clk IMX93_CLK_SAI3_GATE>; 139 AVDD-supply = <®_audio_pwr>; 140 CPVDD-supply = <®_audio_pwr>; 141 DBVDD-supply = <®_audio_pwr>; 142 DCVDD-supply = <®_audio_pwr>; 143 MICVDD-supply = <®_audio_pwr>; 144 PLLVDD-supply = <®_audio_pwr>; 145 SPKVDD1-supply = <®_audio_pwr>; 146 SPKVDD2-supply = <®_audio_pwr>; 147 gpio-cfg = < 148 0x0000 /* 0:Default */ 149 0x0000 /* 1:Default */ 150 0x0000 /* 2:FN_DMICCLK */ 151 0x0000 /* 3:Default */ 152 0x0000 /* 4:FN_DMICCDAT */ 153 0x0000 /* 5:Default */ 154 >; 155 }; 156 157 inertial-meter@6a { 158 compatible = "st,lsm6dso"; 159 reg = <0x6a>; 160 }; 161}; 162 163&lpi2c2 { 164 #address-cells = <1>; 165 #size-cells = <0>; 166 clock-frequency = <400000>; 167 pinctrl-0 = <&pinctrl_lpi2c2>; 168 pinctrl-names = "default"; 169 status = "okay"; 170 171 pcal6524: gpio@22 { 172 compatible = "nxp,pcal6524"; 173 reg = <0x22>; 174 #interrupt-cells = <2>; 175 interrupt-controller; 176 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 177 #gpio-cells = <2>; 178 gpio-controller; 179 interrupt-parent = <&gpio3>; 180 pinctrl-0 = <&pinctrl_pcal6524>; 181 pinctrl-names = "default"; 182 }; 183 184 pmic@25 { 185 compatible = "nxp,pca9451a"; 186 reg = <0x25>; 187 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 188 interrupt-parent = <&pcal6524>; 189 190 regulators { 191 buck1: BUCK1 { 192 regulator-always-on; 193 regulator-boot-on; 194 regulator-max-microvolt = <2237500>; 195 regulator-min-microvolt = <650000>; 196 regulator-name = "BUCK1"; 197 regulator-ramp-delay = <3125>; 198 }; 199 200 buck2: BUCK2 { 201 regulator-always-on; 202 regulator-boot-on; 203 regulator-max-microvolt = <2187500>; 204 regulator-min-microvolt = <600000>; 205 regulator-name = "BUCK2"; 206 regulator-ramp-delay = <3125>; 207 }; 208 209 buck4: BUCK4 { 210 regulator-always-on; 211 regulator-boot-on; 212 regulator-max-microvolt = <3400000>; 213 regulator-min-microvolt = <600000>; 214 regulator-name = "BUCK4"; 215 }; 216 217 buck5: BUCK5 { 218 regulator-always-on; 219 regulator-boot-on; 220 regulator-max-microvolt = <3400000>; 221 regulator-min-microvolt = <600000>; 222 regulator-name = "BUCK5"; 223 }; 224 225 buck6: BUCK6 { 226 regulator-always-on; 227 regulator-boot-on; 228 regulator-max-microvolt = <3400000>; 229 regulator-min-microvolt = <600000>; 230 regulator-name = "BUCK6"; 231 }; 232 233 ldo1: LDO1 { 234 regulator-always-on; 235 regulator-boot-on; 236 regulator-max-microvolt = <3300000>; 237 regulator-min-microvolt = <1600000>; 238 regulator-name = "LDO1"; 239 }; 240 241 ldo4: LDO4 { 242 regulator-always-on; 243 regulator-boot-on; 244 regulator-max-microvolt = <3300000>; 245 regulator-min-microvolt = <800000>; 246 regulator-name = "LDO4"; 247 }; 248 249 ldo5: LDO5 { 250 regulator-always-on; 251 regulator-boot-on; 252 regulator-max-microvolt = <3300000>; 253 regulator-min-microvolt = <1800000>; 254 regulator-name = "LDO5"; 255 }; 256 }; 257 }; 258 259 adp5585: io-expander@34 { 260 compatible = "adi,adp5585-00", "adi,adp5585"; 261 reg = <0x34>; 262 #gpio-cells = <2>; 263 gpio-controller; 264 #pwm-cells = <3>; 265 gpio-reserved-ranges = <5 1>; 266 267 exp-sel-hog { 268 gpio-hog; 269 gpios = <4 GPIO_ACTIVE_HIGH>; 270 output-low; 271 }; 272 }; 273}; 274 275&lpi2c3 { 276 #address-cells = <1>; 277 #size-cells = <0>; 278 clock-frequency = <400000>; 279 pinctrl-0 = <&pinctrl_lpi2c3>; 280 pinctrl-names = "default"; 281 status = "okay"; 282 283 ptn5110: tcpc@50 { 284 compatible = "nxp,ptn5110", "tcpci"; 285 reg = <0x50>; 286 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 287 interrupt-parent = <&gpio3>; 288 289 typec1_con: connector { 290 compatible = "usb-c-connector"; 291 data-role = "dual"; 292 label = "USB-C"; 293 op-sink-microwatt = <15000000>; 294 power-role = "dual"; 295 self-powered; 296 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 297 PDO_VAR(5000, 20000, 3000)>; 298 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 299 try-power-role = "sink"; 300 301 ports { 302 #address-cells = <1>; 303 #size-cells = <0>; 304 305 port@0 { 306 reg = <0>; 307 308 typec1_dr_sw: endpoint { 309 remote-endpoint = <&usb1_drd_sw>; 310 }; 311 }; 312 }; 313 }; 314 }; 315 316 ptn5110_2: tcpc@51 { 317 compatible = "nxp,ptn5110", "tcpci"; 318 reg = <0x51>; 319 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 320 interrupt-parent = <&gpio3>; 321 status = "okay"; 322 323 typec2_con: connector { 324 compatible = "usb-c-connector"; 325 data-role = "dual"; 326 label = "USB-C"; 327 op-sink-microwatt = <15000000>; 328 power-role = "dual"; 329 self-powered; 330 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 331 PDO_VAR(5000, 20000, 3000)>; 332 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 333 try-power-role = "sink"; 334 335 ports { 336 #address-cells = <1>; 337 #size-cells = <0>; 338 339 port@0 { 340 reg = <0>; 341 342 typec2_dr_sw: endpoint { 343 remote-endpoint = <&usb2_drd_sw>; 344 }; 345 }; 346 }; 347 }; 348 }; 349 350 pcf2131: rtc@53 { 351 compatible = "nxp,pcf2131"; 352 reg = <0x53>; 353 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 354 interrupt-parent = <&pcal6524>; 355 status = "okay"; 356 }; 357}; 358 359&lpuart1 { 360 pinctrl-0 = <&pinctrl_uart1>; 361 pinctrl-names = "default"; 362 status = "okay"; 363}; 364 365&lpuart5 { 366 pinctrl-0 = <&pinctrl_uart5>; 367 pinctrl-names = "default"; 368 status = "okay"; 369 370 bluetooth { 371 compatible = "nxp,88w8987-bt"; 372 }; 373}; 374 375&usbotg1 { 376 adp-disable; 377 disable-over-current; 378 dr_mode = "otg"; 379 hnp-disable; 380 srp-disable; 381 usb-role-switch; 382 samsung,picophy-dc-vol-level-adjust = <7>; 383 samsung,picophy-pre-emp-curr-control = <3>; 384 status = "okay"; 385 386 port { 387 usb1_drd_sw: endpoint { 388 remote-endpoint = <&typec1_dr_sw>; 389 }; 390 }; 391}; 392 393&usbotg2 { 394 adp-disable; 395 disable-over-current; 396 dr_mode = "otg"; 397 hnp-disable; 398 srp-disable; 399 usb-role-switch; 400 samsung,picophy-dc-vol-level-adjust = <7>; 401 samsung,picophy-pre-emp-curr-control = <3>; 402 status = "okay"; 403 404 port { 405 usb2_drd_sw: endpoint { 406 remote-endpoint = <&typec2_dr_sw>; 407 }; 408 }; 409}; 410 411&usdhc1 { 412 bus-width = <8>; 413 non-removable; 414 pinctrl-0 = <&pinctrl_usdhc1>; 415 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 416 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 417 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 418 status = "okay"; 419}; 420 421&usdhc2 { 422 bus-width = <4>; 423 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; 424 no-mmc; 425 no-sdio; 426 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 427 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 428 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 429 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; 430 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 431 vmmc-supply = <®_usdhc2_vmmc>; 432 status = "okay"; 433}; 434 435&wdog3 { 436 fsl,ext-reset-output; 437 status = "okay"; 438}; 439 440&iomuxc { 441 pinctrl_eqos: eqosgrp { 442 fsl,pins = < 443 MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e 444 MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e 445 MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 446 MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 447 MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e 448 MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e 449 MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe 450 MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 451 MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e 452 MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e 453 MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e 454 MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e 455 MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe 456 MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e 457 >; 458 }; 459 460 pinctrl_eqos_sleep: eqossleepgrp { 461 fsl,pins = < 462 MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e 463 MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e 464 MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e 465 MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e 466 MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e 467 MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e 468 MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e 469 MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e 470 MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e 471 MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e 472 MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e 473 MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e 474 MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e 475 MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e 476 >; 477 }; 478 479 pinctrl_fec: fecgrp { 480 fsl,pins = < 481 MX91_PAD_ENET2_MDC__ENET2_MDC 0x57e 482 MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x57e 483 MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e 484 MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e 485 MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e 486 MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x57e 487 MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe 488 MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e 489 MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e 490 MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e 491 MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e 492 MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e 493 MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe 494 MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e 495 >; 496 }; 497 498 pinctrl_fec_sleep: fecsleepgrp { 499 fsl,pins = < 500 MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e 501 MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e 502 MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e 503 MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e 504 MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e 505 MX91_PAD_ENET2_RD3__GPIO4_IO27 0x51e 506 MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e 507 MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e 508 MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e 509 MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e 510 MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e 511 MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e 512 MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e 513 MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e 514 >; 515 }; 516 517 pinctrl_lpi2c1: lpi2c1grp { 518 fsl,pins = < 519 MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e 520 MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e 521 >; 522 }; 523 524 pinctrl_lpi2c2: lpi2c2grp { 525 fsl,pins = < 526 MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e 527 MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e 528 >; 529 }; 530 531 pinctrl_lpi2c3: lpi2c3grp { 532 fsl,pins = < 533 MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e 534 MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e 535 >; 536 }; 537 538 pinctrl_pcal6524: pcal6524grp { 539 fsl,pins = < 540 MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e 541 >; 542 }; 543 544 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 545 fsl,pins = < 546 MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e 547 >; 548 }; 549 550 pinctrl_uart1: uart1grp { 551 fsl,pins = < 552 MX91_PAD_UART1_RXD__LPUART1_RX 0x31e 553 MX91_PAD_UART1_TXD__LPUART1_TX 0x31e 554 >; 555 }; 556 557 pinctrl_uart5: uart5grp { 558 fsl,pins = < 559 MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e 560 MX91_PAD_DAP_TDI__LPUART5_RX 0x31e 561 MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e 562 MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e 563 >; 564 }; 565 566 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 567 fsl,pins = < 568 MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e 569 MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e 570 MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 571 MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 572 MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 573 MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 574 MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 575 MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 576 MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 577 MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 578 MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 579 >; 580 }; 581 582 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 583 fsl,pins = < 584 MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe 585 MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe 586 MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe 587 MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe 588 MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe 589 MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe 590 MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe 591 MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe 592 MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe 593 MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe 594 MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 595 >; 596 }; 597 598 pinctrl_usdhc1: usdhc1grp { 599 fsl,pins = < 600 MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582 601 MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382 602 MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382 603 MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382 604 MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382 605 MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382 606 MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382 607 MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382 608 MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382 609 MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382 610 MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 611 >; 612 }; 613 614 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 615 fsl,pins = < 616 MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e 617 MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e 618 MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 619 MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 620 MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 621 MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 622 MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 623 >; 624 }; 625 626 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 627 fsl,pins = < 628 MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe 629 MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe 630 MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe 631 MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe 632 MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe 633 MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe 634 MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 635 >; 636 }; 637 638 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 639 fsl,pins = < 640 MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e 641 >; 642 }; 643 644 pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { 645 fsl,pins = < 646 MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e 647 >; 648 }; 649 650 pinctrl_usdhc2: usdhc2grp { 651 fsl,pins = < 652 MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582 653 MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382 654 MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382 655 MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382 656 MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382 657 MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382 658 MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 659 >; 660 }; 661 662 pinctrl_usdhc2_sleep: usdhc2sleepgrp { 663 fsl,pins = < 664 MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e 665 MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e 666 MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e 667 MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e 668 MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e 669 MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e 670 MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e 671 >; 672 }; 673 674}; 675