1*5bf5090bSLaurentiu Mihalcea// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*5bf5090bSLaurentiu Mihalcea/* 3*5bf5090bSLaurentiu Mihalcea * Copyright 2025 NXP 4*5bf5090bSLaurentiu Mihalcea */ 5*5bf5090bSLaurentiu Mihalcea 6*5bf5090bSLaurentiu Mihalcea/dts-v1/; 7*5bf5090bSLaurentiu Mihalcea 8*5bf5090bSLaurentiu Mihalcea#include "imx8ulp-evk.dts" 9*5bf5090bSLaurentiu Mihalcea 10*5bf5090bSLaurentiu Mihalcea/ { 11*5bf5090bSLaurentiu Mihalcea model = "NXP i.MX8ULP EVK9"; 12*5bf5090bSLaurentiu Mihalcea compatible = "fsl,imx8ulp-9x9-evk", "fsl,imx8ulp"; 13*5bf5090bSLaurentiu Mihalcea}; 14*5bf5090bSLaurentiu Mihalcea 15*5bf5090bSLaurentiu Mihalcea&btcpu { 16*5bf5090bSLaurentiu Mihalcea sound-dai = <&sai6>; 17*5bf5090bSLaurentiu Mihalcea}; 18*5bf5090bSLaurentiu Mihalcea 19*5bf5090bSLaurentiu Mihalcea&iomuxc1 { 20*5bf5090bSLaurentiu Mihalcea pinctrl_sai6: sai6grp { 21*5bf5090bSLaurentiu Mihalcea fsl,pins = < 22*5bf5090bSLaurentiu Mihalcea MX8ULP_PAD_PTE10__I2S6_TX_BCLK 0x43 23*5bf5090bSLaurentiu Mihalcea MX8ULP_PAD_PTE11__I2S6_TX_FS 0x43 24*5bf5090bSLaurentiu Mihalcea MX8ULP_PAD_PTE14__I2S6_TXD2 0x43 25*5bf5090bSLaurentiu Mihalcea MX8ULP_PAD_PTE6__I2S6_RXD0 0x43 26*5bf5090bSLaurentiu Mihalcea >; 27*5bf5090bSLaurentiu Mihalcea }; 28*5bf5090bSLaurentiu Mihalcea}; 29*5bf5090bSLaurentiu Mihalcea 30*5bf5090bSLaurentiu Mihalcea&pinctrl_enet { 31*5bf5090bSLaurentiu Mihalcea fsl,pins = < 32*5bf5090bSLaurentiu Mihalcea MX8ULP_PAD_PTF9__ENET0_MDC 0x43 33*5bf5090bSLaurentiu Mihalcea MX8ULP_PAD_PTF8__ENET0_MDIO 0x43 34*5bf5090bSLaurentiu Mihalcea MX8ULP_PAD_PTF5__ENET0_RXER 0x43 35*5bf5090bSLaurentiu Mihalcea MX8ULP_PAD_PTF6__ENET0_CRS_DV 0x43 36*5bf5090bSLaurentiu Mihalcea MX8ULP_PAD_PTF1__ENET0_RXD0 0x43 37*5bf5090bSLaurentiu Mihalcea MX8ULP_PAD_PTF0__ENET0_RXD1 0x43 38*5bf5090bSLaurentiu Mihalcea MX8ULP_PAD_PTF4__ENET0_TXEN 0x43 39*5bf5090bSLaurentiu Mihalcea MX8ULP_PAD_PTF3__ENET0_TXD0 0x43 40*5bf5090bSLaurentiu Mihalcea MX8ULP_PAD_PTF2__ENET0_TXD1 0x43 41*5bf5090bSLaurentiu Mihalcea MX8ULP_PAD_PTF7__ENET0_REFCLK 0x43 42*5bf5090bSLaurentiu Mihalcea MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43 43*5bf5090bSLaurentiu Mihalcea >; 44*5bf5090bSLaurentiu Mihalcea}; 45*5bf5090bSLaurentiu Mihalcea 46*5bf5090bSLaurentiu Mihalcea&pinctrl_usb1 { 47*5bf5090bSLaurentiu Mihalcea fsl,pins = < 48*5bf5090bSLaurentiu Mihalcea MX8ULP_PAD_PTE16__USB0_ID 0x10003 49*5bf5090bSLaurentiu Mihalcea MX8ULP_PAD_PTE18__USB0_OC 0x10003 50*5bf5090bSLaurentiu Mihalcea >; 51*5bf5090bSLaurentiu Mihalcea}; 52*5bf5090bSLaurentiu Mihalcea 53*5bf5090bSLaurentiu Mihalcea&pinctrl_usb2 { 54*5bf5090bSLaurentiu Mihalcea fsl,pins = < 55*5bf5090bSLaurentiu Mihalcea MX8ULP_PAD_PTD23__USB1_ID 0x10003 56*5bf5090bSLaurentiu Mihalcea MX8ULP_PAD_PTE20__USB1_OC 0x10003 57*5bf5090bSLaurentiu Mihalcea >; 58*5bf5090bSLaurentiu Mihalcea}; 59*5bf5090bSLaurentiu Mihalcea 60*5bf5090bSLaurentiu Mihalcea&sai6 { 61*5bf5090bSLaurentiu Mihalcea pinctrl-names = "default", "sleep"; 62*5bf5090bSLaurentiu Mihalcea pinctrl-0 = <&pinctrl_sai6>; 63*5bf5090bSLaurentiu Mihalcea pinctrl-1 = <&pinctrl_sai6>; 64*5bf5090bSLaurentiu Mihalcea assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>, <&cgc2 IMX8ULP_CLK_SAI6_SEL>; 65*5bf5090bSLaurentiu Mihalcea assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>; 66*5bf5090bSLaurentiu Mihalcea assigned-clock-rates = <12288000>; 67*5bf5090bSLaurentiu Mihalcea fsl,dataline = <1 0x01 0x04>; 68*5bf5090bSLaurentiu Mihalcea status = "okay"; 69*5bf5090bSLaurentiu Mihalcea}; 70