1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2025 NXP 4 */ 5 6/dts-v1/; 7 8#include "imx8ulp-evk.dts" 9 10/ { 11 model = "NXP i.MX8ULP EVK9"; 12 compatible = "fsl,imx8ulp-9x9-evk", "fsl,imx8ulp"; 13}; 14 15&btcpu { 16 sound-dai = <&sai6>; 17}; 18 19&iomuxc1 { 20 pinctrl_sai6: sai6grp { 21 fsl,pins = < 22 MX8ULP_PAD_PTE10__I2S6_TX_BCLK 0x43 23 MX8ULP_PAD_PTE11__I2S6_TX_FS 0x43 24 MX8ULP_PAD_PTE14__I2S6_TXD2 0x43 25 MX8ULP_PAD_PTE6__I2S6_RXD0 0x43 26 >; 27 }; 28}; 29 30&pinctrl_enet { 31 fsl,pins = < 32 MX8ULP_PAD_PTF9__ENET0_MDC 0x43 33 MX8ULP_PAD_PTF8__ENET0_MDIO 0x43 34 MX8ULP_PAD_PTF5__ENET0_RXER 0x43 35 MX8ULP_PAD_PTF6__ENET0_CRS_DV 0x43 36 MX8ULP_PAD_PTF1__ENET0_RXD0 0x43 37 MX8ULP_PAD_PTF0__ENET0_RXD1 0x43 38 MX8ULP_PAD_PTF4__ENET0_TXEN 0x43 39 MX8ULP_PAD_PTF3__ENET0_TXD0 0x43 40 MX8ULP_PAD_PTF2__ENET0_TXD1 0x43 41 MX8ULP_PAD_PTF7__ENET0_REFCLK 0x43 42 MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43 43 >; 44}; 45 46&pinctrl_usb1 { 47 fsl,pins = < 48 MX8ULP_PAD_PTE16__USB0_ID 0x10003 49 MX8ULP_PAD_PTE18__USB0_OC 0x10003 50 >; 51}; 52 53&pinctrl_usb2 { 54 fsl,pins = < 55 MX8ULP_PAD_PTD23__USB1_ID 0x10003 56 MX8ULP_PAD_PTE20__USB1_OC 0x10003 57 >; 58}; 59 60&sai6 { 61 pinctrl-names = "default", "sleep"; 62 pinctrl-0 = <&pinctrl_sai6>; 63 pinctrl-1 = <&pinctrl_sai6>; 64 assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>, <&cgc2 IMX8ULP_CLK_SAI6_SEL>; 65 assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>; 66 assigned-clock-rates = <12288000>; 67 fsl,dataline = <1 0x01 0x04>; 68 status = "okay"; 69}; 70