1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2/* 3 * Copyright (c) 2019-2026 TQ-Systems GmbH <linux@ew.tq-group.com>, 4 * D-82229 Seefeld, Germany. 5 * Author: Alexander Stein 6 */ 7 8/dts-v1/; 9 10#include <dt-bindings/input/linux-event-codes.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/leds/common.h> 13#include <dt-bindings/net/ti-dp83867.h> 14#include <dt-bindings/pwm/pwm.h> 15 16#include "imx8qm-tqma8qm.dtsi" 17 18/ { 19 model = "TQ-Systems i.MX8QM TQMa8QM on MBa8x"; 20 compatible = "tq,imx8qm-tqma8qm-mba8x", "tq,imx8qm-tqma8qm", "fsl,imx8qm"; 21 22 adc { 23 compatible = "iio-hwmon"; 24 io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>; 25 }; 26 27 aliases { 28 rtc0 = &pcf85063; 29 rtc1 = &rtc; 30 }; 31 32 chosen { 33 stdout-path = &lpuart0; 34 }; 35 36 37 clk_xtal25: clk-xtal25 { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <25000000>; 41 }; 42 43 gpio-keys { 44 compatible = "gpio-keys"; 45 pinctrl-names = "default"; 46 pinctrl-0 = <&pinctrl_gpiokeys>; 47 autorepeat; 48 49 switch-1 { 50 label = "SWITCH_A"; 51 linux,code = <BTN_0>; 52 gpios = <&lsio_gpio2 11 GPIO_ACTIVE_LOW>; 53 wakeup-source; 54 }; 55 56 switch-2 { 57 label = "SWITCH_B"; 58 linux,code = <BTN_1>; 59 gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>; 60 wakeup-source; 61 }; 62 }; 63 64 gpio-leds { 65 compatible = "gpio-leds"; 66 pinctrl-names = "default"; 67 pinctrl-0 = <&pinctrl_gpioled>; 68 69 user-led0 { 70 color = <LED_COLOR_ID_GREEN>; 71 function = LED_FUNCTION_HEARTBEAT; 72 gpios = <&lsio_gpio5 20 GPIO_ACTIVE_HIGH>; 73 linux,default-trigger = "heartbeat"; 74 }; 75 76 user-led1 { 77 color = <LED_COLOR_ID_GREEN>; 78 function = LED_FUNCTION_STATUS; 79 gpios = <&lsio_gpio5 19 GPIO_ACTIVE_HIGH>; 80 default-state = "on"; 81 }; 82 }; 83 84 fan0: pwm-fan { 85 compatible = "pwm-fan"; 86 pinctrl-names = "default"; 87 pinctrl-0 = <&pinctrl_pwmfan>; 88 fan-supply = <®_pwm_fan>; 89 #cooling-cells = <2>; 90 /* typical 25 kHz -> 40.000 nsec */ 91 pwms = <&lsio_pwm3 0 40000 PWM_POLARITY_INVERTED>; 92 cooling-levels = <0 32 64 128 196 240>; 93 pulses-per-revolution = <2>; 94 interrupt-parent = <&lsio_gpio2>; 95 interrupts = <20 IRQ_TYPE_EDGE_FALLING>; 96 status = "disabled"; 97 }; 98 99 reg_mba8x_12v: regulator-mba8x-12v { 100 compatible = "regulator-fixed"; 101 pinctrl-names = "default"; 102 pinctrl-0 = <&pinctrl_reg_mba8x_12v>; 103 regulator-name = "MBa8x-V12"; 104 regulator-min-microvolt = <12000000>; 105 regulator-max-microvolt = <12000000>; 106 enable-active-high; 107 gpio = <&lsio_gpio1 2 GPIO_ACTIVE_HIGH>; 108 }; 109 110 reg_mba8x_v3v3: regulator-mba8x-v3v3 { 111 compatible = "regulator-fixed"; 112 regulator-name = "V_3V3_MB"; 113 regulator-min-microvolt = <3300000>; 114 regulator-max-microvolt = <3300000>; 115 regulator-always-on; 116 }; 117 118 reg_pwm_fan: regulator-pwm-fan { 119 compatible = "regulator-fixed"; 120 pinctrl-names = "default"; 121 pinctrl-0 = <&pinctrl_regpwmfan>; 122 regulator-name = "FAN_PWR"; 123 regulator-min-microvolt = <12000000>; 124 regulator-max-microvolt = <12000000>; 125 gpio = <&lsio_gpio2 12 GPIO_ACTIVE_HIGH>; 126 enable-active-high; 127 vin-supply = <®_mba8x_12v>; 128 }; 129 130 reg_usb_phy: regulator-usb-phy { 131 compatible = "regulator-fixed"; 132 regulator-max-microvolt = <3000000>; 133 regulator-min-microvolt = <3000000>; 134 regulator-name = "usb-phy-dummy"; 135 }; 136 137 reg_v1v5_pcie: regulator-v1v5-pcie { 138 compatible = "regulator-fixed"; 139 pinctrl-names = "default"; 140 pinctrl-0 = <&pinctrl_reg_pcie_v1v5>; 141 regulator-name = "V_1V5_MPCIE"; 142 regulator-min-microvolt = <1500000>; 143 regulator-max-microvolt = <1500000>; 144 vin-supply = <®_mba8x_v3v3>; 145 enable-active-high; 146 gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; 147 regulator-always-on; 148 }; 149 150 reg_v1v8: regulator-v1v8 { 151 compatible = "regulator-fixed"; 152 regulator-name = "MBa8x-V1V8"; 153 regulator-min-microvolt = <1800000>; 154 regulator-max-microvolt = <1800000>; 155 regulator-always-on; 156 }; 157 158 reg_v3v3_pcie: regulator-v3v3-pcie { 159 compatible = "regulator-fixed"; 160 pinctrl-names = "default"; 161 pinctrl-0 = <&pinctrl_reg_pcie_v3v3>; 162 regulator-name = "V_3V3_MPCIE"; 163 regulator-min-microvolt = <3300000>; 164 regulator-max-microvolt = <3300000>; 165 vin-supply = <®_mba8x_v3v3>; 166 enable-active-high; 167 gpio = <&lsio_gpio1 1 GPIO_ACTIVE_HIGH>; 168 regulator-always-on; 169 }; 170 171 reg_v3v3_sd: regulator-v3v3-sd { 172 compatible = "regulator-fixed"; 173 pinctrl-names = "default"; 174 pinctrl-0 = <&pinctrl_reg_v3v3_sd>; 175 regulator-name = "V3V3_SD"; 176 regulator-min-microvolt = <3300000>; 177 regulator-max-microvolt = <3300000>; 178 vin-supply = <®_mba8x_v3v3>; 179 gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; 180 enable-active-high; 181 regulator-boot-on; 182 off-on-delay-us = <200000>; 183 }; 184 185 reg_vref_v1v8: regulator-vref-v1v8 { 186 compatible = "regulator-fixed"; 187 regulator-name = "VREF_V1V8"; 188 regulator-min-microvolt = <1800000>; 189 regulator-max-microvolt = <1800000>; 190 regulator-always-on; 191 }; 192 193 reserved-memory { 194 #address-cells = <2>; 195 #size-cells = <2>; 196 ranges; 197 198 /* 199 * global autoconfigured region for contiguous allocations 200 * must not exceed memory size and region 201 */ 202 linux,cma { 203 compatible = "shared-dma-pool"; 204 reusable; 205 size = <0 0x3c000000>; 206 alloc-ranges = <0 0x96000000 0 0x3c000000>; 207 linux,cma-default; 208 }; 209 210 decoder_boot: decoder-boot@84000000 { 211 reg = <0 0x84000000 0 0x2000000>; 212 no-map; 213 }; 214 215 encoder1_boot: encoder1-boot@86000000 { 216 reg = <0 0x86000000 0 0x200000>; 217 no-map; 218 }; 219 220 encoder2_boot: encoder2-boot@86200000 { 221 reg = <0 0x86200000 0 0x200000>; 222 no-map; 223 }; 224 225 decoder_rpc: decoder-rpc@92000000 { 226 reg = <0 0x92000000 0 0x100000>; 227 no-map; 228 }; 229 230 encoder1_rpc: encoder1-rpc@92100000 { 231 reg = <0 0x92100000 0 0x700000>; 232 no-map; 233 }; 234 235 encoder2_rpc: encoder1-rpc@92800000 { 236 reg = <0 0x92800000 0 0x700000>; 237 no-map; 238 }; 239 }; 240 241 sound { 242 compatible = "fsl,imx-audio-tlv320aic32x4"; 243 model = "tqm-tlv320aic32"; 244 ssi-controller = <&sai1>; 245 audio-codec = <&tlv320aic3x04>; 246 audio-routing = 247 "IN3_L", "Mic Jack", 248 "Mic Jack", "Mic Bias", 249 "IN1_L", "Line In Jack", 250 "IN1_R", "Line In Jack", 251 "Line Out Jack", "LOL", 252 "Line Out Jack", "LOR"; 253 }; 254 255 sound-hdmi { 256 compatible = "fsl,imx-audio-hdmi"; 257 model = "imx-audio-dp"; 258 audio-cpu = <&sai5>; 259 hdmi-out; 260 }; 261 262 thermal-zones { 263 cpu0-thermal { 264 trips { 265 soc_active0_0: trip-active0 { 266 temperature = <40000>; 267 hysteresis = <5000>; 268 type = "active"; 269 }; 270 271 soc_active0_1: trip-active1 { 272 temperature = <48000>; 273 hysteresis = <3000>; 274 type = "active"; 275 }; 276 277 soc_active0_2: trip-active2 { 278 temperature = <60000>; 279 hysteresis = <10000>; 280 type = "active"; 281 }; 282 }; 283 284 cooling-maps { 285 map1 { 286 trip = <&soc_active0_0>; 287 cooling-device = <&fan0 1 1>; 288 }; 289 290 map2 { 291 trip = <&soc_active0_1>; 292 cooling-device = <&fan0 2 2>; 293 }; 294 295 map3 { 296 trip = <&soc_active0_2>; 297 cooling-device = <&fan0 3 3>; 298 }; 299 }; 300 }; 301 }; 302}; 303 304&fec1 { 305 pinctrl-names = "default"; 306 pinctrl-0 = <&pinctrl_fec1>; 307 phy-mode = "rgmii-id"; 308 phy-handle = <ðphy0>; 309 nvmem-cells = <&fec_mac0>; 310 nvmem-cell-names = "mac-address"; 311 status = "okay"; 312 313 mdio { 314 #address-cells = <1>; 315 #size-cells = <0>; 316 317 ethphy0: ethernet-phy@0 { 318 compatible = "ethernet-phy-ieee802.3-c22"; 319 reg = <0>; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&pinctrl_ethphy0>; 322 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 323 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 324 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 325 ti,dp83867-rxctrl-strap-quirk; 326 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 327 reset-gpios = <&lsio_gpio2 6 GPIO_ACTIVE_LOW>; 328 reset-assert-us = <500000>; 329 reset-deassert-us = <50000>; 330 enet-phy-lane-no-swap; 331 interrupt-parent = <&lsio_gpio2>; 332 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 333 }; 334 }; 335}; 336 337&fec2 { 338 pinctrl-names = "default"; 339 pinctrl-0 = <&pinctrl_fec2>; 340 phy-mode = "rgmii-id"; 341 phy-handle = <ðphy3>; 342 nvmem-cells = <&fec_mac1>; 343 nvmem-cell-names = "mac-address"; 344 status = "okay"; 345 346 mdio { 347 #address-cells = <1>; 348 #size-cells = <0>; 349 350 ethphy3: ethernet-phy@3 { 351 compatible = "ethernet-phy-ieee802.3-c22"; 352 reg = <3>; 353 pinctrl-names = "default"; 354 pinctrl-0 = <&pinctrl_ethphy3>; 355 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 356 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 357 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 358 ti,dp83867-rxctrl-strap-quirk; 359 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 360 reset-gpios = <&lsio_gpio2 4 GPIO_ACTIVE_LOW>; 361 reset-assert-us = <500000>; 362 reset-deassert-us = <50000>; 363 enet-phy-lane-no-swap; 364 }; 365 }; 366}; 367 368&flexcan1 { 369 pinctrl-names = "default"; 370 pinctrl-0 = <&pinctrl_flexcan1>; 371 status = "okay"; 372}; 373 374&flexcan2 { 375 pinctrl-names = "default"; 376 pinctrl-0 = <&pinctrl_flexcan2>; 377 status = "okay"; 378}; 379 380&hsio_phy { 381 fsl,hsio-cfg = "pciea-pcieb-sata"; 382 fsl,refclk-pad-mode = "input"; 383 status = "okay"; 384}; 385 386/* no refclock gating */ 387&hsio_refa_clk { 388 compatible = "fixed-factor-clock"; 389 clocks = <&pcieclk 0>; 390 clock-div = <1>; 391 clock-mult = <1>; 392 /delete-property/ enable-gpios; 393}; 394 395&hsio_refb_clk { 396 compatible = "fixed-factor-clock"; 397 clocks = <&pcieclk 0>; 398 clock-div = <1>; 399 clock-mult = <1>; 400 /delete-property/ enable-gpios; 401}; 402 403&i2c1 { 404 tlv320aic3x04: audio-codec@18 { 405 compatible = "ti,tlv320aic32x4"; 406 reg = <0x18>; 407 clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; 408 clock-names = "mclk"; 409 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 410 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 411 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 412 <&mclkout0_lpcg IMX_LPCG_CLK_0>; 413 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; 414 ldoin-supply = <®_mba8x_v3v3>; 415 iov-supply = <®_v1v8>; 416 }; 417 418 sensor1: temperature-sensor@1c { 419 compatible = "nxp,se97b", "jedec,jc-42.4-temp"; 420 reg = <0x1c>; 421 }; 422 423 eeprom2: eeprom@54 { 424 compatible = "nxp,se97b", "atmel,24c02"; 425 reg = <0x54>; 426 pagesize = <16>; 427 vcc-supply = <®_mba8x_v3v3>; 428 }; 429 430 pcieclk: clock-generator@68 { 431 compatible = "renesas,9fgv0441"; 432 reg = <0x68>; 433 clocks = <&clk_xtal25>; 434 #clock-cells = <1>; 435 }; 436}; 437 438&lpspi0 { 439 pinctrl-names = "default"; 440 pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>; 441 cs-gpios = <&lsio_gpio3 5 GPIO_ACTIVE_LOW>, <&lsio_gpio3 6 GPIO_ACTIVE_LOW>; 442 status = "okay"; 443}; 444 445&lpspi1 { 446 pinctrl-names = "default"; 447 pinctrl-0 = <&pinctrl_lpspi1 &pinctrl_lpspi1_cs>; 448 cs-gpios = <&lsio_gpio3 24 GPIO_ACTIVE_LOW>, <&lsio_gpio3 25 GPIO_ACTIVE_LOW>; 449 status = "okay"; 450}; 451 452&lpspi2 { 453 pinctrl-names = "default"; 454 pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>; 455 cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>, <&lsio_gpio3 11 GPIO_ACTIVE_LOW>; 456 status = "okay"; 457}; 458 459&lpuart0 { 460 /* console */ 461 pinctrl-names = "default"; 462 pinctrl-0 = <&pinctrl_lpuart0>; 463 status = "okay"; 464}; 465 466&lpuart1 { 467 /* X62 pin header */ 468 pinctrl-names = "default"; 469 pinctrl-0 = <&pinctrl_lpuart1>; 470 status = "okay"; 471}; 472 473&lpuart2 { 474 /* mikroBUS */ 475 pinctrl-names = "default"; 476 pinctrl-0 = <&pinctrl_lpuart2>; 477 status = "okay"; 478}; 479 480&lsio_gpio2 { 481 pinctrl-names = "default"; 482 pinctrl-0 = <&pinctrl_gpio2>; 483 gpio-line-names = "", "", "", "", 484 "", "PCIE0_DISABLE#", "", ""; 485 486 pcie0-wdisable1-hog { 487 gpio-hog; 488 gpios = <5 0>; 489 output-high; 490 line-name = "PCIE0_DISABLE#"; 491 }; 492 493 pcie-clk-pd-hog { 494 gpio-hog; 495 gpios = <10 0>; 496 output-high; 497 line-name = "PCIE_CLK_PD#"; 498 }; 499}; 500 501&lsio_pwm3 { 502 pinctrl-names = "default"; 503 pinctrl-0 = <&pinctrl_lsio_pwm3>; 504 status = "okay"; 505}; 506 507&pciea { 508 pinctrl-names = "default"; 509 pinctrl-0 = <&pinctrl_pciea>; 510 phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; 511 phy-names = "pcie-phy"; 512 reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; 513 status = "okay"; 514}; 515 516&pcieb { 517 pinctrl-names = "default"; 518 pinctrl-0 = <&pinctrl_pcieb>; 519 phys = <&hsio_phy 1 PHY_TYPE_PCIE 1>; 520 phy-names = "pcie-phy"; 521 reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; 522 status = "okay"; 523}; 524 525&sai1 { 526 pinctrl-names = "default"; 527 pinctrl-0 = <&pinctrl_sai1>; 528 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 529 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 530 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 531 <&sai1_lpcg IMX_LPCG_CLK_0>; 532 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 533 status = "okay"; 534}; 535 536&sai5 { 537 status = "okay"; 538}; 539 540&sai5_lpcg { 541 status = "okay"; 542}; 543 544&sata { 545 status = "okay"; 546}; 547 548&usbphy1 { 549 phy-3p0-supply = <®_usb_phy>; 550 status = "okay"; 551}; 552 553&usbotg1 { 554 pinctrl-names = "default"; 555 pinctrl-0 = <&pinctrl_usbotg1>; 556 srp-disable; 557 hnp-disable; 558 adp-disable; 559 power-active-high; 560 over-current-active-low; 561 dr_mode = "otg"; 562 status = "okay"; 563}; 564 565&usb3_phy { 566 status = "okay"; 567}; 568 569&usbotg3 { 570 /* over-current disabled by default */ 571 status = "okay"; 572}; 573 574&usbotg3_cdns3 { 575 dr_mode = "host"; 576 #address-cells = <1>; 577 #size-cells = <0>; 578 pinctrl-names = "default"; 579 pinctrl-0 = <&pinctrl_usbhub>; 580 status = "okay"; 581 582 hub_2_0: hub@1 { 583 compatible = "usb451,8142"; 584 reg = <1>; 585 peer-hub = <&hub_3_0>; 586 reset-gpios = <&lsio_gpio2 7 GPIO_ACTIVE_LOW>; 587 vdd-supply = <®_mba8x_v3v3>; 588 }; 589 590 hub_3_0: hub@2 { 591 compatible = "usb451,8140"; 592 reg = <2>; 593 peer-hub = <&hub_2_0>; 594 reset-gpios = <&lsio_gpio2 7 GPIO_ACTIVE_LOW>; 595 vdd-supply = <®_mba8x_v3v3>; 596 }; 597}; 598 599&usdhc2 { 600 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 601 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 602 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 603 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 604 bus-width = <4>; 605 cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; 606 wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; 607 vmmc-supply = <®_v3v3_sd>; 608 no-mmc; 609 no-sdio; 610 status = "okay"; 611}; 612 613&iomuxc { 614 pinctrl-names = "default"; 615 pinctrl-0 = <&pinctrl_gpio>; 616 617 pinctrl_adc0: adc0grp { 618 fsl,pins = <IMX8QM_ADC_IN1_DMA_ADC0_IN1 0x02000060>, 619 <IMX8QM_ADC_IN2_DMA_ADC0_IN2 0x02000060>; 620 }; 621 622 pinctrl_ethphy0: ethphy0grp { 623 fsl,pins = <IMX8QM_ESAI1_SCKR_LSIO_GPIO2_IO06 0x00000041>, 624 <IMX8QM_ESAI1_TX0_LSIO_GPIO2_IO08 0x00000021>; 625 }; 626 627 pinctrl_ethphy3: ethphy3grp { 628 fsl,pins = <IMX8QM_ESAI1_FSR_LSIO_GPIO2_IO04 0x00000041>; 629 }; 630 631 pinctrl_fec1: fec1grp { 632 fsl,pins = <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0>, 633 <IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000041>, 634 <IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000041>, 635 <IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000041>, 636 <IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000041>, 637 <IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000041>, 638 <IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000041>, 639 <IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000041>, 640 <IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000041>, 641 <IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000040>, 642 <IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000040>, 643 <IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000040>, 644 <IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000040>, 645 <IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000040>, 646 <IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000040>; 647 }; 648 649 pinctrl_fec2: fec2grp { 650 fsl,pins = <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0>, 651 <IMX8QM_ENET1_MDC_CONN_ENET1_MDC 0x06000041>, 652 <IMX8QM_ENET1_MDIO_CONN_ENET1_MDIO 0x06000041>, 653 <IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000041>, 654 <IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000041>, 655 <IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000041>, 656 <IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000041>, 657 <IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000041>, 658 <IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000041>, 659 <IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000040>, 660 <IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000040>, 661 <IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000040>, 662 <IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000040>, 663 <IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000040>, 664 <IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000040>; 665 }; 666 667 pinctrl_flexcan1: flexcan0grp { 668 fsl,pins = <IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x00000021>, 669 <IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x00000021>; 670 }; 671 672 pinctrl_flexcan2: flexcan1grp { 673 fsl,pins = <IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x00000021>, 674 <IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x00000021>; 675 }; 676 677 pinctrl_gpio2: gpio2grp { 678 fsl,pins = <IMX8QM_ESAI1_FST_LSIO_GPIO2_IO05 0x00000021>, 679 <IMX8QM_ESAI1_TX2_RX3_LSIO_GPIO2_IO10 0x00000021>; 680 }; 681 682 pinctrl_gpio: gpiogrp { 683 fsl,pins = /* GPIO0_05 on X62:26 */ 684 <IMX8QM_SIM0_GPIO0_00_LSIO_GPIO0_IO05 0x00000021>, 685 /* GPIO1_14 on X64:21 */ 686 <IMX8QM_LVDS1_I2C1_SCL_LSIO_GPIO1_IO14 0x00000021>, 687 /* GPIO1_15 on X64:23 */ 688 <IMX8QM_LVDS1_I2C1_SDA_LSIO_GPIO1_IO15 0x00000021>, 689 /* GPIO2_17 on X63:37 */ 690 <IMX8QM_SPI3_SCK_LSIO_GPIO2_IO17 0x00000021>, 691 /* GPIO2_21 on X63:39 */ 692 <IMX8QM_SPI3_CS1_LSIO_GPIO2_IO21 0x00000021>, 693 /* GPIO4_12 on X61:24 */ 694 <IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021>, 695 /* GPIO4_11 on X61:26 */ 696 <IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021>, 697 /* GPIO4_10 on X61:28 */ 698 <IMX8QM_USDHC2_VSELECT_LSIO_GPIO4_IO10 0x00000021>, 699 /* GPIO4_09 on X61:30 */ 700 <IMX8QM_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x00000021>, 701 /* GPIO5_23 on X62:24 */ 702 <IMX8QM_USDHC1_STROBE_LSIO_GPIO5_IO23 0x00000021>, 703 /* GPIO5_24 on X61:15 */ 704 <IMX8QM_USDHC2_CLK_LSIO_GPIO5_IO24 0x00000021>, 705 /* GPIO5_25 on X61:17 */ 706 <IMX8QM_USDHC2_CMD_LSIO_GPIO5_IO25 0x00000021>, 707 /* GPIO5_26 on X61:19 */ 708 <IMX8QM_USDHC2_DATA0_LSIO_GPIO5_IO26 0x00000021>, 709 /* GPIO5_27 on X61:21 */ 710 <IMX8QM_USDHC2_DATA1_LSIO_GPIO5_IO27 0x00000021>, 711 /* GPIO5_28 on X61:23 */ 712 <IMX8QM_USDHC2_DATA2_LSIO_GPIO5_IO28 0x00000021>, 713 /* GPIO5_29 on X61:25 */ 714 <IMX8QM_USDHC2_DATA3_LSIO_GPIO5_IO29 0x00000021>; 715 }; 716 717 pinctrl_gpiokeys: gpiokeysgrp { 718 fsl,pins = <IMX8QM_ESAI1_TX3_RX2_LSIO_GPIO2_IO11 0x00000021>, 719 <IMX8QM_SCU_GPIO0_04_LSIO_GPIO1_IO00 0x00000021>; 720 }; 721 722 pinctrl_gpioled: gpioledgrp { 723 fsl,pins = <IMX8QM_USDHC1_DATA4_LSIO_GPIO5_IO19 0x00000021>, 724 <IMX8QM_USDHC1_DATA5_LSIO_GPIO5_IO20 0x00000021>; 725 }; 726 727 pinctrl_lpspi0_cs: lpspi0csgrp { 728 fsl,pins = <IMX8QM_SPI0_CS0_LSIO_GPIO3_IO05 0x00000021>, 729 <IMX8QM_SPI0_CS1_LSIO_GPIO3_IO06 0x00000021>; 730 }; 731 732 pinctrl_lpspi0: lpspi0grp { 733 fsl,pins = <IMX8QM_SPI0_SCK_DMA_SPI0_SCK 0x0600004d>, 734 <IMX8QM_SPI0_SDO_DMA_SPI0_SDO 0x0600004d>, 735 <IMX8QM_SPI0_SDI_DMA_SPI0_SDI 0x0600004d>; 736 }; 737 738 pinctrl_lpspi1_cs: lpspi1csgrp { 739 fsl,pins = <IMX8QM_ADC_IN6_LSIO_GPIO3_IO24 0x00000021>, 740 <IMX8QM_ADC_IN7_LSIO_GPIO3_IO25 0x00000021>; 741 }; 742 743 pinctrl_lpspi1: lpspi1grp { 744 fsl,pins = <IMX8QM_ADC_IN3_DMA_SPI1_SCK 0x0600004d>, 745 <IMX8QM_ADC_IN4_DMA_SPI1_SDO 0x0600004d>, 746 <IMX8QM_ADC_IN5_DMA_SPI1_SDI 0x0600004d>; 747 }; 748 749 pinctrl_lpspi2: lpspi2grp { 750 fsl,pins = <IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x0600004d>, 751 <IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x0600004d>, 752 <IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x0600004d>; 753 }; 754 755 pinctrl_lpspi2_cs: lpspi2sgrp { 756 fsl,pins = <IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x00000021>, 757 <IMX8QM_SPI2_CS1_LSIO_GPIO3_IO11 0x00000021>; 758 }; 759 760 pinctrl_lpuart0: lpuart0grp { 761 fsl,pins = <IMX8QM_UART0_RX_DMA_UART0_RX 0x06000021>, 762 <IMX8QM_UART0_TX_DMA_UART0_TX 0x06000021>, 763 <IMX8QM_UART0_CTS_B_DMA_UART0_CTS_B 0x00000021>, 764 <IMX8QM_UART0_RTS_B_DMA_UART0_RTS_B 0x00000021>; 765 }; 766 767 pinctrl_lpuart1: lpuart1grp { 768 fsl,pins = <IMX8QM_UART1_RX_DMA_UART1_RX 0x06000021>, 769 <IMX8QM_UART1_TX_DMA_UART1_TX 0x06000021>, 770 <IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x00000021>, 771 <IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x00000021>; 772 }; 773 774 pinctrl_lpuart2: lpuart2grp { 775 fsl,pins = <IMX8QM_LVDS0_I2C1_SDA_DMA_UART2_RX 0x06000021>, 776 <IMX8QM_LVDS0_I2C1_SCL_DMA_UART2_TX 0x06000021>; 777 }; 778 779 pinctrl_lsio_pwm3: lsiopwm3grp { 780 fsl,pins = <IMX8QM_GPT0_COMPARE_LSIO_PWM3_OUT 0x00000021>; 781 }; 782 783 pinctrl_pciea: pcieagrp { 784 fsl,pins = <IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021>, 785 <IMX8QM_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B 0x06000021>, 786 <IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021>; 787 }; 788 789 pinctrl_pcieb: pciebgrp { 790 fsl,pins = <IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000021>, 791 <IMX8QM_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B 0x06000021>, 792 <IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021>; 793 }; 794 795 pinctrl_pwmfan: pwmfangrp { 796 fsl,pins = <IMX8QM_SPI3_CS0_LSIO_GPIO2_IO20 0x30>; 797 }; 798 799 pinctrl_reg_mba8x_12v: regmba12vgrp { 800 fsl,pins = <IMX8QM_SCU_GPIO0_06_LSIO_GPIO1_IO02 0x00000021>; 801 }; 802 803 pinctrl_reg_pcie_v1v5: regpcie1v5grp { 804 fsl,pins = <IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x00000021>; 805 }; 806 807 pinctrl_reg_pcie_v3v3: regpcie3v3grp { 808 fsl,pins = <IMX8QM_SCU_GPIO0_05_LSIO_GPIO1_IO01 0x00000021>; 809 }; 810 811 pinctrl_regpwmfan: regpwmfangrp { 812 fsl,pins = <IMX8QM_ESAI1_TX4_RX1_LSIO_GPIO2_IO12 0x00000021>; 813 }; 814 815 pinctrl_reg_v3v3_sd: regv3v3sdgrp { 816 fsl,pins = <IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021>; 817 }; 818 819 pinctrl_sai1: sai1grp { 820 fsl,pins = <IMX8QM_SAI1_RXD_AUD_SAI1_RXD 0x06000041>, 821 <IMX8QM_SAI1_RXC_AUD_SAI1_RXC 0x06000041>, 822 <IMX8QM_SAI1_RXFS_AUD_SAI1_RXFS 0x06000041>, 823 <IMX8QM_SAI1_TXD_AUD_SAI1_TXD 0x06000061>, 824 <IMX8QM_SAI1_TXC_AUD_SAI1_TXC 0x06000041>, 825 <IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004d>; 826 }; 827 828 pinctrl_usbhub: usbhubgrp { 829 fsl,pins = <IMX8QM_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000021>; 830 }; 831 832 pinctrl_usbotg1: usbotg1grp { 833 fsl,pins = <IMX8QM_USB_SS3_TC2_CONN_USB_OTG1_OC 0x00000021>, 834 <IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021>; 835 }; 836 837 pinctrl_usdhc2: usdhc2grp { 838 fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>, 839 <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021>, 840 <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021>, 841 <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021>, 842 <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021>, 843 <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021>, 844 <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>; 845 }; 846 847 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 848 fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>, 849 <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021>, 850 <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021>, 851 <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021>, 852 <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021>, 853 <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021>, 854 <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>; 855 }; 856 857 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 858 fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>, 859 <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021>, 860 <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021>, 861 <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021>, 862 <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021>, 863 <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021>, 864 <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>; 865 }; 866 867 pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 868 fsl,pins = <IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021>, 869 <IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021>; 870 }; 871}; 872