1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2025 Ultratronik 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/usb/pd.h> 9#include "imx8mp.dtsi" 10 11/ { 12 model = "NXP i.MX8MPlus Ultratronik MMI_A53 board"; 13 compatible = "ultratronik,imx8mp-ultra-mach-sbc", "fsl,imx8mp"; 14 15 aliases { 16 ethernet0 = &fec; 17 ethernet1 = &eqos; 18 rtc0 = &hwrtc; 19 rtc1 = &snvs_rtc; 20 }; 21 22 chosen { 23 stdout-path = &uart2; 24 }; 25 26 gpio-sbu-mux { 27 compatible = "nxp,cbdtu02043", "gpio-sbu-mux"; 28 pinctrl-names = "default"; 29 pinctrl-0 = <&pinctrl_sbu_mux>; 30 select-gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; 31 enable-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; 32 orientation-switch; 33 34 port { 35 usb3_data_ss: endpoint { 36 remote-endpoint = <&typec_con_ss>; 37 }; 38 }; 39 }; 40 41 gpio-keys { 42 compatible = "gpio-keys"; 43 44 button-0 { 45 gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; /* Wakeup */ 46 label = "Wakeup"; 47 linux,code = <KEY_WAKEUP>; 48 pinctrl-0 = <&pinctrl_gpio_key_wakeup>; 49 pinctrl-names = "default"; 50 wakeup-source; 51 }; 52 }; 53 54 leds { 55 compatible = "gpio-leds"; 56 pinctrl-names = "default"; 57 pinctrl-0 = <&pinctrl_gpio_leds>; 58 59 led1 { 60 label = "red"; 61 gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; 62 default-state = "off"; 63 }; 64 65 led2 { 66 label = "green"; 67 gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; 68 default-state = "off"; 69 }; 70 71 led3 { 72 label = "yellow"; 73 gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; 74 default-state = "off"; 75 }; 76 }; 77 78 reg_usba_vbus: regulator-usba-vbus { 79 compatible = "regulator-fixed"; 80 pinctrl-names = "default"; 81 pinctrl-0 = <&pinctrl_usb1>; 82 regulator-name = "usb-A-vbus"; 83 regulator-min-microvolt = <5000000>; 84 regulator-max-microvolt = <5000000>; 85 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 86 enable-active-high; 87 }; 88 89 reg_usdhc2_vmmc: regulator-usdhc2 { 90 compatible = "regulator-fixed"; 91 pinctrl-names = "default"; 92 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 93 regulator-name = "VSD_3V3"; 94 regulator-min-microvolt = <3300000>; 95 regulator-max-microvolt = <3300000>; 96 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 97 enable-active-high; 98 }; 99}; 100 101&A53_0 { 102 cpu-supply = <&buck2>; 103}; 104 105&A53_1 { 106 cpu-supply = <&buck2>; 107}; 108 109&A53_2 { 110 cpu-supply = <&buck2>; 111}; 112 113&A53_3 { 114 cpu-supply = <&buck2>; 115}; 116 117&ecspi1 { 118 #address-cells = <1>; 119 #size-cells = <0>; 120 pinctrl-names = "default"; 121 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; 122 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 123 status = "okay"; 124 125 slb9670: tpm@0 { 126 compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; 127 reg = <0>; 128 spi-max-frequency = <32000000>; 129 pinctrl-names = "default"; 130 pinctrl-0 = <&pinctrl_slb9670>; 131 interrupt-parent = <&gpio1>; 132 interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 133 }; 134}; 135 136&ecspi2 { 137 #address-cells = <1>; 138 #size-cells = <0>; 139 pinctrl-names = "default"; 140 pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; 141 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, 142 <&gpio1 8 GPIO_ACTIVE_LOW>, 143 <&gpio1 9 GPIO_ACTIVE_LOW>; 144 status = "okay"; 145 146 nfc-transceiver@1 { 147 compatible = "st,st95hf"; 148 reg = <1>; 149 pinctrl-names = "default"; 150 pinctrl-0 = <&pinctrl_nfc>; 151 spi-max-frequency = <100000>; 152 interrupt-parent = <&gpio1>; 153 interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 154 enable-gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; 155 }; 156}; 157 158&eqos { 159 pinctrl-names = "default"; 160 pinctrl-0 = <&pinctrl_eqos>; 161 phy-mode = "rgmii-id"; 162 phy-handle = <ðphy0>; 163 status = "okay"; 164 165 mdio { 166 compatible = "snps,dwmac-mdio"; 167 #address-cells = <1>; 168 #size-cells = <0>; 169 170 ethphy0: ethernet-phy@1 { 171 compatible = "ethernet-phy-ieee802.3-c22"; 172 reg = <0x1>; 173 interrupt-parent = <&gpio4>; 174 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 175 }; 176 }; 177}; 178 179&fec { 180 pinctrl-names = "default"; 181 pinctrl-0 = <&pinctrl_fec>; 182 phy-mode = "rgmii-id"; 183 phy-handle = <ðphy1>; 184 fsl,magic-packet; 185 status = "okay"; 186 187 mdio { 188 #address-cells = <1>; 189 #size-cells = <0>; 190 191 ethphy1: ethernet-phy@2 { 192 compatible = "ethernet-phy-ieee802.3-c22"; 193 reg = <0x2>; 194 interrupt-parent = <&gpio4>; 195 interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 196 }; 197 }; 198}; 199 200&flexcan1 { 201 pinctrl-names = "default"; 202 pinctrl-0 = <&pinctrl_flexcan1>; 203 status = "okay"; 204}; 205 206&gpio1 { 207 gpio-line-names = 208 "#TPM_IRQ", "GPIO1", "", "#PMIC_INT", 209 "SD2_VSEL", "#TOUCH_IRQ", "#NFC_INT_I", "#NFC_INT", 210 "#SPI2_CS2", "#SPI2_CS3", "#RTS4", "", 211 "USB_PWR", "GPIO2", "GPIO3", ""; 212}; 213 214&gpio2 { 215 gpio-line-names = 216 "", "", "", "", "", "", "", "", 217 "", "", "", "", "#SD2_CD", "", "", "", 218 "", "", "", "", "#USB-C_EN", "", "", "", 219 "", "", "", "", "", "", "", ""; 220}; 221 222&gpio3 { 223 gpio-line-names = 224 "", "", "", "", "", "", "", "", 225 "", "", "", "", "", "", "", "", 226 "", "", "", "", "", "", "DISP_POW", "GPIO4", 227 "#", "", "", "", "", "", "", ""; 228}; 229 230&gpio4 { 231 gpio-line-names = 232 "BKL_POW", "#ETH1_INT", "#TPM_RES", "#PCAP_RES", 233 "", "", "", "", 234 "", "", "", "", "", "", "", "", 235 "", "", "#ETH0_INT", "#USB-C_ALERT", 236 "#USB-C_SEL", "", "", "", 237 "LED_RED", "LED_GREEN", "LED_YELLOW", "#WAKEUP", 238 "", "", "", ""; 239}; 240 241&gpio5 { 242 gpio-line-names = 243 "", "", "", "", "", "", "", "", 244 "", "#SPI1_CS", "", "", "", "#SPI2_CS1", "", "", 245 "", "", "", "", "ENA_KAM", "ENA_LED", "", "", 246 "", "", "", "", "", "", "", ""; 247}; 248 249&hdmi_pvi { 250 status = "okay"; 251}; 252 253&hdmi_tx { 254 ddc-i2c-bus = <&i2c5>; 255 pinctrl-names = "default"; 256 pinctrl-0 = <&pinctrl_hdmi>; 257 status = "okay"; 258}; 259 260&hdmi_tx_phy { 261 status = "okay"; 262}; 263 264&i2c1 { 265 clock-frequency = <100000>; 266 pinctrl-names = "default", "gpio"; 267 pinctrl-0 = <&pinctrl_i2c1>; 268 pinctrl-1 = <&pinctrl_i2c1_gpio>; 269 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 270 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 271 status = "okay"; 272 273 pmic@25 { 274 compatible = "nxp,pca9450c"; 275 reg = <0x25>; 276 pinctrl-0 = <&pinctrl_pmic>; 277 interrupt-parent = <&gpio1>; 278 interrupts = <3 GPIO_ACTIVE_LOW>; 279 280 /* 281 * i.MX 8M Plus Data Sheet for Consumer Products 282 * 3.1.4 Operating ranges 283 * MIMX8ML8DVNLZAB 284 */ 285 regulators { 286 buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */ 287 regulator-min-microvolt = <850000>; 288 regulator-max-microvolt = <1050000>; 289 regulator-always-on; 290 regulator-boot-on; 291 regulator-ramp-delay = <3125>; 292 }; 293 294 buck2: BUCK2 { /* VDD_ARM */ 295 regulator-min-microvolt = <850000>; 296 regulator-max-microvolt = <1000000>; 297 regulator-always-on; 298 regulator-boot-on; 299 regulator-ramp-delay = <3125>; 300 nxp,dvs-run-voltage = <950000>; 301 nxp,dvs-standby-voltage = <850000>; 302 }; 303 304 buck4: BUCK4 { /* +3V3 */ 305 regulator-min-microvolt = <3300000>; 306 regulator-max-microvolt = <3300000>; 307 regulator-always-on; 308 regulator-boot-on; 309 }; 310 311 buck5: BUCK5 { /* +1V8 */ 312 regulator-min-microvolt = <1800000>; 313 regulator-max-microvolt = <1800000>; 314 regulator-always-on; 315 regulator-boot-on; 316 }; 317 318 buck6: BUCK6 { /* DRAM_1V1 */ 319 regulator-min-microvolt = <1100000>; 320 regulator-max-microvolt = <1100000>; 321 regulator-always-on; 322 regulator-boot-on; 323 }; 324 325 ldo1: LDO1 { /* NVCC_SNVS_1V8 */ 326 regulator-min-microvolt = <1800000>; 327 regulator-max-microvolt = <1800000>; 328 regulator-always-on; 329 regulator-boot-on; 330 }; 331 332 ldo3: LDO3 { /* VDDA_1P8 */ 333 regulator-min-microvolt = <1800000>; 334 regulator-max-microvolt = <1800000>; 335 regulator-always-on; 336 regulator-boot-on; 337 }; 338 339 ldo4: LDO4 { /* ENET_2V5 */ 340 regulator-min-microvolt = <2500000>; 341 regulator-max-microvolt = <2500000>; 342 regulator-always-on; 343 regulator-boot-on; 344 }; 345 346 ldo5: LDO5 { /* NVCC_SD2 */ 347 regulator-min-microvolt = <1800000>; 348 regulator-max-microvolt = <3300000>; 349 regulator-always-on; 350 regulator-boot-on; 351 }; 352 }; 353 }; 354 355 crypto@35 { 356 compatible = "atmel,atecc508a"; 357 reg = <0x35>; 358 }; 359 360 eeprom@50 { 361 compatible = "atmel,24c16"; 362 reg = <0x50>; 363 pagesize = <16>; 364 }; 365}; 366 367&i2c2 { 368 clock-frequency = <100000>; 369 pinctrl-names = "default", "gpio"; 370 pinctrl-0 = <&pinctrl_i2c2>; 371 pinctrl-1 = <&pinctrl_i2c2_gpio>; 372 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 373 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 374 status = "okay"; 375 376 hwrtc: rtc@32 { 377 compatible = "epson,rx8900"; 378 reg = <0x32>; 379 epson,vdet-disable; 380 trickle-diode-disable; 381 }; 382 383 tcpc@52 { 384 compatible = "nxp,ptn5110", "tcpci"; 385 reg = <0x52>; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&pinctrl_ptn5110>; 388 interrupt-parent = <&gpio4>; 389 interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 390 391 usb_con: connector { 392 compatible = "usb-c-connector"; 393 label = "USB-C"; 394 power-role = "dual"; 395 data-role = "dual"; 396 try-power-role = "sink"; 397 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 398 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 399 PDO_VAR(5000, 5000, 3000)>; 400 op-sink-microwatt = <15000000>; 401 self-powered; 402 403 ports { 404 #address-cells = <1>; 405 #size-cells = <0>; 406 407 port@0 { 408 reg = <0>; 409 410 typec_dr_sw: endpoint { 411 remote-endpoint = <&usb3_drd_sw>; 412 }; 413 }; 414 415 port@1 { 416 reg = <1>; 417 418 typec_con_ss: endpoint { 419 remote-endpoint = <&usb3_data_ss>; 420 }; 421 }; 422 }; 423 }; 424 }; 425}; 426 427&i2c3 { 428 clock-frequency = <100000>; 429 pinctrl-names = "default", "gpio"; 430 pinctrl-0 = <&pinctrl_i2c3>; 431 pinctrl-1 = <&pinctrl_i2c3_gpio>; 432 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 433 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 434 status = "okay"; 435}; 436 437&i2c5 { /* HDMI EDID bus */ 438 clock-frequency = <100000>; 439 pinctrl-names = "default", "gpio"; 440 pinctrl-0 = <&pinctrl_i2c5>; 441 pinctrl-1 = <&pinctrl_i2c5_gpio>; 442 scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 443 sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 444 status = "okay"; 445}; 446 447&lcdif3 { 448 status = "okay"; 449}; 450 451&pwm1 { 452 pinctrl-names = "default"; 453 pinctrl-0 = <&pinctrl_pwm1>; 454 status = "okay"; 455}; 456 457&pwm2 { 458 pinctrl-names = "default"; 459 pinctrl-0 = <&pinctrl_pwm2>; 460 status = "okay"; 461}; 462 463&snvs_pwrkey { 464 status = "okay"; 465}; 466 467&uart2 { 468 /* system console */ 469 pinctrl-names = "default"; 470 pinctrl-0 = <&pinctrl_uart2>; 471 status = "okay"; 472}; 473 474&uart3 { 475 pinctrl-names = "default"; 476 pinctrl-0 = <&pinctrl_uart3>; 477 status = "okay"; 478}; 479 480&uart4 { 481 /* expansion port serial connection */ 482 pinctrl-names = "default"; 483 pinctrl-0 = <&pinctrl_uart4>; 484 status = "okay"; 485}; 486 487&usb3_phy0 { 488 status = "okay"; 489}; 490 491&usb3_0 { 492 status = "okay"; 493}; 494 495&usb_dwc3_0 { 496 dr_mode = "otg"; 497 hnp-disable; 498 srp-disable; 499 adp-disable; 500 usb-role-switch; 501 status = "okay"; 502 503 port { 504 usb3_drd_sw: endpoint { 505 remote-endpoint = <&typec_dr_sw>; 506 }; 507 }; 508}; 509 510&usb3_phy1 { 511 vbus-supply = <®_usba_vbus>; 512 status = "okay"; 513}; 514 515&usb3_1 { 516 status = "okay"; 517}; 518 519&usb_dwc3_1 { 520 dr_mode = "host"; 521 snps,hsphy_interface = "utmi"; 522 status = "okay"; 523}; 524 525&usdhc2 { 526 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; 527 assigned-clock-rates = <400000000>; 528 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 529 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 530 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 531 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 532 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 533 bus-width = <4>; 534 vmmc-supply = <®_usdhc2_vmmc>; 535 vqmmc-supply = <&ldo5>; 536 status = "okay"; 537}; 538 539&usdhc3 { 540 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; 541 assigned-clock-rates = <400000000>; 542 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 543 pinctrl-0 = <&pinctrl_usdhc3>; 544 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 545 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 546 vmmc-supply = <&buck4>; 547 vqmmc-supply = <&buck5>; 548 bus-width = <8>; 549 no-sd; 550 no-sdio; 551 non-removable; 552 status = "okay"; 553}; 554 555&wdog1 { 556 pinctrl-names = "default"; 557 pinctrl-0 = <&pinctrl_wdog>; 558 fsl,ext-reset-output; 559 status = "okay"; 560}; 561 562&iomuxc { 563 pinctrl-names = "default"; 564 pinctrl-0 = <&pinctrl_hog>; 565 566 pinctrl_ecspi1_cs: ecspi1-cs-grp { 567 fsl,pins = < 568 MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40 /* #SPI1_CS */ 569 >; 570 }; 571 572 pinctrl_ecspi1: ecspi1-grp { 573 fsl,pins = < 574 MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82 575 MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82 576 MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82 577 >; 578 }; 579 580 pinctrl_ecspi2_cs: ecspi2-cs-grp { 581 fsl,pins = < 582 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40 /* #SPI2_CS */ 583 MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40 /* #SPI2_CS2 */ 584 MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40 /* #SPI2_CS3 */ 585 >; 586 }; 587 588 pinctrl_ecspi2: ecspi2-grp { 589 fsl,pins = < 590 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 591 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 592 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 593 >; 594 }; 595 596 pinctrl_eqos: eqos-grp { 597 fsl,pins = < 598 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x0 599 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x0 600 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 601 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 602 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 603 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 604 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 605 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 606 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 607 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 608 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 609 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 610 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 611 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 612 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x10 /* #ETH0_INT */ 613 >; 614 }; 615 616 pinctrl_fec: fec-grp { 617 fsl,pins = < 618 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x0 619 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x0 620 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 621 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 622 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 623 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 624 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 625 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 626 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 627 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 628 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 629 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 630 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 631 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 632 MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x10 /* #ETH1_INT */ 633 >; 634 }; 635 636 pinctrl_flexcan1: flexcan1-grp { 637 fsl,pins = < 638 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 639 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 640 >; 641 }; 642 643 pinctrl_gpio_key_wakeup: gpio-key-wakeup-grp { 644 fsl,pins = < 645 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40 /* #WAKEUP */ 646 >; 647 }; 648 649 pinctrl_gpio_leds: gpio-leds-grp { 650 fsl,pins = < 651 MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x40 /* LED_RED */ 652 MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x40 /* LED_GREEN */ 653 MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40 /* LED_YELLOW */ 654 >; 655 }; 656 657 pinctrl_hdmi: hdmi-grp { 658 fsl,pins = < 659 MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x154 660 MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x154 661 >; 662 }; 663 664 pinctrl_hog: hog-grp { 665 fsl,pins = < 666 MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x40 /* GPIO1 */ 667 MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x40 /* GPIO2 */ 668 MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x40 /* GPIO3 */ 669 MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x40 /* GPIO4 */ 670 MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x40 /* ENA_KAM */ 671 MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x40 /* ENA_LED */ 672 MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x40 /* #PCAP_RES */ 673 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x40 /* #RTS4 */ 674 >; 675 }; 676 677 pinctrl_i2c1: i2c1-grp { 678 fsl,pins = < 679 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c0 680 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c0 681 >; 682 }; 683 684 pinctrl_i2c1_gpio: i2c1-gpio-grp { 685 fsl,pins = < 686 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0xc0 687 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0xc0 688 >; 689 }; 690 691 pinctrl_i2c2: i2c2-grp { 692 fsl,pins = < 693 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c0 694 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c0 695 >; 696 }; 697 698 pinctrl_i2c2_gpio: i2c2-gpio-grp { 699 fsl,pins = < 700 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0xc0 701 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0xc0 702 >; 703 }; 704 705 pinctrl_i2c3: i2c3-grp { 706 fsl,pins = < 707 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 708 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 709 >; 710 }; 711 712 pinctrl_i2c3_gpio: i2c3-gpio-grp { 713 fsl,pins = < 714 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0xc2 715 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0xc2 716 >; 717 }; 718 719 pinctrl_i2c5: i2c5-grp { 720 fsl,pins = < 721 MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x400000c4 722 MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x400000c4 723 >; 724 }; 725 726 pinctrl_i2c5_gpio: i2c5-gpio-grp { 727 fsl,pins = < 728 MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0xc4 729 MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0xc4 730 >; 731 }; 732 733 pinctrl_nfc: nfc-grp { 734 fsl,pins = < 735 MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x40 /* NFC_INT_I */ 736 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x40 /* NFC_INT */ 737 >; 738 }; 739 740 pinctrl_pmic: pmic-grp { 741 fsl,pins = < 742 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40 /* #PMIC_INT */ 743 >; 744 }; 745 746 pinctrl_ptn5110: ptn5110-grp { 747 fsl,pins = < 748 MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c4 /* #USB-C_ALERT */ 749 >; 750 }; 751 752 pinctrl_pwm1: pwm1-grp { 753 fsl,pins = < 754 MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x116 755 >; 756 }; 757 758 pinctrl_pwm2: pwm2-grp { 759 fsl,pins = < 760 MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x116 /* EXT_PWM */ 761 >; 762 }; 763 764 pinctrl_reg_usdhc2_vmmc: reg-usdhc2-vmmc-grp { 765 fsl,pins = < 766 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 767 >; 768 }; 769 770 pinctrl_sbu_mux: sbu-mux-grp { 771 fsl,pins = < 772 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x16 /* #USB-C_SEL */ 773 MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x16 /* #USB-C_EN */ 774 >; 775 }; 776 777 pinctrl_slb9670: slb9670-grp { 778 fsl,pins = < 779 MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x40 /* #TPM_IRQ */ 780 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x40 /* #TPM_RES */ 781 >; 782 }; 783 784 pinctrl_uart2: uart2-grp { 785 fsl,pins = < 786 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 787 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 788 >; 789 }; 790 791 pinctrl_uart3: uart3-grp { 792 fsl,pins = < 793 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x40 794 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x40 795 >; 796 }; 797 798 pinctrl_uart4: uart4-grp { 799 fsl,pins = < 800 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x40 801 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x40 802 >; 803 }; 804 805 pinctrl_usb1: usb1-grp { 806 fsl,pins = < 807 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x40 /* USB_PWR */ 808 >; 809 }; 810 811 pinctrl_usdhc2: usdhc2-grp { 812 fsl,pins = < 813 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 814 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 815 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 816 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 817 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 818 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 819 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 /* SD2_VSEL */ 820 >; 821 }; 822 823 pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { 824 fsl,pins = < 825 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 826 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 827 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 828 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 829 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 830 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 831 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 /* SD2_VSEL */ 832 >; 833 }; 834 835 pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { 836 fsl,pins = < 837 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 838 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 839 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 840 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 841 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 842 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 843 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 /* SD2_VSEL */ 844 >; 845 }; 846 847 pinctrl_usdhc2_gpio: usdhc2-gpio-grp { 848 fsl,pins = < 849 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 850 >; 851 }; 852 853 pinctrl_usdhc3: usdhc3-grp { 854 fsl,pins = < 855 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 856 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 857 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 858 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 859 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 860 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 861 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 862 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 863 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 864 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 865 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 866 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x40 /* #SD3_RESET */ 867 >; 868 }; 869 870 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { 871 fsl,pins = < 872 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 873 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 874 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 875 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 876 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 877 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 878 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 879 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 880 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 881 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 882 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 883 >; 884 }; 885 886 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { 887 fsl,pins = < 888 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x192 889 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d2 890 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2 891 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2 892 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2 893 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2 894 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2 895 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2 896 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2 897 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2 898 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x192 899 >; 900 }; 901 902 pinctrl_wdog: wdog-grp { 903 fsl,pins = < 904 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 /* #WDOG */ 905 >; 906 }; 907}; 908