1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2025 Josua Mayer <josua@solid-run.com> 4 */ 5 6#include "imx8mp.dtsi" 7 8/ { 9 model = "SolidRun i.MX8MP SoM"; 10 compatible = "solidrun,imx8mp-sr-som", "fsl,imx8mp"; 11 12 chosen { 13 bootargs = "earlycon=ec_imx6q,0x30890000,115200"; 14 stdout-path = &uart2; 15 }; 16 17 memory@40000000 { 18 device_type = "memory"; 19 reg = <0x0 0x40000000 0 0xc0000000>, 20 <0x1 0x00000000 0 0xc0000000>; 21 }; 22 23 usdhc1_pwrseq: usdhc1-pwrseq { 24 compatible = "mmc-pwrseq-simple"; 25 reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; 26 }; 27 28 v_1_8: regulator-1-8 { 29 compatible = "regulator-fixed"; 30 regulator-name = "1v8"; 31 regulator-min-microvolt = <1800000>; 32 regulator-max-microvolt = <1800000>; 33 }; 34 35 v_3_3: regulator-3-3 { 36 compatible = "regulator-fixed"; 37 regulator-name = "3v3"; 38 regulator-min-microvolt = <3300000>; 39 regulator-max-microvolt = <3300000>; 40 }; 41}; 42 43/* 44 * Reserve all physical memory from within the first 1GB of DDR address 45 * space to avoid panic on low memory systems. 46 */ 47&dsp_reserved { 48 reg = <0 0x6f000000 0 0x1000000>; 49}; 50 51&eqos { 52 pinctrl-names = "default"; 53 pinctrl-0 = <&eqos_pins>, <&phy0_pins>; 54 phy-mode = "rgmii-id"; 55 phy = <&phy0>; 56 snps,force_thresh_dma_mode; 57 snps,mtl-tx-config = <&mtl_tx_setup>; 58 snps,mtl-rx-config = <&mtl_rx_setup>; 59 status = "okay"; 60 61 mdio { 62 compatible = "snps,dwmac-mdio"; 63 #address-cells = <1>; 64 #size-cells = <0>; 65 66 phy0: ethernet-phy@0 { 67 compatible = "ethernet-phy-ieee802.3-c22"; 68 reg = <0>; 69 reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; 70 interrupt-parent = <&gpio4>; 71 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 72 }; 73 }; 74 75 mtl_tx_setup: tx-queues-config { 76 snps,tx-queues-to-use = <5>; 77 78 queue0 { 79 snps,dcb-algorithm; 80 snps,priority = <0x1>; 81 }; 82 83 queue1 { 84 snps,dcb-algorithm; 85 snps,priority = <0x2>; 86 }; 87 88 queue2 { 89 snps,dcb-algorithm; 90 snps,priority = <0x4>; 91 }; 92 93 queue3 { 94 snps,dcb-algorithm; 95 snps,priority = <0x8>; 96 }; 97 98 queue4 { 99 snps,dcb-algorithm; 100 snps,priority = <0xf0>; 101 }; 102 }; 103 104 mtl_rx_setup: rx-queues-config { 105 snps,rx-queues-to-use = <5>; 106 snps,rx-sched-sp; 107 108 queue0 { 109 snps,dcb-algorithm; 110 snps,priority = <0x1>; 111 snps,map-to-dma-channel = <0>; 112 }; 113 114 queue1 { 115 snps,dcb-algorithm; 116 snps,priority = <0x2>; 117 snps,map-to-dma-channel = <1>; 118 }; 119 120 queue2 { 121 snps,dcb-algorithm; 122 snps,priority = <0x4>; 123 snps,map-to-dma-channel = <2>; 124 }; 125 126 queue3 { 127 snps,dcb-algorithm; 128 snps,priority = <0x8>; 129 snps,map-to-dma-channel = <3>; 130 }; 131 132 queue4 { 133 snps,dcb-algorithm; 134 snps,priority = <0xf0>; 135 snps,map-to-dma-channel = <4>; 136 }; 137 }; 138}; 139 140&fec { 141 pinctrl-names = "default"; 142 pinctrl-0 = <&fec_pins>, <&phy1_pins>; 143 phy-mode = "rgmii-id"; 144 phy = <&phy1>; 145 fsl,magic-packet; 146 status = "okay"; 147 148 mdio { 149 #address-cells = <1>; 150 #size-cells = <0>; 151 152 phy1: ethernet-phy@1 { 153 compatible = "ethernet-phy-ieee802.3-c22"; 154 reg = <0x1>; 155 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; 156 interrupt-parent = <&gpio4>; 157 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 158 }; 159 }; 160}; 161 162&i2c1 { 163 clock-frequency = <400000>; 164 pinctrl-names = "default", "gpio"; 165 pinctrl-0 = <&i2c1_pins>; 166 pinctrl-1 = <&i2c1_gpio_pins>; 167 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 168 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 169 status = "okay"; 170 171 pmic: pmic@25 { 172 compatible = "nxp,pca9450c"; 173 reg = <0x25>; 174 pinctrl-0 = <&pmic_pins>; 175 pinctrl-names = "default"; 176 interrupt-parent = <&gpio1>; 177 interrupts = <3 GPIO_ACTIVE_LOW>; 178 nxp,i2c-lt-enable; 179 180 regulators { 181 buck1: BUCK1 { 182 regulator-name = "BUCK1"; 183 regulator-min-microvolt = <600000>; 184 regulator-max-microvolt = <2187500>; 185 regulator-boot-on; 186 regulator-always-on; 187 regulator-ramp-delay = <3125>; 188 }; 189 190 buck2: BUCK2 { 191 regulator-name = "BUCK2"; 192 regulator-min-microvolt = <600000>; 193 regulator-max-microvolt = <2187500>; 194 regulator-boot-on; 195 regulator-always-on; 196 regulator-ramp-delay = <3125>; 197 nxp,dvs-run-voltage = <950000>; 198 nxp,dvs-standby-voltage = <850000>; 199 }; 200 201 buck4: BUCK4{ 202 regulator-name = "BUCK4"; 203 regulator-min-microvolt = <600000>; 204 regulator-max-microvolt = <3400000>; 205 regulator-boot-on; 206 regulator-always-on; 207 }; 208 209 buck5: BUCK5{ 210 regulator-name = "BUCK5"; 211 regulator-min-microvolt = <600000>; 212 regulator-max-microvolt = <3400000>; 213 regulator-boot-on; 214 regulator-always-on; 215 }; 216 217 buck6: BUCK6 { 218 regulator-name = "BUCK6"; 219 regulator-min-microvolt = <600000>; 220 regulator-max-microvolt = <3400000>; 221 regulator-boot-on; 222 regulator-always-on; 223 }; 224 225 ldo1: LDO1 { 226 regulator-name = "LDO1"; 227 regulator-min-microvolt = <1600000>; 228 regulator-max-microvolt = <3300000>; 229 regulator-boot-on; 230 regulator-always-on; 231 }; 232 233 ldo2: LDO2 { 234 regulator-name = "LDO2"; 235 regulator-min-microvolt = <800000>; 236 regulator-max-microvolt = <1150000>; 237 regulator-boot-on; 238 regulator-always-on; 239 }; 240 241 ldo3: LDO3 { 242 regulator-name = "LDO3"; 243 regulator-min-microvolt = <800000>; 244 regulator-max-microvolt = <3300000>; 245 regulator-boot-on; 246 regulator-always-on; 247 }; 248 249 ldo4: LDO4 { 250 regulator-name = "LDO4"; 251 regulator-min-microvolt = <800000>; 252 regulator-max-microvolt = <3300000>; 253 regulator-boot-on; 254 regulator-always-on; 255 }; 256 257 ldo5: LDO5 { 258 regulator-name = "LDO5"; 259 regulator-min-microvolt = <1800000>; 260 regulator-max-microvolt = <3300000>; 261 regulator-boot-on; 262 regulator-always-on; 263 }; 264 }; 265 }; 266 267 som_eeprom: eeprom@50{ 268 compatible = "st,24c01", "atmel,24c01"; 269 reg = <0x50>; 270 pagesize = <16>; 271 }; 272}; 273 274&i2c2 { 275 clock-frequency = <100000>; 276 pinctrl-names = "default", "gpio"; 277 pinctrl-0 = <&i2c2_pins>; 278 pinctrl-1 = <&i2c2_gpio_pins>; 279 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 280 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 281 status = "okay"; 282}; 283 284&i2c3 { 285 clock-frequency = <100000>; 286 pinctrl-names = "default", "gpio"; 287 pinctrl-0 = <&i2c3_pins>; 288 pinctrl-1 = <&i2c3_gpio_pins>; 289 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 290 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 291 status = "okay"; 292}; 293 294&i2c4 { 295 /* routed to basler camera connector */ 296 clock-frequency = <100000>; 297 pinctrl-names = "default", "gpio"; 298 pinctrl-0 = <&i2c4_pins>; 299 pinctrl-1 = <&i2c4_gpio_pins>; 300 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 301 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 302 status = "okay"; 303}; 304 305&iomuxc { 306 eqos_pins: pinctrl-eqos-grp { 307 fsl,pins = < 308 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 309 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 310 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 311 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 312 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 313 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 314 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 315 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 316 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f 317 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f 318 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f 319 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f 320 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f 321 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f 322 >; 323 }; 324 325 fec_pins: pinctrl-fec-grp { 326 fsl,pins = < 327 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 328 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 329 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 330 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 331 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 332 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 333 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 334 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 335 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f 336 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f 337 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f 338 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f 339 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f 340 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f 341 >; 342 }; 343 344 i2c1_pins: pinctrl-i2c1-grp { 345 fsl,pins = < 346 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 347 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 348 >; 349 }; 350 351 i2c1_gpio_pins: pinctrl-i2c1-gpio-grp { 352 fsl,pins = < 353 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c3 354 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c3 355 >; 356 }; 357 358 i2c2_pins: pinctrl-i2c2-grp { 359 fsl,pins = < 360 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 361 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 362 >; 363 }; 364 365 i2c2_gpio_pins: pinctrl-i2c2-gpio-grp { 366 fsl,pins = < 367 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c3 368 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c3 369 >; 370 }; 371 372 i2c3_pins: pinctrl-i2c3-grp { 373 fsl,pins = < 374 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 375 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 376 >; 377 }; 378 379 i2c3_gpio_pins: pinctrl-i2c3-gpio-grp { 380 fsl,pins = < 381 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c3 382 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c3 383 >; 384 }; 385 386 i2c4_pins: pinctrl-i2c4-grp { 387 fsl,pins = < 388 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 389 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 390 >; 391 }; 392 393 i2c4_gpio_pins: pinctrl-i2c4-gpio-grp { 394 fsl,pins = < 395 MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c3 396 MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c3 397 >; 398 }; 399 400 phy0_pins: pinctrl-phy0-grp { 401 fsl,pins = < 402 /* RESET_N: weak i/o, open drain, external 1k pull-up */ 403 MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x20 404 /* INT_N: weak i/o, open drain, internal pull-up */ 405 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x160 406 >; 407 }; 408 409 phy1_pins: pinctrl-phy-1-grp { 410 fsl,pins = < 411 /* RESET_N: weak i/o, open drain, external 1k pull-up */ 412 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x20 413 /* INT_N: weak i/o, open drain, internal pull-up */ 414 MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x160 415 >; 416 }; 417 418 pmic_pins: pinctrl-pmic-grp { 419 fsl,pins = < 420 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 421 >; 422 }; 423 424 uart1_pins: pinctrl-uart1-grp { 425 fsl,pins = < 426 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 427 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 428 MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 429 MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 430 /* BT_REG_ON */ 431 MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x0 432 /* BT_WAKE_DEV */ 433 MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x0 434 /* BT_WAKE_HOST */ 435 MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x100 436 >; 437 }; 438 439 uart2_pins: pinctrl-uart2-grp { 440 fsl,pins = < 441 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 442 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 443 >; 444 }; 445 446 usdhc1_pins: pinctrl-usdhc1-grp { 447 fsl,pins = < 448 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 449 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 450 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 451 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 452 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 453 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 454 /* WL_REG_ON */ 455 MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x0 456 /* WL_WAKE_HOST */ 457 MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x100 458 >; 459 }; 460 461 usdhc1_100mhz_pins: pinctrl-usdhc1g-100mhz-grp { 462 fsl,pins = < 463 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 464 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 465 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 466 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 467 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 468 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 469 >; 470 }; 471 472 usdhc1_200mhz_pins: pinctrl-usdhc1-200mhz-grp { 473 fsl,pins = < 474 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 475 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 476 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 477 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 478 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 479 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 480 >; 481 }; 482 483 usdhc3_pins: pinctrl-usdhc3-grp { 484 fsl,pins = < 485 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 486 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 487 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 488 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 489 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 490 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 491 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 492 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 493 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 494 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 495 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 496 >; 497 }; 498 499 usdhc3_100mhz_pins: pinctrl-usdhc3-100mhz-grp { 500 fsl,pins = < 501 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 502 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 503 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 504 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 505 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 506 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 507 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 508 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 509 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 510 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 511 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 512 >; 513 }; 514 515 usdhc3_200mhz_pins: pinctrl-usdhc3-200mhz-grp { 516 fsl,pins = < 517 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 518 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 519 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 520 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 521 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 522 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 523 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 524 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 525 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 526 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 527 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 528 >; 529 }; 530 531 wdog1_pins: pinctrl-wdog1-grp { 532 fsl,pins = < 533 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x140 534 >; 535 }; 536}; 537 538&uart1 { 539 pinctrl-names = "default"; 540 pinctrl-0 = <&uart1_pins>; 541 uart-has-rtscts; 542 /* select 80MHz parent clock to support maximum baudrate 4Mbps */ 543 assigned-clocks = <&clk IMX8MP_CLK_UART1>; 544 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 545 status = "okay"; 546 547 bluetooth { 548 compatible = "brcm,bcm4345c5"; 549 device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; 550 host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; 551 shutdown-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; 552 /* Murata 1MW module supports max. 3M baud */ 553 max-speed = <3000000>; 554 }; 555}; 556 557&uart2 { 558 pinctrl-names = "default"; 559 pinctrl-0 = <&uart2_pins>; 560 status = "okay"; 561}; 562 563&usdhc1 { 564 pinctrl-names = "default"; 565 pinctrl-0 = <&usdhc1_pins>; 566 pinctrl-1 = <&usdhc1_100mhz_pins>; 567 pinctrl-2 = <&usdhc1_200mhz_pins>; 568 vmmc-supply = <&v_3_3>; 569 vqmmc-supply = <&v_1_8>; 570 bus-width = <4>; 571 mmc-pwrseq = <&usdhc1_pwrseq>; 572 status = "okay"; 573}; 574 575&usdhc3 { 576 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 577 pinctrl-0 = <&usdhc3_pins>; 578 pinctrl-1 = <&usdhc3_100mhz_pins>; 579 pinctrl-2 = <&usdhc3_200mhz_pins>; 580 vmmc-supply = <&v_3_3>; 581 vqmmc-supply = <&v_1_8>; 582 bus-width = <8>; 583 non-removable; 584 status = "okay"; 585}; 586 587&wdog1 { 588 pinctrl-names = "default"; 589 pinctrl-0 = <&wdog1_pins>; 590 status = "okay"; 591}; 592