1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright 2020 Protonic Holland 4 * Copyright 2019 NXP 5 */ 6 7/dts-v1/; 8 9#include "imx8mp.dtsi" 10 11/ { 12 model = "Protonic PRT8ML"; 13 compatible = "prt,prt8ml", "fsl,imx8mp"; 14 15 chosen { 16 stdout-path = &uart4; 17 }; 18 19 pcie_refclk: pcie0-refclk { 20 compatible = "fixed-clock"; 21 #clock-cells = <0>; 22 clock-frequency = <100000000>; 23 }; 24 25 pcie_refclk_oe: pcie0-refclk-oe { 26 compatible = "gpio-gate-clock"; 27 pinctrl-names = "default"; 28 pinctrl-0 = <&pinctrl_pcie_refclk>; 29 clocks = <&pcie_refclk>; 30 #clock-cells = <0>; 31 enable-gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; 32 }; 33}; 34 35&A53_0 { 36 cpu-supply = <&fan53555>; 37}; 38 39&A53_1 { 40 cpu-supply = <&fan53555>; 41}; 42 43&A53_2 { 44 cpu-supply = <&fan53555>; 45}; 46 47&A53_3 { 48 cpu-supply = <&fan53555>; 49}; 50 51&a53_opp_table { 52 opp-1200000000 { 53 opp-microvolt = <900000>; 54 }; 55 56 opp-1600000000 { 57 opp-microvolt = <980000>; 58 }; 59 60 /* Power supply insuffient for 1.8 GHz */ 61 /delete-node/ opp-1800000000; 62}; 63 64&ecspi2 { 65 pinctrl-names = "default"; 66 pinctrl-0 = <&pinctrl_ecspi2>; 67 cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>; 68 69 /* Disable DMA to meet performance requirements */ 70 /delete-property/ dmas; 71 /delete-property/ dma-names; 72 status = "okay"; 73 74 switch@0 { 75 compatible = "nxp,sja1105q"; 76 reg = <0>; 77 reset-gpios = <&gpio_exp_1 4 GPIO_ACTIVE_LOW>; 78 spi-cpha; 79 spi-max-frequency = <4000000>; 80 spi-rx-delay-us = <1>; 81 spi-tx-delay-us = <1>; 82 83 ports { 84 #address-cells = <1>; 85 #size-cells = <0>; 86 87 port@3 { 88 reg = <3>; 89 label = "rj45"; 90 phy-handle = <&rj45_phy>; 91 phy-mode = "rgmii-id"; 92 }; 93 94 port@4 { 95 reg = <4>; 96 ethernet = <&fec>; 97 label = "cpu"; 98 phy-mode = "rgmii-id"; 99 rx-internal-delay-ps = <2000>; 100 tx-internal-delay-ps = <2000>; 101 102 /* Unreliable at 1000Mbps, limit RGMII to 100Mbps */ 103 fixed-link { 104 full-duplex; 105 speed = <100>; 106 }; 107 }; 108 }; 109 }; 110}; 111 112&fec { 113 pinctrl-names = "default"; 114 pinctrl-0 = <&pinctrl_fec>; 115 phy-mode = "rgmii"; /* switch inserts delay */ 116 rx-internal-delay-ps = <0>; 117 tx-internal-delay-ps = <0>; 118 status = "okay"; 119 120 fixed-link { 121 full-duplex; 122 speed = <100>; 123 }; 124 125 mdio { 126 #address-cells = <1>; 127 #size-cells = <0>; 128 129 rj45_phy: ethernet-phy@2 { 130 reg = <2>; 131 reset-gpios = <&gpio_exp_1 1 GPIO_ACTIVE_LOW>; 132 reset-assert-us = <10000>; 133 reset-deassert-us = <80000>; 134 }; 135 }; 136}; 137 138&flexcan1 { 139 pinctrl-names = "default"; 140 pinctrl-0 = <&pinctrl_flexcan1>; 141 status = "okay"; 142}; 143 144&flexcan2 { 145 pinctrl-names = "default"; 146 pinctrl-0 = <&pinctrl_flexcan2>; 147 status = "okay"; 148}; 149 150&i2c1 { 151 clock-frequency = <400000>; 152 pinctrl-names = "default"; 153 pinctrl-0 = <&pinctrl_i2c1>; 154 status = "okay"; 155 156 ak5558: codec@10 { 157 compatible = "asahi-kasei,ak5558"; 158 reg = <0x10>; 159 reset-gpios = <&gpio_exp_1 2 GPIO_ACTIVE_LOW>; 160 }; 161 162 gpio_exp_1: gpio@25 { 163 compatible = "nxp,pca9571"; 164 reg = <0x25>; 165 gpio-controller; 166 #gpio-cells = <2>; 167 }; 168}; 169 170&i2c2 { 171 clock-frequency = <400000>; 172 pinctrl-names = "default"; 173 pinctrl-0 = <&pinctrl_i2c2>; 174 status = "okay"; 175 176 tps65987ddh_0: usb-pd@20 { 177 compatible = "ti,tps6598x"; 178 reg = <0x20>; 179 pinctrl-names = "default"; 180 pinctrl-0 = <&pinctrl_tps65987ddh_0>; 181 interrupts-extended = <&gpio1 12 IRQ_TYPE_LEVEL_LOW>; 182 }; 183 184 gpio_exp_2: gpio@25 { 185 compatible = "nxp,pca9571"; 186 reg = <0x25>; 187 gpio-controller; 188 #gpio-cells = <2>; 189 190 c0-hreset-hog { 191 gpio-hog; 192 gpios = <7 GPIO_ACTIVE_LOW>; 193 line-name = "c0-hreset"; 194 output-low; 195 }; 196 197 c1-hreset-hog { 198 gpio-hog; 199 gpios = <6 GPIO_ACTIVE_LOW>; 200 line-name = "c1-hreset"; 201 output-low; 202 }; 203 }; 204 205 fan53555: regulator@60 { 206 compatible = "fcs,fan53555"; 207 reg = <0x60>; 208 pinctrl-names = "default"; 209 pinctrl-0 = <&pinctrl_fan53555>; 210 regulator-name = "fan53555"; 211 regulator-min-microvolt = <900000>; 212 regulator-max-microvolt = <980000>; 213 regulator-always-on; 214 regulator-boot-on; 215 fcs,suspend-voltage-selector = <1>; 216 }; 217}; 218 219&i2c3 { 220 clock-frequency = <400000>; 221 pinctrl-names = "default"; 222 pinctrl-0 = <&pinctrl_i2c3>; 223 status = "okay"; 224 225 ak4458: codec@11 { 226 compatible = "asahi-kasei,ak4458"; 227 reg = <0x11>; 228 #sound-dai-cells = <0>; 229 reset-gpios = <&gpio_exp_2 5 GPIO_ACTIVE_LOW>; 230 }; 231 232 tps65987ddh_1: usb-pd@20 { 233 compatible = "ti,tps6598x"; 234 reg = <0x20>; 235 pinctrl-names = "default"; 236 pinctrl-0 = <&pinctrl_tps65987ddh_1>; 237 interrupts-extended = <&gpio1 15 IRQ_TYPE_LEVEL_LOW>; 238 }; 239}; 240 241&lcdif1 { 242 status = "okay"; 243}; 244 245&snvs_pwrkey { 246 status = "okay"; 247}; 248 249&uart4 { 250 pinctrl-names = "default"; 251 pinctrl-0 = <&pinctrl_uart4>; 252 status = "okay"; 253}; 254 255&usb3_0 { 256 status = "okay"; 257}; 258 259&usb3_1 { 260 status = "okay"; 261}; 262 263&usb3_phy0 { 264 status = "okay"; 265}; 266 267&usb3_phy1 { 268 status = "okay"; 269}; 270 271&usb_dwc3_0 { 272 dr_mode = "host"; 273 status = "okay"; 274}; 275 276&usb_dwc3_1 { 277 dr_mode = "host"; 278 status = "okay"; 279}; 280 281&usdhc2 { 282 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 283 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 284 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 285 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 286 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; 287 assigned-clock-rates = <100000000>; 288 bus-width = <4>; 289 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 290 no-1-8-v; 291 sd-uhs-sdr12; 292 sd-uhs-sdr25; 293 status = "okay"; 294}; 295 296&usdhc3 { 297 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 298 pinctrl-0 = <&pinctrl_usdhc3>; 299 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 300 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 301 assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>; 302 assigned-clock-rates = <400000000>; 303 bus-width = <8>; 304 non-removable; 305 no-sdio; 306 no-sd; 307 status = "okay"; 308}; 309 310&wdog1 { 311 pinctrl-names = "default"; 312 pinctrl-0 = <&pinctrl_wdog>; 313 fsl,ext-reset-output; 314 status = "okay"; 315}; 316 317&iomuxc { 318 pinctrl_ecspi2: ecspi2grp { 319 fsl,pins = < 320 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x154 321 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x154 322 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x154 323 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x154 324 >; 325 }; 326 327 pinctrl_fan53555: fan53555grp { 328 fsl,pins = < 329 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x114 330 >; 331 }; 332 333 pinctrl_fec: fecgrp { 334 fsl,pins = < 335 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 336 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 337 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 338 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 339 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 340 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 341 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 342 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 343 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f 344 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f 345 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f 346 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f 347 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f 348 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f 349 >; 350 }; 351 352 pinctrl_flexcan1: flexcan1grp { 353 fsl,pins = < 354 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 355 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 356 >; 357 }; 358 359 pinctrl_flexcan2: flexcan2grp { 360 fsl,pins = < 361 MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x154 362 MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x154 363 >; 364 }; 365 366 pinctrl_i2c1: i2c1grp { 367 fsl,pins = < 368 MX8MP_IOMUXC_ECSPI1_SCLK__I2C1_SCL 0x400000c3 369 MX8MP_IOMUXC_ECSPI1_MOSI__I2C1_SDA 0x400000c3 370 >; 371 }; 372 373 pinctrl_i2c2: i2c2grp { 374 fsl,pins = < 375 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400000c3 376 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400000c3 377 >; 378 }; 379 380 pinctrl_i2c3: i2c3grp { 381 fsl,pins = < 382 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400000c3 383 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400000c3 384 >; 385 }; 386 387 pinctrl_pcie_refclk: pcierefclkgrp { 388 fsl,pins = < 389 MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0xc6 390 >; 391 }; 392 393 pinctrl_tps65987ddh_0: tps65987ddh-0grp { 394 fsl,pins = < 395 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x1d0 396 >; 397 }; 398 399 pinctrl_tps65987ddh_1: tps65987ddh-1grp { 400 fsl,pins = < 401 MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1d0 402 >; 403 }; 404 405 pinctrl_uart4: uart4grp { 406 fsl,pins = < 407 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x040 408 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x040 409 >; 410 }; 411 412 pinctrl_usdhc2: usdhc2grp { 413 fsl,pins = < 414 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 415 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 416 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 417 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 418 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 419 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 420 >; 421 }; 422 423 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 424 fsl,pins = < 425 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 426 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 427 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 428 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 429 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 430 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 431 >; 432 }; 433 434 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 435 fsl,pins = < 436 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 437 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 438 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 439 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 440 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 441 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 442 >; 443 }; 444 445 pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 446 fsl,pins = < 447 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0d4 448 >; 449 }; 450 451 pinctrl_usdhc3: usdhc3grp { 452 fsl,pins = < 453 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 454 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 455 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 456 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 457 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 458 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 459 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 460 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 461 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 462 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 463 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 464 >; 465 }; 466 467 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 468 fsl,pins = < 469 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 470 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 471 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 472 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 473 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 474 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 475 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 476 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 477 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 478 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 479 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 480 >; 481 }; 482 483 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 484 fsl,pins = < 485 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 486 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 487 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 488 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 489 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 490 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 491 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 492 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 493 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 494 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 495 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 496 >; 497 }; 498 499 pinctrl_wdog: wdoggrp { 500 fsl,pins = < 501 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 502 >; 503 }; 504}; 505