1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2025 Josua Mayer <josua@solid-run.com> 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/phy/phy-imx8-pcie.h> 9 10#include "imx8mp-sr-som.dtsi" 11#include "imx8mp-hummingboard-pulse-codec.dtsi" 12#include "imx8mp-hummingboard-pulse-common.dtsi" 13#include "imx8mp-hummingboard-pulse-hdmi.dtsi" 14#include "imx8mp-hummingboard-pulse-m2con.dtsi" 15#include "imx8mp-hummingboard-pulse-mini-hdmi.dtsi" 16 17/ { 18 model = "SolidRun i.MX8MP HummingBoard Pulse"; 19 compatible = "solidrun,imx8mp-hummingboard-pulse", 20 "solidrun,imx8mp-sr-som", "fsl,imx8mp"; 21 22 aliases { 23 ethernet0 = &eqos; 24 ethernet1 = &pcie_eth; 25 }; 26}; 27 28&fec { 29 /* this board does not use second phy / ethernet on SoM */ 30 status = "disabled"; 31}; 32 33&gpio1 { 34 pinctrl-0 = <&mpcie_reset_pins>, <&m2_reset_pins>; 35 pinctrl-names = "default"; 36 37 m2-reset-hog { 38 gpio-hog; 39 gpios = <6 GPIO_ACTIVE_LOW>; 40 output-low; 41 line-name = "m2-reset"; 42 }; 43}; 44 45&iomuxc { 46 pinctrl-names = "default"; 47 pinctrl-0 = <&mikro_pwm_pins>, <&mikro_int_pins>, <&hdmi_pins>, 48 <&m2_wwan_wake_pins>; 49 50 pcie_eth_pins: pinctrl-pcie-eth-grp { 51 fsl,pins = < 52 MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x0 53 >; 54 }; 55}; 56 57&pcie { 58 pinctrl-0 = <&pcie_eth_pins>; 59 pinctrl-names = "default"; 60 reset-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>; 61 status = "okay"; 62 63 root@0,0 { 64 compatible = "pci16c3,abcd"; 65 reg = <0x00000000 0 0 0 0>; 66 #address-cells = <3>; 67 #size-cells = <2>; 68 69 /* Intel i210 */ 70 pcie_eth: ethernet@1,0 { 71 compatible = "pci8086,157b"; 72 reg = <0x00010000 0 0 0 0>; 73 }; 74 }; 75}; 76 77&pcie_phy { 78 clocks = <&hsio_blk_ctrl>; 79 clock-names = "ref"; 80 fsl,clkreq-unsupported; 81 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 82 status = "okay"; 83}; 84