1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2024 Yazan Shhady <yazan.shhady@solid-run.com> 4 * Copyright 2025 Josua Mayer <josua@solid-run.com> 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/leds/common.h> 10#include <dt-bindings/phy/phy-imx8-pcie.h> 11 12#include "imx8mp-sr-som.dtsi" 13 14/ { 15 compatible = "solidrun,imx8mp-hummingboard-iiot", 16 "solidrun,imx8mp-sr-som", "fsl,imx8mp"; 17 model = "SolidRun i.MX8MP HummingBoard IIoT"; 18 19 /* power for M.2 B-Key connector (J6) */ 20 regulator-m2-b { 21 compatible = "regulator-fixed"; 22 regulator-name = "m2-b"; 23 gpios = <&tca6416_u20 5 GPIO_ACTIVE_HIGH>; 24 regulator-always-on; 25 regulator-max-microvolt = <3300000>; 26 regulator-min-microvolt = <3300000>; 27 enable-active-high; 28 }; 29 30 /* power for M.2 M-Key connector (J4) */ 31 regulator-m2-m { 32 compatible = "regulator-fixed"; 33 regulator-name = "m2-m"; 34 gpios = <&tca6416_u20 6 GPIO_ACTIVE_HIGH>; 35 regulator-always-on; 36 regulator-max-microvolt = <3300000>; 37 regulator-min-microvolt = <3300000>; 38 enable-active-high; 39 }; 40 41 /* power for USB-A J27 behind USB Hub Port 3 */ 42 regulator-vbus-2 { 43 compatible = "regulator-fixed"; 44 regulator-name = "vbus2"; 45 regulator-always-on; 46 regulator-max-microvolt = <5000000>; 47 regulator-min-microvolt = <5000000>; 48 gpio = <&tca6416_u20 12 GPIO_ACTIVE_HIGH>; 49 enable-active-high; 50 }; 51 52 /* power for USB-A J27 behind USB Hub Port 4 */ 53 regulator-vbus-3 { 54 compatible = "regulator-fixed"; 55 regulator-name = "vbus3"; 56 regulator-always-on; 57 regulator-max-microvolt = <5000000>; 58 regulator-min-microvolt = <5000000>; 59 gpio = <&tca6416_u20 13 GPIO_ACTIVE_HIGH>; 60 enable-active-high; 61 }; 62 63 aliases { 64 /* J10 */ 65 ethernet0 = &eqos; 66 /* J11 */ 67 ethernet1 = &fec; 68 gpio5 = &tca6408_u48; 69 gpio6 = &tca6408_u37; 70 gpio7 = &tca6416_u20; 71 gpio8 = &tca6416_u21; 72 i2c6 = &i2c_exp; 73 i2c7 = &i2c_csi; 74 i2c8 = &i2c_dsi; 75 i2c9 = &i2c_lvds; 76 rtc0 = &carrier_rtc; 77 rtc1 = &snvs_rtc; 78 }; 79 80 gpio-keys { 81 compatible = "gpio-keys"; 82 83 wakeup-event { 84 interrupts-extended = <&tca6416_u21 11 IRQ_TYPE_EDGE_FALLING>; 85 label = "m2-m-wakeup"; 86 wakeup-source; 87 linux,code = <KEY_WAKEUP>; 88 }; 89 }; 90 91 can_mux: mux-controller-0 { 92 compatible = "gpio-mux"; 93 /* 94 * Mux routes CAN bus signals between SoM connector pins, 95 * expansion connector (J22) and on-board transceivers using 96 * two GPIO: 97 * - IO3: 0 = on-board transceivers, 1 = expansion connector 98 * - IO4: 0 = J9-55/57/59/61, 1 = J7-12/16 & J9-54/56 99 */ 100 mux-gpios = <&tca6416_u20 3 GPIO_ACTIVE_HIGH>, 101 <&tca6416_u20 4 GPIO_ACTIVE_HIGH>; 102 /* default J7-12/16 & J9-54/56 to on-board transceivers */ 103 idle-state = <2>; 104 #mux-control-cells = <0>; 105 }; 106 107 spi_mux: mux-controller-1 { 108 compatible = "gpio-mux"; 109 /* default on-board */ 110 idle-state = <0>; 111 /* 112 * Mux switches spi bus between on-board tpm 113 * and expansion connector (J22). 114 */ 115 mux-gpios = <&tca6416_u21 0 GPIO_ACTIVE_HIGH>; 116 #mux-control-cells = <0>; 117 }; 118 119 uart3_uart4_b2b_mux: mux-controller-2 { 120 compatible = "gpio-mux"; 121 /* default on-board */ 122 idle-state = <0>; 123 /* 124 * Mux switches both uart3 and uart4 tx/rx between expansion 125 * connector (J22) and on-board rs232/rs485 transceivers 126 * using one GPIO: 0 = on-board, 1 = connector. 127 */ 128 mux-gpios = <&tca6416_u20 0 GPIO_ACTIVE_HIGH>; 129 #mux-control-cells = <0>; 130 }; 131 132 uart3_rs_232_485_mux: mux-controller-3 { 133 compatible = "gpio-mux"; 134 /* default rs232 */ 135 idle-state = <0>; 136 /* 137 * Mux switches uart3 tx/rx between rs232 and rs485 138 * transceivers. using one GPIO: 0 = rs232, 1 = rs485. 139 */ 140 mux-gpios = <&tca6416_u20 1 GPIO_ACTIVE_HIGH>; 141 #mux-control-cells = <0>; 142 }; 143 144 uart4_rs_232_485_mux: mux-controller-4 { 145 compatible = "gpio-mux"; 146 /* default rs232 */ 147 idle-state = <0>; 148 /* 149 * Mux switches uart4 tx/rx between rs232 and rs485 150 * transceivers. using one GPIO: 0 = rs232, 1 = rs485. 151 */ 152 mux-gpios = <&tca6416_u20 2 GPIO_ACTIVE_HIGH>; 153 #mux-control-cells = <0>; 154 }; 155 156 v_1_2: regulator-1-2 { 157 compatible = "regulator-fixed"; 158 regulator-name = "1v2"; 159 regulator-max-microvolt = <1800000>; 160 regulator-min-microvolt = <1800000>; 161 }; 162 163 reg_dsi_panel: regulator-dsi-panel { 164 compatible = "regulator-fixed"; 165 regulator-name = "dsi-panel"; 166 gpios = <&tca6416_u20 15 GPIO_ACTIVE_HIGH>; 167 regulator-max-microvolt = <11200000>; 168 regulator-min-microvolt = <11200000>; 169 enable-active-high; 170 }; 171 172 vmmc: regulator-mmc { 173 compatible = "regulator-fixed"; 174 regulator-name = "vmmc"; 175 pinctrl-0 = <&vmmc_pins>; 176 pinctrl-names = "default"; 177 regulator-max-microvolt = <3300000>; 178 regulator-min-microvolt = <3300000>; 179 startup-delay-us = <250>; 180 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 181 enable-active-high; 182 }; 183 184 /* power for USB-A J5003 */ 185 vbus1: regulator-vbus-1 { 186 compatible = "regulator-fixed"; 187 regulator-name = "vbus1"; 188 regulator-max-microvolt = <5000000>; 189 regulator-min-microvolt = <5000000>; 190 gpio = <&tca6416_u20 14 GPIO_ACTIVE_HIGH>; 191 enable-active-high; 192 }; 193 194 rfkill-m2-b-gnss { 195 compatible = "rfkill-gpio"; 196 /* rfkill-gpio inverts internally */ 197 shutdown-gpios = <&tca6416_u20 10 GPIO_ACTIVE_HIGH>; 198 label = "m2-b gnss"; 199 radio-type = "gps"; 200 }; 201 202 rfkill-m2-b-wwan { 203 compatible = "rfkill-gpio"; 204 /* rfkill-gpio inverts internally */ 205 shutdown-gpios = <&tca6416_u20 9 GPIO_ACTIVE_HIGH>; 206 label = "m2-b radio"; 207 radio-type = "wwan"; 208 }; 209}; 210 211&ecspi2 { 212 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 213 num-cs = <1>; 214 pinctrl-0 = <&ecspi2_pins>; 215 pinctrl-names = "default"; 216 status = "okay"; 217 218 ecspi2_muxed: spi@0 { 219 compatible = "spi-mux"; 220 reg = <0>; 221 #address-cells = <1>; 222 #size-cells = <0>; 223 mux-controls = <&spi_mux>; 224 /* mux bandwidth is 2GHz, soc max. spi clock is 166MHz */ 225 spi-max-frequency = <166000000>; 226 227 tpm@0 { 228 compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; 229 reg = <0>; 230 interrupts-extended = <&tca6416_u21 9 IRQ_TYPE_LEVEL_LOW>; 231 reset-gpios = <&tca6416_u21 1 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; 232 spi-max-frequency = <43000000>; 233 }; 234 }; 235}; 236 237&flexcan1 { 238 pinctrl-0 = <&can1_pins>; 239 pinctrl-names = "default"; 240 status = "okay"; 241 242 can-transceiver { 243 max-bitrate = <8000000>; 244 }; 245}; 246 247&flexcan2 { 248 pinctrl-0 = <&can2_pins>; 249 pinctrl-names = "default"; 250 status = "okay"; 251 252 can-transceiver { 253 max-bitrate = <8000000>; 254 }; 255}; 256 257&i2c2 { 258 i2c-mux@70 { 259 compatible = "nxp,pca9546"; 260 reg = <0x70>; 261 #address-cells = <1>; 262 #size-cells = <0>; 263 /* 264 * This reset is open drain, 265 * but reset core does not support GPIO_OPEN_DRAIN flag. 266 */ 267 reset-gpios = <&tca6416_u21 2 GPIO_ACTIVE_LOW>; 268 269 /* channel 0 routed to expansion connector (J22) */ 270 i2c_exp: i2c@0 { 271 reg = <0>; 272 #address-cells = <1>; 273 #size-cells = <0>; 274 }; 275 276 /* channel 1 routed to mipi-csi connector (J23) */ 277 i2c_csi: i2c@1 { 278 reg = <1>; 279 #address-cells = <1>; 280 #size-cells = <0>; 281 }; 282 283 /* channel 2 routed to mipi-dsi connector (J25) */ 284 i2c_dsi: i2c@2 { 285 reg = <2>; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 289 tca6408_u48: gpio@21 { 290 compatible = "ti,tca6408"; 291 reg = <0x21>; 292 #gpio-cells = <2>; 293 gpio-controller; 294 gpio-line-names = "CAM_RST#", "DSI_RESET", 295 "DSI_STBYB", "DSI_PWM_BL", 296 "DSI_L/R", "DSI_U/D", 297 "DSI_CTP_/RST", "CAM_TRIG"; 298 /* 299 * reset shared between U37 and U48, to be 300 * supported once gpio-pca953x switches to 301 * reset framework. 302 * 303 * reset-gpios = <&tca6416_u21 4 304 * (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>; 305 */ 306 }; 307 308 }; 309 310 /* channel 2 routed to lvds connector (J24) */ 311 i2c_lvds: i2c@3 { 312 reg = <3>; 313 #address-cells = <1>; 314 #size-cells = <0>; 315 316 tca6408_u37: gpio@20 { 317 compatible = "ti,tca6408"; 318 reg = <0x20>; 319 #gpio-cells = <2>; 320 gpio-controller; 321 gpio-line-names = "SELB", "LVDS_RESET", 322 "LVDS_STBYB", "LVDS_PWM_BL", 323 "LVDS_L/R", "LVDS_U/D", 324 "LVDS_CTP_/RST", ""; 325 /* 326 * reset shared between U37 and U48, to be 327 * supported once gpio-pca953x switches to 328 * reset framework. 329 * 330 * reset-gpios = <&tca6416_u21 4 331 * (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>; 332 */ 333 }; 334 335 }; 336 }; 337}; 338 339&i2c3 { 340 /* highest i2c clock supported by all peripherals is 400kHz */ 341 clock-frequency = <400000>; 342 343 tca6416_u20: gpio@20 { 344 reg = <0x20>; 345 #gpio-cells = <2>; 346 gpio-controller; 347 gpio-line-names = "TCA_INT/EXT_UART", "TCA_UARTA_232/485", 348 "TCA_UARTB_232/485", "TCA_INT/EXT_CAN", 349 "TCA_NXP/REN", "TCA_M.2B_3V3_EN", 350 "TCA_M.2M_3V3_EN", "TCA_M.2M_RESET#", 351 "TCA_M.2B_RESET#", "TCA_M.2B_W_DIS#", 352 "TCA_M.2B_GPS_EN#", "TCA_USB-HUB_RST#", 353 "TCA_USB_HUB3_PWR_EN", "TCA_USB_HUB4_PWR_EN", 354 "TCA_USB1_PWR_EN", "TCA_VIDEO_PWR_EN"; 355 /* 356 * This is a TI TCAL6416 using same programming model as 357 * NXP PCAL6416, not to be confused with TI TCA6416. 358 */ 359 compatible = "nxp,pcal6416"; 360 361 m2-b-reset-hog { 362 gpios = <8 GPIO_ACTIVE_LOW>; 363 gpio-hog; 364 line-name = "m2-b-reset"; 365 output-low; 366 }; 367 }; 368 369 tca6416_u21: gpio@21 { 370 reg = <0x21>; 371 #interrupt-cells = <2>; 372 interrupt-controller; 373 #gpio-cells = <2>; 374 gpio-controller; 375 gpio-line-names = "TCA_SPI_TPM/EXT", "TCA_TPM_RST#", 376 "TCA_I2C_RST", "TCA_RS232_SHTD#", 377 "TCA_LCD_I2C_RST", "TCA_DIG_OUT1", 378 "TCA_bDIG_IN1", "TCA_SENS_INT", 379 "TCA_ALERT#", "TCA_TPM_PIRQ#", 380 "TCA_RTC_INT", "TCA_M.2M_WAKW_ON_LAN", 381 "TCA_M.2M_CLKREQ#", "TCA_LVDS_INT#", 382 "", "TCA_POE_AT"; 383 interrupts-extended = <&gpio1 15 IRQ_TYPE_EDGE_FALLING>; 384 pinctrl-0 = <&tca6416_u21_int_pins>; 385 pinctrl-names = "default"; 386 /* 387 * This is a TI TCAL6416 using same programming model as 388 * NXP PCAL6416, not to be confused with TI TCA6416. 389 */ 390 compatible = "nxp,pcal6416"; 391 392 lcd-i2c-reset-hog { 393 gpios = <4 (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>; 394 line-name = "lcd-i2c-reset"; 395 output-low; 396 /* 397 * reset shared between U37 and U48, to be 398 * supported once gpio-pca953x switches to 399 * reset framework. 400 */ 401 gpio-hog; 402 }; 403 404 m2-m-clkreq-hog { 405 gpios = <12 GPIO_ACTIVE_LOW>; 406 gpio-hog; 407 input; 408 line-name = "m2-m-clkreq"; 409 }; 410 411 rs232_shutdown: rs232-shutdown-hog { 412 gpios = <3 GPIO_ACTIVE_LOW>; 413 gpio-hog; 414 line-name = "rs232-shutdown"; 415 output-low; 416 }; 417 }; 418 419 led-controller@30 { 420 compatible = "ti,lp5562"; 421 reg = <0x30>; 422 #address-cells = <1>; 423 #size-cells = <0>; 424 /* use internal clock, could use external generated by rtc */ 425 clock-mode = /bits/ 8 <1>; 426 427 multi-led@0 { 428 reg = <0x0>; 429 #address-cells = <1>; 430 #size-cells = <0>; 431 color = <LED_COLOR_ID_RGB>; 432 label = "D7"; 433 434 led@0 { 435 reg = <0x0>; 436 color = <LED_COLOR_ID_RED>; 437 led-cur = /bits/ 8 <0x32>; 438 max-cur = /bits/ 8 <0x64>; 439 }; 440 441 led@1 { 442 reg = <0x1>; 443 color = <LED_COLOR_ID_GREEN>; 444 led-cur = /bits/ 8 <0x19>; 445 max-cur = /bits/ 8 <0x32>; 446 }; 447 448 led@2 { 449 reg = <0x2>; 450 color = <LED_COLOR_ID_BLUE>; 451 led-cur = /bits/ 8 <0x19>; 452 max-cur = /bits/ 8 <0x32>; 453 }; 454 }; 455 456 led@3 { 457 reg = <0x3>; 458 chan-name = "D8"; 459 color = <LED_COLOR_ID_GREEN>; 460 label = "D8"; 461 led-cur = /bits/ 8 <0x19>; 462 max-cur = /bits/ 8 <0x64>; 463 }; 464 }; 465 466 light-sensor@44 { 467 compatible = "isil,isl29023"; 468 reg = <0x44>; 469 /* IRQ shared between accelerometer, light-sensor and Tamper input (J5007) */ 470 interrupts-extended = <&tca6416_u21 7 IRQ_TYPE_EDGE_FALLING>; 471 }; 472 473 accelerometer@53 { 474 compatible = "adi,adxl345"; 475 reg = <0x53>; 476 /* IRQ shared between accelerometer, light-sensor and Tamper input (J5007) */ 477 interrupts-extended = <&tca6416_u21 7 IRQ_TYPE_EDGE_FALLING>; 478 interrupt-names = "INT1"; 479 }; 480 481 carrier_eeprom: eeprom@57 { 482 compatible = "atmel,24c02"; 483 reg = <0x57>; 484 pagesize = <8>; 485 }; 486 487 carrier_rtc: rtc@69 { 488 compatible = "abracon,ab1805"; 489 reg = <0x69>; 490 abracon,tc-diode = "schottky"; 491 abracon,tc-resistor = <3>; 492 /* 493 * AM1805 RTC used on this board has only nTIRQ pins wired, 494 * which is for countdown timer irqs only. 495 * Driver does not support this, disable for now. 496 * 497 * interrupts-extended = <&tca6416_u21 10 IRQ_TYPE_EDGE_FALLING>; 498 */ 499 }; 500}; 501 502&iomuxc { 503 can1_pins: pinctrl-can1-grp { 504 fsl,pins = < 505 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 506 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 507 >; 508 }; 509 510 can2_pins: pinctrl-can2-grp { 511 fsl,pins = < 512 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 513 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 514 >; 515 }; 516 517 ecspi2_pins: pinctrl-ecspi2-grp { 518 fsl,pins = < 519 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 520 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 521 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 522 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 523 >; 524 }; 525 526 tca6416_u21_int_pins: pinctrl-tca6416-u21-int-grp { 527 fsl,pins = < 528 MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x0 529 >; 530 }; 531 532 /* UARTA */ 533 uart3_pins: pinctrl-uart3-grp { 534 fsl,pins = < 535 MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 536 MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 537 MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140 538 >; 539 }; 540 541 /* UARTB */ 542 uart4_pins: pinctrl-uart4-grp { 543 fsl,pins = < 544 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 545 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 546 MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x140 547 >; 548 }; 549 550 usdhc2_100mhz_pins: pinctrl-usdhc2-100mhz-grp { 551 fsl,pins = < 552 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 553 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 554 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 555 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 556 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 557 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 558 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140 559 MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140 560 >; 561 }; 562 563 usdhc2_200mhz_pins: pinctrl-usdhc2-200mhz-grp { 564 fsl,pins = < 565 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 566 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 567 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 568 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 569 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 570 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 571 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140 572 MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140 573 >; 574 }; 575 576 usdhc2_pins: pinctrl-usdhc2-grp { 577 fsl,pins = < 578 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 579 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 580 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 581 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 582 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 583 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 584 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140 585 MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140 586 >; 587 }; 588 589 vmmc_pins: pinctrl-vmmc-grp { 590 fsl,pins = < 591 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x0 592 >; 593 }; 594}; 595 596&pcie { 597 reset-gpio = <&tca6416_u20 7 GPIO_ACTIVE_LOW>; 598 status = "okay"; 599}; 600 601/* M.2 M-Key (J4) */ 602&pcie_phy { 603 clocks = <&hsio_blk_ctrl>; 604 clock-names = "ref"; 605 fsl,clkreq-unsupported; 606 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 607 status = "okay"; 608}; 609 610&phy0 { 611 leds { 612 #address-cells = <1>; 613 #size-cells = <0>; 614 615 /* ADIN1300 LED_0 pin */ 616 led@0 { 617 reg = <0>; 618 color = <LED_COLOR_ID_GREEN>; 619 default-state = "keep"; 620 function = LED_FUNCTION_LAN; 621 }; 622 }; 623}; 624 625&phy1 { 626 leds { 627 #address-cells = <1>; 628 #size-cells = <0>; 629 630 /* ADIN1300 LED_0 pin */ 631 led@0 { 632 reg = <0>; 633 color = <LED_COLOR_ID_GREEN>; 634 default-state = "keep"; 635 function = LED_FUNCTION_LAN; 636 }; 637 }; 638}; 639 640&uart3 { 641 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 642 /* select 80MHz parent clock to support maximum baudrate 4Mbps */ 643 assigned-clocks = <&clk IMX8MP_CLK_UART3>; 644 pinctrl-0 = <&uart3_pins>; 645 pinctrl-names = "default"; 646 rts-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; 647 status = "okay"; 648}; 649 650&uart4 { 651 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 652 /* select 80MHz parent clock to support maximum baudrate 4Mbps */ 653 assigned-clocks = <&clk IMX8MP_CLK_UART4>; 654 pinctrl-0 = <&uart4_pins>; 655 pinctrl-names = "default"; 656 rts-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; 657 status = "okay"; 658}; 659 660&usb3_0 { 661 status = "okay"; 662}; 663 664&usb3_1 { 665 status = "okay"; 666}; 667 668&usb3_phy0 { 669 vbus-supply = <&vbus1>; 670 fsl,phy-tx-preemp-amp-tune-microamp = <1200>; 671 status = "okay"; 672}; 673 674&usb3_phy1 { 675 status = "okay"; 676}; 677 678&usb_dwc3_0 { 679 dr_mode = "host"; 680}; 681 682&usb_dwc3_1 { 683 #address-cells = <1>; 684 #size-cells = <0>; 685 dr_mode = "host"; 686 687 hub_2_0: hub@1 { 688 compatible = "usb4b4,6502", "usb4b4,6506"; 689 reg = <1>; 690 peer-hub = <&hub_3_0>; 691 reset-gpios = <&tca6416_u20 11 GPIO_ACTIVE_LOW>; 692 vdd2-supply = <&v_3_3>; 693 vdd-supply = <&v_1_2>; 694 }; 695 696 hub_3_0: hub@2 { 697 compatible = "usb4b4,6500", "usb4b4,6504"; 698 reg = <2>; 699 peer-hub = <&hub_2_0>; 700 reset-gpios = <&tca6416_u20 11 GPIO_ACTIVE_LOW>; 701 vdd2-supply = <&v_3_3>; 702 vdd-supply = <&v_1_2>; 703 }; 704}; 705 706&usdhc2 { 707 bus-width = <4>; 708 cap-power-off-card; 709 full-pwr-cycle; 710 pinctrl-0 = <&usdhc2_pins>; 711 pinctrl-1 = <&usdhc2_100mhz_pins>; 712 pinctrl-2 = <&usdhc2_200mhz_pins>; 713 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 714 vmmc-supply = <&vmmc>; 715 status = "okay"; 716}; 717