xref: /linux/scripts/dtc/include-prefixes/arm64/freescale/imx8mp-frdm.dts (revision 6589b3d76db2d6adbf8f2084c303fb24252a0dc6) 
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6/dts-v1/;
7
8#include "imx8mp.dtsi"
9
10/ {
11	model = "NXP i.MX8MPlus FRDM board";
12	compatible = "fsl,imx8mp-frdm", "fsl,imx8mp";
13
14	chosen {
15		stdout-path = &uart2;
16	};
17
18	gpio-leds {
19		compatible = "gpio-leds";
20
21		led-0 {
22			label = "red";
23			gpios = <&pcal6416_0 13 GPIO_ACTIVE_HIGH>;
24			default-state = "off";
25		};
26
27		led-1 {
28			label = "green";
29			gpios = <&pcal6416_0 14 GPIO_ACTIVE_HIGH>;
30			default-state = "on";
31		};
32
33		led-2 {
34			label = "blue";
35			gpios = <&pcal6416_0 15 GPIO_ACTIVE_HIGH>;
36			default-state = "off";
37		};
38	};
39
40	memory@40000000 {
41		device_type = "memory";
42		reg = <0x0 0x40000000 0 0xc0000000>,
43		      <0x1 0x00000000 0 0x40000000>;
44	};
45};
46
47&A53_0 {
48	cpu-supply = <&reg_arm>;
49};
50
51&A53_1 {
52	cpu-supply = <&reg_arm>;
53};
54
55&A53_2 {
56	cpu-supply = <&reg_arm>;
57};
58
59&A53_3 {
60	cpu-supply = <&reg_arm>;
61};
62
63&i2c1 {
64	clock-frequency = <400000>;
65	pinctrl-names = "default";
66	pinctrl-0 = <&pinctrl_i2c1>;
67	status = "okay";
68
69	pmic@25 {
70		compatible = "nxp,pca9450c";
71		reg = <0x25>;
72		pinctrl-names = "default";
73		pinctrl-0 = <&pinctrl_pmic>;
74		interrupt-parent = <&gpio1>;
75		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
76
77		regulators {
78			BUCK1 {
79				regulator-name = "BUCK1";
80				regulator-min-microvolt = <720000>;
81				regulator-max-microvolt = <1000000>;
82				regulator-boot-on;
83				regulator-always-on;
84				regulator-ramp-delay = <3125>;
85			};
86
87			reg_arm: BUCK2 {
88				regulator-name = "BUCK2";
89				regulator-min-microvolt = <720000>;
90				regulator-max-microvolt = <1025000>;
91				regulator-boot-on;
92				regulator-always-on;
93				regulator-ramp-delay = <3125>;
94				nxp,dvs-run-voltage = <950000>;
95				nxp,dvs-standby-voltage = <850000>;
96			};
97
98			BUCK4 {
99				regulator-name = "BUCK4";
100				regulator-min-microvolt = <3000000>;
101				regulator-max-microvolt = <3600000>;
102				regulator-boot-on;
103				regulator-always-on;
104			};
105
106			reg_buck5: BUCK5 {
107				regulator-name = "BUCK5";
108				regulator-min-microvolt = <1650000>;
109				regulator-max-microvolt = <1950000>;
110				regulator-boot-on;
111				regulator-always-on;
112			};
113
114			BUCK6 {
115				regulator-name = "BUCK6";
116				regulator-min-microvolt = <1045000>;
117				regulator-max-microvolt = <1155000>;
118				regulator-boot-on;
119				regulator-always-on;
120			};
121
122			LDO1 {
123				regulator-name = "LDO1";
124				regulator-min-microvolt = <1650000>;
125				regulator-max-microvolt = <1950000>;
126				regulator-boot-on;
127				regulator-always-on;
128			};
129
130			LDO3 {
131				regulator-name = "LDO3";
132				regulator-min-microvolt = <1710000>;
133				regulator-max-microvolt = <1890000>;
134				regulator-boot-on;
135				regulator-always-on;
136			};
137
138			LDO5 {
139				regulator-name = "LDO5";
140				regulator-min-microvolt = <1800000>;
141				regulator-max-microvolt = <3300000>;
142				regulator-boot-on;
143				regulator-always-on;
144			};
145		};
146	};
147
148	pcal6416_0: gpio@20 {
149		compatible = "nxp,pcal6416";
150		reg = <0x20>;
151		gpio-controller;
152		#gpio-cells = <2>;
153		interrupt-controller;
154		#interrupt-cells = <2>;
155		pinctrl-names = "default";
156		pinctrl-0 = <&pinctrl_pcal6416_0_int>;
157		interrupt-parent = <&gpio3>;
158		interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
159		gpio-line-names = "CSI1_nRST",
160			"CSI2_nRST",
161			"DSI_CTP_RST",
162			"EXT_PWREN1",
163			"CAN_STBY",
164			"EXP_P0_5",
165			"EXP_P0_6",
166			"P0_7",
167			"LVDS0_BLT_EN",
168			"LVDS1_BLT_EN",
169			"LVDS0_CTP_RST",
170			"LVDS1_CTP_RST",
171			"SPK_PWREN",
172			"RLED_GPIO",
173			"GLED_GPIO",
174			"BLED_GPIO";
175	};
176
177	pcal6416_1: gpio@21 {
178		compatible = "nxp,pcal6416";
179		reg = <0x21>;
180		gpio-controller;
181		#gpio-cells = <2>;
182		interrupt-controller;
183		#interrupt-cells = <2>;
184		pinctrl-names = "default";
185		pinctrl-0 = <&pinctrl_pcal6416_1_int>;
186		interrupt-parent = <&gpio2>;
187		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
188		gpio-line-names = "P0_0",
189			"P0_1",
190			"AUD_nINT",
191			"RTC_nINTA",
192			"USB1_SS_SEL",
193			"USB2_PWR_EN",
194			"SPI_EXP_SEL",
195			"P0_7",
196			"W2_HOST_WAKE_SD_3V3",
197			"W2_HOST_WAKE_BT_3V3",
198			"EXP_WIFI_BT_PDN_3V3",
199			"EXP_BT_RST_3V3",
200			"W2_RST_IND_3V3",
201			"SPI_nINT_3V3",
202			"KEYM_PCIE_nWAKE",
203			"P1_7";
204	};
205};
206
207&i2c2 {
208	clock-frequency = <400000>;
209	pinctrl-names = "default";
210	pinctrl-0 = <&pinctrl_i2c2>;
211	status = "okay";
212};
213
214&i2c3 {
215	clock-frequency = <400000>;
216	pinctrl-names = "default";
217	pinctrl-0 = <&pinctrl_i2c3>;
218	status = "okay";
219};
220
221&snvs_pwrkey {
222	status = "okay";
223};
224
225&uart2 {
226	pinctrl-names = "default";
227	pinctrl-0 = <&pinctrl_uart2>;
228	status = "okay";
229};
230
231&uart3 {
232	pinctrl-names = "default";
233	pinctrl-0 = <&pinctrl_uart3>;
234	assigned-clocks = <&clk IMX8MP_CLK_UART3>;
235	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
236	uart-has-rtscts;
237	status = "okay";
238};
239
240&usdhc3 {
241	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
242	assigned-clock-rates = <400000000>;
243	pinctrl-names = "default", "state_100mhz", "state_200mhz";
244	pinctrl-0 = <&pinctrl_usdhc3>;
245	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
246	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
247	bus-width = <8>;
248	non-removable;
249	status = "okay";
250};
251
252&iomuxc {
253	pinctrl_i2c1: i2c1grp {
254		fsl,pins = <
255			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL	0x400001c2
256			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA	0x400001c2
257		>;
258	};
259
260	pinctrl_i2c2: i2c2grp {
261		fsl,pins = <
262			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL	0x400001c2
263			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA	0x400001c2
264		>;
265	};
266
267	pinctrl_i2c3: i2c3grp {
268		fsl,pins = <
269			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL	0x400001c2
270			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA	0x400001c2
271		>;
272	};
273
274	pinctrl_pmic: pmicgrp {
275		fsl,pins = <
276			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03	0x000001c0
277		>;
278	};
279
280	pinctrl_pcal6416_0_int: pcal6416-0-int-grp {
281		fsl,pins = <
282			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x146
283		>;
284	};
285
286	pinctrl_pcal6416_1_int: pcal6416-1-int-grp {
287		fsl,pins = <
288			MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11	0x146
289		>;
290	};
291
292	pinctrl_uart2: uart2grp {
293		fsl,pins = <
294			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140
295			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140
296		>;
297	};
298
299	pinctrl_uart3: uart3grp {
300		fsl,pins = <
301			MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX	0x140
302			MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX	0x140
303			MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS	0x140
304			MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS	0x140
305		>;
306	};
307
308	pinctrl_usdhc3: usdhc3grp {
309		fsl,pins = <
310			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190
311			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0
312			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0
313			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0
314			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0
315			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0
316			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0
317			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0
318			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0
319			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0
320			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190
321		>;
322	};
323
324	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
325		fsl,pins = <
326			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194
327			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4
328			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4
329			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4
330			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4
331			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4
332			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4
333			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4
334			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4
335			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4
336			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194
337		>;
338	};
339
340	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
341		fsl,pins = <
342			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196
343			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6
344			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6
345			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6
346			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6
347			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6
348			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6
349			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6
350			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6
351			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6
352			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196
353		>;
354	};
355};
356