xref: /linux/scripts/dtc/include-prefixes/arm64/freescale/imx8mn-vhip4-evalboard-common.dtsi (revision 6589b3d76db2d6adbf8f2084c303fb24252a0dc6) 
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2020-2024 Fedor Ross <fedor.ross@ifm.com>
4 */
5
6#include "imx8mn.dtsi"
7#include <dt-bindings/leds/common.h>
8
9/ {
10	model = "ifm i.MX8MNano VHIP4 Evaluation Board";
11	compatible = "ifm,imx8mn-vhip4-evalboard", "ifm,imx8mn-vhip4", "fsl,imx8mn";
12
13	aliases {
14		mmc0 = &usdhc3;
15		mmc1 = &usdhc1;
16		mmc2 = &usdhc2;
17		rtc0 = &hw_rtc;
18		rtc1 = &snvs_rtc;
19	};
20
21	chosen {
22		bootargs = "console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200 rootwait";
23		stdout-path = &uart3;
24	};
25
26	memory@40000000 {
27		device_type = "memory";
28		reg = <0x0 0x40000000 0 0x40000000>;
29	};
30
31	can_clk20m: can-clk20m {
32		compatible = "fixed-clock";
33		#clock-cells = <0>;
34		clock-frequency = <20000000>;
35	};
36
37	can_clk40m: can-clk40m {
38		compatible = "fixed-clock";
39		#clock-cells = <0>;
40		clock-frequency = <40000000>;
41	};
42
43	gpio-keys {
44		compatible = "gpio-keys";
45		pinctrl-0 = <&pinctrl_gpio_button>;
46		pinctrl-names = "default";
47
48		button-2 {
49			label = "Button2";
50			gpios = <&gpio2 16 GPIO_ACTIVE_LOW>;
51			linux,code = <KEY_2>;
52		};
53
54		button-3 {
55			label = "Button3";
56			gpios = <&gpio2 18 GPIO_ACTIVE_LOW>;
57			linux,code = <KEY_3>;
58		};
59	};
60
61	ifm_led: led {
62		compatible = "gpio-leds";
63		pinctrl-0 = <&pinctrl_gpio_led>;
64		pinctrl-names = "default", "extended";
65
66		led-0 {
67			function = LED_FUNCTION_STATUS;
68			function-enumerator = <1>;
69			color = <LED_COLOR_ID_YELLOW>;
70			gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
71			default-state = "keep";
72		};
73
74		led-1 {
75			function = LED_FUNCTION_STATUS;
76			function-enumerator = <2>;
77			color = <LED_COLOR_ID_GREEN>;
78			gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
79			default-state = "keep";
80		};
81	};
82};
83
84&A53_0 {
85	cpu-supply = <&buck2_reg>;
86};
87
88&A53_1 {
89	cpu-supply = <&buck2_reg>;
90};
91
92&A53_2 {
93	cpu-supply = <&buck2_reg>;
94};
95
96&A53_3 {
97	cpu-supply = <&buck2_reg>;
98};
99
100&ddrc {
101	operating-points-v2 = <&ddrc_opp_table>;
102
103	ddrc_opp_table: opp-table {
104		compatible = "operating-points-v2";
105
106		opp-25000000 {
107			opp-hz = /bits/ 64 <25000000>;
108		};
109
110		opp-100000000 {
111			opp-hz = /bits/ 64 <100000000>;
112		};
113
114		opp-600000000 {
115			opp-hz = /bits/ 64 <600000000>;
116		};
117	};
118};
119
120&ecspi1 {
121	pinctrl-names = "default";
122	pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_cs>;
123	/delete-property/ dmas;
124	/delete-property/ dma-names;
125};
126
127&ecspi3 {
128	pinctrl-names = "default";
129	pinctrl-0 = <&pinctrl_ecspi3>, <&pinctrl_ecspi3_cs>;
130	/delete-property/ dmas;
131	/delete-property/ dma-names;
132};
133
134&gpu {
135	/* SoC has GPU fused off. */
136	status = "disabled";
137};
138
139&i2c1 {
140	clock-frequency = <100000>;
141	pinctrl-names = "default", "gpio";
142	pinctrl-0 = <&pinctrl_i2c1>;
143	pinctrl-1 = <&pinctrl_i2c1_gpio>;
144
145	eeprom@51 {
146		compatible = "atmel,24c128";
147		reg = <0x51>;
148	};
149
150	hw_rtc: rtc@52 {
151		compatible = "microcrystal,rv3028";
152		reg = <0x52>;
153	};
154};
155
156&i2c3 {
157	clock-frequency = <100000>;
158	pinctrl-names = "default", "gpio";
159	pinctrl-0 = <&pinctrl_i2c3>;
160	pinctrl-1 = <&pinctrl_i2c3_gpio>;
161
162	ifm_pmic: pmic@4b {
163		compatible = "rohm,bd71847";
164		reg = <0x4b>;
165		pinctrl-0 = <&pinctrl_pmic>;
166		rohm,reset-snvs-powered;
167
168		regulators {
169			buck1_reg: BUCK1 {
170				regulator-name = "buck1";
171				regulator-min-microvolt = <790000>;
172				regulator-max-microvolt = <860000>;
173				regulator-boot-on;
174				regulator-always-on;
175				regulator-ramp-delay = <1250>;
176			};
177
178			buck2_reg: BUCK2 {
179				regulator-name = "buck2";
180				regulator-min-microvolt = <840000>;
181				regulator-max-microvolt = <960000>;
182				regulator-boot-on;
183				regulator-always-on;
184				regulator-ramp-delay = <1250>;
185			};
186
187			buck3_reg: BUCK3 {
188				// BUCK5 in datasheet
189				regulator-name = "buck3";
190				regulator-min-microvolt = <700000>;
191				regulator-max-microvolt = <1350000>;
192			};
193
194			buck4_reg: BUCK4 {
195				// BUCK6 in datasheet
196				regulator-name = "buck4";
197				regulator-min-microvolt = <3300000>;
198				regulator-max-microvolt = <3300000>;
199				regulator-boot-on;
200				regulator-always-on;
201			};
202
203			buck5_reg: BUCK5 {
204				// BUCK7 in datasheet
205				regulator-name = "buck5";
206				regulator-min-microvolt = <1800000>;
207				regulator-max-microvolt = <1800000>;
208				regulator-boot-on;
209				regulator-always-on;
210			};
211
212			buck6_reg: BUCK6 {
213				// BUCK8 in datasheet
214				regulator-name = "buck6";
215				regulator-min-microvolt = <1100000>;
216				regulator-max-microvolt = <1100000>;
217				regulator-boot-on;
218				regulator-always-on;
219			};
220
221			ldo1_reg: LDO1 {
222				regulator-name = "ldo1";
223				regulator-min-microvolt = <1800000>;
224				regulator-max-microvolt = <1800000>;
225				regulator-boot-on;
226				regulator-always-on;
227			};
228
229			ldo2_reg: LDO2 {
230				regulator-name = "ldo2";
231				regulator-min-microvolt = <800000>;
232				regulator-max-microvolt = <800000>;
233				regulator-boot-on;
234				regulator-always-on;
235			};
236
237			ldo3_reg: LDO3 {
238				regulator-name = "ldo3";
239				regulator-min-microvolt = <1800000>;
240				regulator-max-microvolt = <1800000>;
241				regulator-boot-on;
242				regulator-always-on;
243			};
244
245			ldo4_reg: LDO4 {
246				regulator-name = "ldo4";
247				regulator-min-microvolt = <900000>;
248				regulator-max-microvolt = <1800000>;
249			};
250
251			ldo5_reg: LDO5 {
252				regulator-name = "ldo5";
253				regulator-min-microvolt = <3300000>;
254				regulator-max-microvolt = <3300000>;
255			};
256
257			ldo6_reg: LDO6 {
258				regulator-name = "ldo6";
259				regulator-min-microvolt = <1200000>;
260				regulator-max-microvolt = <1200000>;
261				regulator-boot-on;
262				regulator-always-on;
263			};
264		};
265	};
266};
267
268&iomuxc {
269	pinctrl_ecspi1: ecspi1-grp {
270		fsl,pins = <
271			MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x110
272			MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x110
273			MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x190
274		>;
275	};
276
277	pinctrl_ecspi3: ecspi3-grp {
278		fsl,pins = <
279			/* SPI3_CAN_CLK */
280			MX8MN_IOMUXC_UART1_RXD_ECSPI3_SCLK		0x110
281			/* SPI3_CAN_MOSI */
282			MX8MN_IOMUXC_UART1_TXD_ECSPI3_MOSI		0x110
283			/* SPI3_CAN_MISO */
284			MX8MN_IOMUXC_UART2_RXD_ECSPI3_MISO		0x190
285		>;
286	};
287
288	pinctrl_gpio_button: gpiobutton-grp {
289		fsl,pins = <
290			MX8MN_IOMUXC_SD2_DATA1_GPIO2_IO16		0x96
291			MX8MN_IOMUXC_SD2_DATA3_GPIO2_IO18		0x96
292		>;
293	};
294
295	pinctrl_gpio_led: gpioled-grp {
296		fsl,pins = <
297			MX8MN_IOMUXC_SD2_CLK_GPIO2_IO13			0x116
298			MX8MN_IOMUXC_SD2_DATA0_GPIO2_IO15		0x116
299		>;
300	};
301
302	pinctrl_usdhc3: usdhc3-grp {
303		fsl,pins = <
304			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000110
305			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
306			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
307			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
308			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
309			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
310			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
311			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
312			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
313			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
314			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190
315			MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B	0x150
316		>;
317	};
318
319	pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
320		fsl,pins = <
321			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000114
322			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
323			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
324			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
325			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
326			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
327			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
328			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
329			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
330			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
331			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194
332			MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B	0x150
333		>;
334	};
335
336	pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
337		fsl,pins = <
338			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000116
339			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
340			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
341			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
342			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
343			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
344			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
345			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
346			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
347			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
348			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196
349			MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B	0x150
350		>;
351	};
352
353	pinctrl_wdog: wdog-grp {
354		fsl,pins = <
355			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0x64
356		>;
357	};
358};
359
360&pgc_gpumix {
361	/* SoC has GPU fused off. */
362	status = "disabled";
363};
364
365&snvs_pwrkey {
366	status = "okay";
367};
368
369&uart3 { /* console */
370	pinctrl-names = "default";
371	pinctrl-0 = <&pinctrl_uart3>;
372	status = "okay";
373};
374
375&usbotg1 {
376	status = "okay";
377};
378
379&usdhc3 {
380	assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
381	assigned-clock-rates = <400000000>;
382	pinctrl-names = "default", "state_100mhz", "state_200mhz";
383	pinctrl-0 = <&pinctrl_usdhc3>;
384	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
385	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
386	bus-width = <8>;
387	non-removable;
388	status = "okay";
389};
390
391&wdog1 {
392	pinctrl-names = "default";
393	pinctrl-0 = <&pinctrl_wdog>;
394	fsl,ext-reset-output;
395	status = "okay";
396};
397