1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Device Tree file for SolidSense N8 Compact 4 * 5 * Copyright 2024 Josua Mayer <josua@solid-run.com> 6 */ 7 8/dts-v1/; 9 10#include <dt-bindings/leds/common.h> 11 12#include "imx8mn.dtsi" 13 14/ { 15 compatible = "solidrun,solidsense-n8-compact", "fsl,imx8mn"; 16 model = "SolidRun SolidSense N8 Compact"; 17 18 /* LED labels based on enclosure, schematic names differ. */ 19 leds { 20 compatible = "gpio-leds"; 21 pinctrl-0 = <&led_pins>; 22 pinctrl-names = "default"; 23 24 /* D20 */ 25 led1 { 26 default-state = "off"; 27 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; 28 label = "led1"; 29 }; 30 31 /* D18 */ 32 led2 { 33 default-state = "off"; 34 gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; 35 label = "led2"; 36 }; 37 38 /* D19 */ 39 led3 { 40 default-state = "off"; 41 gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; 42 label = "led3"; 43 }; 44 }; 45 46 aliases { 47 gpio5 = &expander; 48 rtc0 = &rtc; 49 rtc1 = &snvs_rtc; 50 usb0 = &usbotg1; 51 watchdog0 = &wdog1; 52 watchdog1 = &rtc; 53 }; 54 55 chosen { 56 stdout-path = &uart2; 57 }; 58 59 reg_modem_vbat: regulator-modem-vbat { 60 compatible = "regulator-fixed"; 61 regulator-name = "modem-vbat"; 62 pinctrl-0 = <®ulator_modem_vbat_pins>; 63 pinctrl-names = "default"; 64 regulator-always-on; 65 regulator-max-microvolt = <3800000>; 66 regulator-min-microvolt = <3800000>; 67 gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; 68 enable-active-high; 69 }; 70 71 /* power to lte modems behind hub ports 2/3 */ 72 reg_modem_vbus: regulator-modem-vbus { 73 compatible = "regulator-fixed"; 74 regulator-name = "modem-vbus"; 75 pinctrl-0 = <®ulator_modem_vbus_pins>; 76 pinctrl-names = "default"; 77 regulator-always-on; 78 regulator-max-microvolt = <5000000>; 79 regulator-min-microvolt = <5000000>; 80 gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>; 81 enable-active-high; 82 }; 83 84 /* power to usb hub, and type-a behind hub port 1 */ 85 reg_usb1_vbus: regulator-usb1-vbus { 86 compatible = "regulator-fixed"; 87 regulator-name = "usb1-vbus"; 88 pinctrl-0 = <®ulator_usb1_vbus_pins>; 89 pinctrl-names = "default"; 90 regulator-max-microvolt = <5000000>; 91 regulator-min-microvolt = <5000000>; 92 gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; 93 enable-active-high; 94 }; 95 96 reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 97 compatible = "regulator-fixed"; 98 regulator-name = "usdhc2-vmmc"; 99 off-on-delay-us = <250>; 100 pinctrl-0 = <®ulator_usdhc2_vmmc_pins>; 101 pinctrl-names = "default"; 102 regulator-max-microvolt = <3300000>; 103 regulator-min-microvolt = <3300000>; 104 vin-supply = <®_vdd_3v3>; 105 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 106 enable-active-high; 107 }; 108 109 reg_vdd_1v8: regulator-vdd-1v8 { 110 compatible = "regulator-fixed"; 111 regulator-name = "vdd-1v8"; 112 regulator-max-microvolt = <1800000>; 113 regulator-min-microvolt = <1800000>; 114 }; 115 116 reg_vdd_3v3: regulator-vdd-3v3 { 117 compatible = "regulator-fixed"; 118 regulator-name = "vdd-3v3"; 119 regulator-max-microvolt = <3300000>; 120 regulator-min-microvolt = <3300000>; 121 }; 122 123 rfkill { 124 compatible = "rfkill-gpio"; 125 /* rfkill-gpio inverts internally */ 126 shutdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; 127 label = "rfkill-wwan"; 128 pinctrl-0 = <&modem_pins>; 129 pinctrl-names = "default"; 130 radio-type = "wwan"; 131 }; 132 133 usdhc1_pwrseq: usdhc1-pwrseq { 134 compatible = "mmc-pwrseq-simple"; 135 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; 136 }; 137 138 memory@40000000 { 139 reg = <0x0 0x40000000 0 0x80000000>; 140 device_type = "memory"; 141 }; 142}; 143 144&A53_0 { 145 cpu-supply = <&buck2_reg>; 146}; 147 148&A53_1 { 149 cpu-supply = <&buck2_reg>; 150}; 151 152&A53_2 { 153 cpu-supply = <&buck2_reg>; 154}; 155 156&A53_3 { 157 cpu-supply = <&buck2_reg>; 158}; 159 160&ddrc { 161 operating-points-v2 = <&ddrc_opp_table>; 162 163 ddrc_opp_table: opp-table { 164 compatible = "operating-points-v2"; 165 166 opp-266500000 { 167 opp-hz = /bits/ 64 <266500000>; 168 }; 169 170 opp-600000000 { 171 opp-hz = /bits/ 64 <600000000>; 172 }; 173 }; 174}; 175 176&ecspi2 { 177 /* native chip-select causes reading 0xffffffff */ 178 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 179 num-cs = <1>; 180 pinctrl-0 = <&ecspi2_pins>; 181 pinctrl-names = "default"; 182 status = "okay"; 183 184 can@0 { 185 compatible = "microchip,mcp2518fd"; 186 reg = <0>; 187 interrupt-parent = <&gpio5>; 188 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 189 clocks = <&clk IMX8MN_CLK_CLKOUT1>; 190 /* generate 8MHz clock from soc-internal 24mhz reference */ 191 assigned-clock-parents = <&clk IMX8MN_CLK_24M>, <0>; 192 assigned-clock-rates = <0>, <8000000>; 193 assigned-clocks = <&clk IMX8MN_CLK_CLKOUT1_SEL>, 194 <&clk IMX8MN_CLK_CLKOUT1_DIV>; 195 pinctrl-0 = <&can_pins>; 196 pinctrl-names = "default"; 197 spi-max-frequency = <20000000>; 198 }; 199}; 200 201&fec1 { 202 phy-handle = <&phy4>; 203 phy-mode = "rgmii-id"; 204 pinctrl-0 = <&fec1_pins>; 205 pinctrl-names = "default"; 206 status = "okay"; 207 208 mdio { 209 #address-cells = <1>; 210 #size-cells = <0>; 211 212 /* 213 * Depending on board revision two different phys are used: 214 * - v1.1: atheros phy at address 4 215 * - v1.2+: analog devices phy at address 0 216 * Configure first version by default. 217 * On v1.2 and later, U-Boot will enable the correct phy 218 * based on runtime detection and patch dtb accordingly. 219 */ 220 221 /* ADIN1300 */ 222 phy0: ethernet-phy@0 { 223 reg = <0>; 224 interrupt-parent = <&gpio1>; 225 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 226 reset-assert-us = <10>; 227 reset-deassert-us = <5000>; 228 reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; 229 adi,led-polarity = <GPIO_ACTIVE_LOW>; 230 adi,link-st-polarity = <GPIO_ACTIVE_LOW>; 231 status = "disabled"; 232 233 leds { 234 #address-cells = <1>; 235 #size-cells = <0>; 236 237 led@0 { 238 reg = <0>; 239 active-low; 240 color = <LED_COLOR_ID_YELLOW>; 241 default-state = "keep"; 242 function = LED_FUNCTION_LAN; 243 }; 244 }; 245 }; 246 247 /* AR8035 */ 248 phy4: ethernet-phy@4 { 249 reg = <4>; 250 reset-assert-us = <10000>; 251 reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; 252 status = "okay"; 253 }; 254 }; 255}; 256 257&gpio5 { 258 usb-hub-reset-hog { 259 line-name = "usb-hub-reset"; 260 gpios = <3 GPIO_ACTIVE_LOW>; 261 gpio-hog; 262 /* deasserted */ 263 output-low; 264 }; 265}; 266 267&i2c1 { 268 pinctrl-0 = <&i2c1_pins>; 269 pinctrl-names = "default"; 270 status = "okay"; 271 272 pmic@4b { 273 compatible = "rohm,bd71847"; 274 reg = <0x4b>; 275 interrupt-parent = <&gpio1>; 276 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 277 clocks = <&osc_32k>; 278 #clock-cells = <0>; 279 clock-output-names = "clk-32k-out"; 280 pinctrl-0 = <&pmic_pins>; 281 pinctrl-names = "default"; 282 rohm,reset-snvs-powered; 283 284 regulators { 285 BUCK1 { 286 regulator-always-on; 287 regulator-boot-on; 288 regulator-max-microvolt = <1300000>; 289 regulator-min-microvolt = <700000>; 290 regulator-ramp-delay = <1250>; 291 // supplies soc vdd, soc mipi vdd @ 0.9V 292 regulator-name = "buck1"; 293 rohm,dvs-run-voltage = <850000>; 294 rohm,dvs-suspend-voltage = <750000>; 295 }; 296 297 buck2_reg: BUCK2 { 298 regulator-name = "buck2"; 299 regulator-always-on; 300 regulator-boot-on; 301 regulator-max-microvolt = <1300000>; 302 regulator-min-microvolt = <700000>; 303 regulator-ramp-delay = <1250>; 304 rohm,dvs-idle-voltage = <900000>; 305 rohm,dvs-run-voltage = <1000000>; 306 rohm,dvs-suspend-voltage = <0>; 307 }; 308 309 BUCK3 { 310 // BUCK5 in datasheet 311 // output floating 312 regulator-name = "buck3"; 313 regulator-max-microvolt = <1350000>; 314 regulator-min-microvolt = <700000>; 315 }; 316 317 BUCK4 { 318 regulator-always-on; 319 regulator-boot-on; 320 regulator-max-microvolt = <3300000>; 321 regulator-min-microvolt = <3000000>; 322 // BUCK6 in datasheet 323 // supplies ldo3, ldo5, muxsw 324 regulator-name = "buck4"; 325 }; 326 327 BUCK5 { 328 regulator-always-on; 329 regulator-boot-on; 330 regulator-max-microvolt = <1995000>; 331 regulator-min-microvolt = <1605000>; 332 // BUCK7 in datasheet 333 // supplies ldo4, ldo6, muxsw 334 // enables dram vpp @ 2.5V 335 regulator-name = "buck5"; 336 }; 337 338 BUCK6 { 339 // BUCK8 in datasheet 340 // supplies dram @ 1.2V 341 regulator-name = "buck6"; 342 regulator-always-on; 343 regulator-boot-on; 344 regulator-max-microvolt = <1400000>; 345 regulator-min-microvolt = <800000>; 346 }; 347 348 LDO1 { 349 // supplies soc snvs @ 1.8V 350 regulator-name = "ldo1"; 351 regulator-always-on; 352 regulator-boot-on; 353 regulator-max-microvolt = <3300000>; 354 regulator-min-microvolt = <1600000>; 355 }; 356 357 LDO2 { 358 // supplies soc snvs @ 0.8V 359 regulator-name = "ldo2"; 360 regulator-always-on; 361 regulator-boot-on; 362 regulator-max-microvolt = <900000>; 363 regulator-min-microvolt = <800000>; 364 }; 365 366 LDO3 { 367 // supplies soc vdd @ 1.8V 368 regulator-name = "ldo3"; 369 regulator-always-on; 370 regulator-boot-on; 371 regulator-max-microvolt = <3300000>; 372 regulator-min-microvolt = <1800000>; 373 }; 374 375 LDO4 { 376 // output floating 377 regulator-name = "ldo4"; 378 regulator-max-microvolt = <1800000>; 379 regulator-min-microvolt = <900000>; 380 }; 381 382 LDO5 { 383 // output floating 384 regulator-name = "ldo5"; 385 regulator-max-microvolt = <3300000>; 386 regulator-min-microvolt = <800000>; 387 }; 388 389 LDO6 { 390 // supplies soc vdd mipi @ 1.2V 391 regulator-name = "ldo6"; 392 regulator-always-on; 393 regulator-boot-on; 394 regulator-max-microvolt = <1800000>; 395 regulator-min-microvolt = <900000>; 396 }; 397 }; 398 }; 399}; 400 401&i2c2 { 402 /* 403 * routed to various connectors: 404 * - basler camera (CON2) 405 * - touchscreen (J3) 406 * - expansion connector (J14) 407 */ 408 pinctrl-names = "default"; 409 pinctrl-0 = <&i2c2_pins>; 410 status = "okay"; 411}; 412 413&i2c3 { 414 pinctrl-0 = <&i2c3_pins>; 415 pinctrl-names = "default"; 416 status = "okay"; 417 418 expander: gpio@20 { 419 compatible = "ti,tca6408"; 420 reg = <0x20>; 421 #interrupt-cells = <2>; 422 interrupt-controller; 423 interrupt-parent = <&gpio2>; 424 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 425 #gpio-cells = <2>; 426 gpio-controller; 427 gpio-line-names = "SYSGD", "PFO#", "CAPGD", "CAPFLT#", 428 "CHGEN#", "BSTEN#", "", ""; 429 pinctrl-0 = <&gpio_expander_pins>; 430 pinctrl-names = "default"; 431 reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; 432 }; 433 434 light-sensor@44 { 435 compatible = "isil,isl29023"; 436 reg = <0x44>; 437 }; 438 439 accelerometer@53 { 440 compatible = "adi,adxl345"; 441 reg = <0x53>; 442 }; 443 444 /* battery-charger@68 */ 445 446 rtc: rtc@69 { 447 compatible = "abracon,abx80x"; 448 reg = <0x69>; 449 interrupt-parent = <&gpio1>; 450 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 451 pinctrl-0 = <&rtc_pins>; 452 pinctrl-names = "default"; 453 abracon,tc-diode = "schottky"; 454 abracon,tc-resistor = <3>; 455 }; 456}; 457 458&i2c4 { 459 /* routed to expansion connector (J14) */ 460 pinctrl-names = "default"; 461 pinctrl-0 = <&i2c4_pins>; 462 status = "okay"; 463}; 464 465&iomuxc { 466 pinctrl-0 = <&tamper_pins>, <&usb_hub_pins>; 467 pinctrl-names = "default"; 468 469 can_pins: pinctrl-can-grp { 470 fsl,pins = < 471 MX8MN_IOMUXC_SAI3_TXD_GPIO5_IO1 0x140 472 >; 473 }; 474 475 ecspi2_pins: pinctrl-ecspi2-grp { 476 fsl,pins = < 477 MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x96 478 MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x1d6 479 MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x1d6 480 MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x1d6 481 >; 482 }; 483 484 fec1_pins: pinctrl-fec1-grp { 485 /* 486 * Some pins are sampled at phy reset to apply configuration: 487 * - AR803x PHY (revision 1.1) 488 * - RXD[1:0]: phy address bits [1:0] 489 * - RXD[3:2],RX_CTL: mac interface select bits 3,1,0 490 * - ADIN1300 PHY (revision 1.2 or later) 491 * - RXD[3:0]: phy address bits [3:0] 492 * - RX_CTL,RXC: mac interface select bits 1,0 493 * SoC enables pull-down at reset, PHYs have internal 494 * pull-down, so pinmux may unset pull-enable. 495 */ 496 fsl,pins = < 497 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x2 498 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x2 499 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1e 500 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1e 501 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1e 502 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1e 503 /* RD[3:0] sampled at phy reset for address bits [3:0] */ 504 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90 505 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90 506 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90 507 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90 508 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x10 509 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90 510 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90 511 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x10 512 /* phy reset */ 513 MX8MN_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x0 514 /* phy interrupt */ 515 MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140 516 >; 517 }; 518 519 gpio_expander_pins: pinctrl-gpio-expander-grp { 520 fsl,pins = < 521 MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x140 522 MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140 523 >; 524 }; 525 526 i2c1_pins: pinctrl-i2c1-grp { 527 fsl,pins = < 528 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c2 529 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c2 530 >; 531 }; 532 533 i2c2_pins: pinctrl-i2c2-grp { 534 fsl,pins = < 535 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2 536 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2 537 >; 538 }; 539 540 i2c3_pins: pinctrl-i2c3-grp { 541 fsl,pins = < 542 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2 543 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2 544 >; 545 }; 546 547 i2c4_pins: pinctrl-i2c4-grp { 548 fsl,pins = < 549 MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2 550 MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2 551 >; 552 }; 553 554 ieee802151_radio_pins: pinctrl-ieee802151-radio-grp { 555 fsl,pins = < 556 /* RESETN */ 557 MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x0 558 /* VDD_EN */ 559 MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x0 560 /* SWDCLK */ 561 MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x0 562 /* SDIO */ 563 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x0 564 >; 565 }; 566 567 led_pins: pinctrl-led-grp { 568 fsl,pins = < 569 MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x100 570 MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x100 571 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x100 572 >; 573 }; 574 575 modem_pins: pinctrl-modem-grp { 576 fsl,pins = < 577 /* RESET_N: modem-internal pull-down */ 578 MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x0 579 /* PWRKEY: pull-down ensures always-on */ 580 MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x100 581 >; 582 }; 583 584 pmic_pins: pinctrl-pmic-grp { 585 fsl,pins = < 586 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x140 587 >; 588 }; 589 590 regulator_modem_vbat_pins: pinctrl-regulator-modem-vbat-grp { 591 fsl,pins = < 592 MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x0 593 >; 594 }; 595 596 regulator_modem_vbus_pins: pinctrl-regulator-modem-vbus-grp { 597 fsl,pins = < 598 MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x0 599 >; 600 }; 601 602 regulator_usb1_vbus_pins: pinctrl-regulator-usb1-vbus-grp { 603 fsl,pins = < 604 MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x0 605 >; 606 }; 607 608 regulator_usdhc2_vmmc_pins: pinctrl-regulator-usdhc2-vmmc-grp { 609 fsl,pins = < 610 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0 611 >; 612 }; 613 614 rtc_pins: pinctrl-rtc-grp { 615 fsl,pins = < 616 MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140 617 MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x100 618 >; 619 }; 620 621 tamper_pins: pinctrl-tamper-grp { 622 /* 623 * Routed to physical tamper input (J12), 624 * accelerometer and light-sensor interrupts. 625 */ 626 fsl,pins = < 627 MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x140 628 >; 629 }; 630 631 uart1_pins: pinctrl-uart1-grp { 632 fsl,pins = < 633 MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 634 MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 635 MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 636 MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 637 /* BT_REG_ON */ 638 MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0 639 /* BT_WAKE_DEV */ 640 MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0 641 /* BT_WAKE_HOST */ 642 MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x100 643 >; 644 }; 645 646 uart2_pins: pinctrl-uart2-grp { 647 fsl,pins = < 648 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 649 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 650 >; 651 }; 652 653 uart3_pins: pinctrl-uart3-grp { 654 fsl,pins = < 655 MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x140 656 MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x140 657 MX8MN_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x140 658 MX8MN_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x140 659 >; 660 }; 661 662 uart4_pins: pinctrl-uart4-grp { 663 fsl,pins = < 664 MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 665 MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 666 >; 667 }; 668 669 usb_hub_pins: pinctrl-usb-hub-grp { 670 fsl,pins = < 671 MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x0 672 >; 673 }; 674 675 usdhc1_pins: pinctrl-usdhc1-grp { 676 fsl,pins = < 677 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 678 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 679 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 680 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 681 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 682 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 683 /* wifi refclk */ 684 MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x0 685 /* WL_WAKE_HOST */ 686 MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x100 687 /* WL_REG_ON */ 688 MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0 689 >; 690 }; 691 692 usdhc2_100mhz_pins: pinctrl-usdhc2-100mhz-grp { 693 fsl,pins = < 694 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 695 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 696 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 697 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 698 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 699 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 700 MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0 701 /* usdhc2 signalling voltage pmic control */ 702 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x140 703 >; 704 }; 705 706 usdhc2_200mhz_pins: pinctrl-usdhc2-100mhz-grp { 707 fsl,pins = < 708 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 709 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 710 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 711 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 712 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 713 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 714 MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0 715 /* usdhc2 signalling voltage pmic control */ 716 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x140 717 >; 718 }; 719 720 usdhc2_pins: pinctrl-usdhc2-grp { 721 fsl,pins = < 722 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 723 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 724 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 725 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 726 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 727 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 728 MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0 729 /* usdhc2 signalling voltage pmic control */ 730 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x140 731 >; 732 }; 733 734 usdhc3_pins: pinctrl-usdhc3-grp { 735 fsl,pins = < 736 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 737 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 738 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 739 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 740 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 741 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 742 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 743 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 744 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 745 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 746 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 747 >; 748 }; 749 750 wdog1_pins: pinctrl-wdog1-grp { 751 fsl,pins = < 752 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x140 753 >; 754 }; 755}; 756 757/* Bluetooth */ 758&uart1 { 759 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; 760 /* select 80MHz parent clock to support maximum baudrate 4Mbps */ 761 assigned-clocks = <&clk IMX8MN_CLK_UART1>; 762 pinctrl-0 = <&uart1_pins>; 763 pinctrl-names = "default"; 764 uart-has-rtscts; 765 status = "okay"; 766 767 bluetooth { 768 compatible = "brcm,bcm4330-bt"; 769 device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; 770 host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; 771 max-speed = <3000000>; 772 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; 773 }; 774}; 775 776/* console */ 777&uart2 { 778 pinctrl-0 = <&uart2_pins>; 779 pinctrl-names = "default"; 780 status = "okay"; 781}; 782 783/* RS485 */ 784&uart3 { 785 pinctrl-0 = <&uart3_pins>; 786 pinctrl-names = "default"; 787 uart-has-rtscts; 788 fsl,dte-mode; 789 linux,rs485-enabled-at-boot-time; 790 status = "okay"; 791}; 792 793/* 802.15.1 radio */ 794&uart4 { 795 pinctrl-0 = <&uart4_pins &ieee802151_radio_pins>; 796 pinctrl-names = "default"; 797 status = "okay"; 798}; 799 800&usbotg1 { 801 disable-over-current; 802 dr_mode = "host"; 803 vbus-supply = <®_usb1_vbus>; 804 status = "okay"; 805}; 806 807/* WiFi */ 808&usdhc1 { 809 bus-width = <4>; 810 mmc-pwrseq = <&usdhc1_pwrseq>; 811 pinctrl-0 = <&usdhc1_pins>; 812 pinctrl-names = "default"; 813 vmmc-supply = <®_vdd_3v3>; 814 vqmmc-supply = <®_vdd_1v8>; 815 status = "okay"; 816}; 817 818/* microSD */ 819&usdhc2 { 820 broken-cd; 821 bus-width = <4>; 822 pinctrl-0 = <&usdhc2_pins>; 823 pinctrl-1 = <&usdhc2_100mhz_pins>; 824 pinctrl-2 = <&usdhc2_200mhz_pins>; 825 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 826 vmmc-supply = <®_usdhc2_vmmc>; 827 status = "okay"; 828}; 829 830/* eMMC */ 831&usdhc3 { 832 bus-width = <8>; 833 non-removable; 834 pinctrl-0 = <&usdhc3_pins>; 835 vmmc-supply = <®_vdd_3v3>; 836 vqmmc-supply = <®_vdd_1v8>; 837 /* 838 * Use lowest drive strength for all high-speed modes to minimise 839 * electro-magnetic emissions. 840 * In this particular design HS-400 still works okay, no extra 841 * pinctrl for 100mhz and 200mhz are required. 842 */ 843 pinctrl-names = "default"; 844 status = "okay"; 845}; 846 847&wdog1 { 848 pinctrl-0 = <&wdog1_pins>; 849 pinctrl-names = "default"; 850 status = "okay"; 851}; 852