1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2025 Josua Mayer <josua@solid-run.com> 4 */ 5 6#include <dt-bindings/phy/phy-imx8-pcie.h> 7 8#include "imx8mm.dtsi" 9 10/ { 11 compatible = "solidrun,imx8mm-sr-som", "fsl,imx8mm"; 12 model = "SolidRun i.MX8MM SoM"; 13 14 chosen { 15 bootargs = "earlycon=ec_imx6q,0x30890000,115200"; 16 stdout-path = &uart2; 17 }; 18 19 v_1_8: regulator-1-8 { 20 compatible = "regulator-fixed"; 21 regulator-name = "1v8"; 22 regulator-max-microvolt = <1800000>; 23 regulator-min-microvolt = <1800000>; 24 }; 25 26 v_3_3: regulator-3-3 { 27 compatible = "regulator-fixed"; 28 regulator-name = "3v3"; 29 regulator-max-microvolt = <3300000>; 30 regulator-min-microvolt = <3300000>; 31 }; 32 33 usdhc1_pwrseq: usdhc1-pwrseq { 34 compatible = "mmc-pwrseq-simple"; 35 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; 36 }; 37 38 memory@40000000 { 39 reg = <0x0 0x40000000 0 0x80000000>; 40 device_type = "memory"; 41 }; 42}; 43 44&fec1 { 45 phy = <&phy0>; 46 phy-mode = "rgmii-id"; 47 pinctrl-0 = <&fec1_pins>; 48 pinctrl-names = "default"; 49 status = "okay"; 50 51 mdio { 52 #address-cells = <1>; 53 #size-cells = <0>; 54 55 phy0: ethernet-phy@4 { 56 compatible = "ethernet-phy-ieee802.3-c22"; 57 reg = <0x4>; 58 phy-reset-duration = <10>; 59 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 60 vddio-supply = <&vddio>; 61 qca,smarteee-tw-us-1g = <24>; 62 63 vddio: vddio-regulator { 64 regulator-max-microvolt = <1800000>; 65 regulator-min-microvolt = <1800000>; 66 }; 67 }; 68 }; 69}; 70 71&i2c1 { 72 clock-frequency = <400000>; 73 pinctrl-0 = <&i2c1_pins>; 74 pinctrl-names = "default"; 75 status = "okay"; 76 77 pmic@4b { 78 compatible = "rohm,bd71847"; 79 reg = <0x4b>; 80 interrupt-parent = <&gpio1>; 81 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 82 clocks = <&osc_32k>; 83 #clock-cells = <0>; 84 clock-output-names = "clk-32k-out"; 85 pinctrl-0 = <&pmic_pins>; 86 pinctrl-names = "default"; 87 rohm,reset-snvs-powered; 88 89 regulators { 90 buck1_reg: BUCK1 { 91 regulator-name = "buck1"; 92 regulator-always-on; 93 regulator-boot-on; 94 regulator-max-microvolt = <1300000>; 95 regulator-min-microvolt = <700000>; 96 regulator-ramp-delay = <1250>; 97 }; 98 99 buck2_reg: BUCK2 { 100 regulator-name = "buck2"; 101 regulator-always-on; 102 regulator-boot-on; 103 regulator-max-microvolt = <1300000>; 104 regulator-min-microvolt = <700000>; 105 regulator-ramp-delay = <1250>; 106 rohm,dvs-idle-voltage = <900000>; 107 rohm,dvs-run-voltage = <1000000>; 108 }; 109 110 buck3_reg: BUCK3 { 111 // BUCK5 in datasheet 112 regulator-name = "buck3"; 113 regulator-always-on; 114 regulator-boot-on; 115 regulator-max-microvolt = <1350000>; 116 regulator-min-microvolt = <700000>; 117 }; 118 119 buck4_reg: BUCK4 { 120 // BUCK6 in datasheet 121 regulator-name = "buck4"; 122 regulator-always-on; 123 regulator-boot-on; 124 regulator-max-microvolt = <3300000>; 125 regulator-min-microvolt = <3000000>; 126 }; 127 128 buck5_reg: BUCK5 { 129 // BUCK7 in datasheet 130 regulator-name = "buck5"; 131 regulator-always-on; 132 regulator-boot-on; 133 regulator-max-microvolt = <1995000>; 134 regulator-min-microvolt = <1605000>; 135 }; 136 137 buck6_reg: BUCK6 { 138 // BUCK8 in datasheet 139 regulator-name = "buck6"; 140 regulator-always-on; 141 regulator-boot-on; 142 regulator-max-microvolt = <1400000>; 143 regulator-min-microvolt = <800000>; 144 }; 145 146 ldo1_reg: LDO1 { 147 regulator-name = "ldo1"; 148 regulator-always-on; 149 regulator-boot-on; 150 regulator-max-microvolt = <3300000>; 151 regulator-min-microvolt = <1600000>; 152 }; 153 154 ldo2_reg: LDO2 { 155 regulator-name = "ldo2"; 156 regulator-always-on; 157 regulator-boot-on; 158 regulator-max-microvolt = <900000>; 159 regulator-min-microvolt = <800000>; 160 }; 161 162 ldo3_reg: LDO3 { 163 regulator-name = "ldo3"; 164 regulator-always-on; 165 regulator-boot-on; 166 regulator-max-microvolt = <3300000>; 167 regulator-min-microvolt = <1800000>; 168 }; 169 170 ldo4_reg: LDO4 { 171 regulator-name = "ldo4"; 172 regulator-always-on; 173 regulator-boot-on; 174 regulator-max-microvolt = <1800000>; 175 regulator-min-microvolt = <900000>; 176 }; 177 178 ldo6_reg: LDO6 { 179 regulator-name = "ldo6"; 180 regulator-always-on; 181 regulator-boot-on; 182 regulator-max-microvolt = <1800000>; 183 regulator-min-microvolt = <900000>; 184 }; 185 }; 186 }; 187 188 som_eeprom: eeprom@50 { 189 compatible = "st,24c01", "atmel,24c01"; 190 reg = <0x50>; 191 pagesize = <16>; 192 }; 193}; 194 195&iomuxc { 196 fec1_pins: pinctrl-fec1-grp { 197 fsl,pins = < 198 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 199 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 200 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 201 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 202 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 203 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 204 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 205 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 206 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 207 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 208 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 209 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 210 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 211 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 212 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 213 >; 214 }; 215 216 i2c1_pins: pinctrl-i2c1-grp { 217 fsl,pins = < 218 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 219 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 220 >; 221 }; 222 223 pcie_pins: pinctrl-pcie-grp { 224 fsl,pins = < 225 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x0 226 >; 227 }; 228 229 pmic_pins: pinctrl-pmic-grp { 230 fsl,pins = < 231 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x140 232 >; 233 }; 234 235 uart1_pins: pinctrl-uart1-grp { 236 fsl,pins = < 237 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 238 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 239 MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 240 MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 241 /* BT_REG_ON */ 242 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0 243 /* BT_WAKE_DEV */ 244 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0 245 /* BT_WAKE_HOST */ 246 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x100 247 >; 248 }; 249 250 uart2_pins: pinctrl-uart2-grp { 251 fsl,pins = < 252 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 253 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 254 >; 255 }; 256 257 usdhc1_pins: pinctrl-usdhc1-grp { 258 fsl,pins = < 259 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 260 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 261 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 262 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 263 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 264 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 265 /* wifi refclk */ 266 MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x0 267 /* WL_REG_ON */ 268 MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0 269 /* WL_WAKE_HOST */ 270 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x100 271 >; 272 }; 273 274 usdhc3_100mhz_pins: pinctrl-usdhc3-100mhz-grp { 275 fsl,pins = < 276 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 277 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 278 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 279 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 280 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 281 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 282 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 283 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 284 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 285 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 286 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 287 >; 288 }; 289 290 usdhc3_200mhz_pins: pinctrl-usdhc3-200mhz-grp { 291 fsl,pins = < 292 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 293 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 294 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 295 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 296 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 297 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 298 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 299 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 300 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 301 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 302 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 303 >; 304 }; 305 306 usdhc3_pins: pinctrl-usdhc3-grp { 307 fsl,pins = < 308 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 309 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 310 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 311 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 312 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 313 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 314 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 315 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 316 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 317 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 318 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 319 >; 320 }; 321 322 wdog1_pins: pinctrl-wdog1-grp { 323 fsl,pins = < 324 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x140 325 >; 326 }; 327}; 328 329/* assembly-option for AI accelerator on SoM, otherwise routed to carrier */ 330&pcie0 { 331 pinctrl-0 = <&pcie_pins>; 332 pinctrl-names = "default"; 333 reset-gpios = <&gpio1 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; 334 status = "okay"; 335}; 336 337&pcie_phy { 338 fsl,clkreq-unsupported; 339 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 340 status = "okay"; 341}; 342 343&uart1 { 344 /* select 80MHz parent clock to support maximum baudrate 4Mbps */ 345 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 346 assigned-clocks = <&clk IMX8MM_CLK_UART1>; 347 pinctrl-0 = <&uart1_pins>; 348 pinctrl-names = "default"; 349 uart-has-rtscts; 350 status = "okay"; 351 352 bluetooth { 353 compatible = "brcm,bcm4330-bt"; 354 device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; 355 host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; 356 max-speed = <3000000>; 357 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; 358 }; 359}; 360 361&uart2 { 362 pinctrl-0 = <&uart2_pins>; 363 pinctrl-names = "default"; 364 status = "okay"; 365}; 366 367&usdhc1 { 368 bus-width = <4>; 369 mmc-pwrseq = <&usdhc1_pwrseq>; 370 pinctrl-0 = <&usdhc1_pins>; 371 pinctrl-names = "default"; 372 vmmc-supply = <&v_3_3>; 373 vqmmc-supply = <&v_1_8>; 374 status = "okay"; 375}; 376 377&usdhc3 { 378 bus-width = <8>; 379 non-removable; 380 pinctrl-0 = <&usdhc3_pins>; 381 pinctrl-1 = <&usdhc3_100mhz_pins>; 382 pinctrl-2 = <&usdhc3_200mhz_pins>; 383 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 384 vmmc-supply = <&v_3_3>; 385 vqmmc-supply = <&v_1_8>; 386 status = "okay"; 387}; 388 389&wdog1 { 390 pinctrl-0 = <&wdog1_pins>; 391 pinctrl-names = "default"; 392 status = "okay"; 393}; 394