1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2// 3// Device Tree file describing the PCIe Mobiveil's GPEX 4.0 IP 4// found on LX2160A Rev1 5// 6// Copyright 2026 NXP 7 8&soc { 9 pcie1: pcie@3400000 { 10 compatible = "fsl,lx2160a-pcie"; 11 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 12 <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ 13 reg-names = "csr_axi_slave", "config_axi_slave"; 14 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 15 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 16 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 17 interrupt-names = "aer", "pme", "intr"; 18 #address-cells = <3>; 19 #size-cells = <2>; 20 device_type = "pci"; 21 dma-coherent; 22 apio-wins = <8>; 23 ppio-wins = <8>; 24 bus-range = <0x0 0xff>; 25 ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 26 msi-parent = <&its 0>; 27 #interrupt-cells = <1>; 28 interrupt-map-mask = <0 0 0 7>; 29 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 30 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 31 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 32 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 33 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 34 status = "disabled"; 35 }; 36 37 pcie2: pcie@3500000 { 38 compatible = "fsl,lx2160a-pcie"; 39 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 40 <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ 41 reg-names = "csr_axi_slave", "config_axi_slave"; 42 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 43 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 44 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 45 interrupt-names = "aer", "pme", "intr"; 46 #address-cells = <3>; 47 #size-cells = <2>; 48 device_type = "pci"; 49 dma-coherent; 50 apio-wins = <8>; 51 ppio-wins = <8>; 52 bus-range = <0x0 0xff>; 53 ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 54 msi-parent = <&its 0>; 55 #interrupt-cells = <1>; 56 interrupt-map-mask = <0 0 0 7>; 57 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 58 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 59 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 60 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 61 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 62 status = "disabled"; 63 }; 64 65 pcie3: pcie@3600000 { 66 compatible = "fsl,lx2160a-pcie"; 67 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ 68 <0x90 0x00000000 0x0 0x00002000>; /* configuration space */ 69 reg-names = "csr_axi_slave", "config_axi_slave"; 70 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 71 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 72 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 73 interrupt-names = "aer", "pme", "intr"; 74 #address-cells = <3>; 75 #size-cells = <2>; 76 device_type = "pci"; 77 dma-coherent; 78 apio-wins = <256>; 79 ppio-wins = <24>; 80 bus-range = <0x0 0xff>; 81 ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 82 msi-parent = <&its 0>; 83 #interrupt-cells = <1>; 84 interrupt-map-mask = <0 0 0 7>; 85 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 86 <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 87 <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 88 <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 89 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 90 status = "disabled"; 91 }; 92 93 pcie4: pcie@3700000 { 94 compatible = "fsl,lx2160a-pcie"; 95 reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */ 96 <0x98 0x00000000 0x0 0x00002000>; /* configuration space */ 97 reg-names = "csr_axi_slave", "config_axi_slave"; 98 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 99 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 100 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 101 interrupt-names = "aer", "pme", "intr"; 102 #address-cells = <3>; 103 #size-cells = <2>; 104 device_type = "pci"; 105 dma-coherent; 106 apio-wins = <8>; 107 ppio-wins = <8>; 108 bus-range = <0x0 0xff>; 109 ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 110 msi-parent = <&its 0>; 111 #interrupt-cells = <1>; 112 interrupt-map-mask = <0 0 0 7>; 113 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 114 <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 115 <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 116 <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 117 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 118 status = "disabled"; 119 }; 120 121 pcie5: pcie@3800000 { 122 compatible = "fsl,lx2160a-pcie"; 123 reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */ 124 <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ 125 reg-names = "csr_axi_slave", "config_axi_slave"; 126 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 127 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 128 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 129 interrupt-names = "aer", "pme", "intr"; 130 #address-cells = <3>; 131 #size-cells = <2>; 132 device_type = "pci"; 133 dma-coherent; 134 apio-wins = <256>; 135 ppio-wins = <24>; 136 bus-range = <0x0 0xff>; 137 ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 138 msi-parent = <&its 0>; 139 #interrupt-cells = <1>; 140 interrupt-map-mask = <0 0 0 7>; 141 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 142 <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 143 <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 144 <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 145 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 146 status = "disabled"; 147 }; 148 149 pcie6: pcie@3900000 { 150 compatible = "fsl,lx2160a-pcie"; 151 reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */ 152 <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ 153 reg-names = "csr_axi_slave", "config_axi_slave"; 154 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 155 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 156 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 157 interrupt-names = "aer", "pme", "intr"; 158 #address-cells = <3>; 159 #size-cells = <2>; 160 device_type = "pci"; 161 dma-coherent; 162 apio-wins = <8>; 163 ppio-wins = <8>; 164 bus-range = <0x0 0xff>; 165 ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 166 msi-parent = <&its 0>; 167 #interrupt-cells = <1>; 168 interrupt-map-mask = <0 0 0 7>; 169 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 170 <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 171 <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 172 <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 173 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 174 status = "disabled"; 175 }; 176}; 177