1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2/* 3 * Copyright (c) 2018-2025 TQ-Systems GmbH <linux@ew.tq-group.com>, 4 * D-82229 Seefeld, Germany. 5 * Author: Matthias Schiffer 6 * Author: Max Merchel 7 */ 8 9/dts-v1/; 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/input/input.h> 13#include <dt-bindings/leds/common.h> 14#include <dt-bindings/net/ti-dp83867.h> 15#include "fsl-ls1012a-tqmls1012al.dtsi" 16 17/ { 18 model = "TQ-Systems TQMLS1012AL on MBLS1012AL"; 19 compatible = "tq,ls1012a-tqmls1012al-mbls1012al", "tq,ls1012a-tqmls1012al", "fsl,ls1012a"; 20 chassis-type = "embedded"; 21 22 aliases { 23 /* use MAC from U-Boot environment */ 24 /* TODO: PFE */ 25 ethernet2 = &swport0; 26 ethernet3 = &swport1; 27 ethernet4 = &swport2; 28 ethernet5 = &swport3; 29 serial0 = &duart0; 30 spi0 = &qspi; 31 }; 32 33 chosen { 34 stdout-path = &duart0; 35 }; 36 37 gpio-keys { 38 compatible = "gpio-keys"; 39 autorepeat; 40 41 switch-1 { 42 label = "S2"; 43 linux,code = <BTN_0>; 44 gpios = <&gpio_exp_3p3v 13 GPIO_ACTIVE_LOW>; 45 }; 46 47 switch-2 { 48 label = "X15"; 49 linux,code = <BTN_1>; 50 gpios = <&gpio_exp_1p8v 5 GPIO_ACTIVE_LOW>; 51 }; 52 53 switch-3 { 54 label = "X16"; 55 linux,code = <BTN_2>; 56 gpios = <&gpio_exp_1p8v 4 GPIO_ACTIVE_LOW>; 57 }; 58 }; 59 60 gpio-leds { 61 compatible = "gpio-leds"; 62 63 led-0 { 64 color = <LED_COLOR_ID_GREEN>; 65 function = LED_FUNCTION_HEARTBEAT; 66 gpios = <&gpio_exp_3p3v 14 GPIO_ACTIVE_LOW>; 67 linux,default-trigger = "heartbeat"; 68 }; 69 70 led-1 { 71 color = <LED_COLOR_ID_GREEN>; 72 function = LED_FUNCTION_STATUS; 73 gpios = <&gpio_exp_3p3v 15 GPIO_ACTIVE_LOW>; 74 linux,default-trigger = "default-on"; 75 }; 76 }; 77 78 reserved-memory { 79 #address-cells = <2>; 80 #size-cells = <2>; 81 ranges; 82 83 /* global autoconfigured region for contiguous allocations */ 84 linux,cma { 85 compatible = "shared-dma-pool"; 86 reusable; 87 /* 64 MiB */ 88 size = <0 0x04000000>; 89 /* 512 - 128 MiB, our minimum RAM config will be 512 MiB */ 90 alloc-ranges = <0 0x80000000 0 0x98000000>; 91 linux,cma-default; 92 }; 93 }; 94 95 reg_1v5: regulator-1v5 { 96 compatible = "regulator-fixed"; 97 regulator-name = "V_1V5"; 98 regulator-min-microvolt = <1500000>; 99 regulator-max-microvolt = <1500000>; 100 regulator-always-on; 101 }; 102 103 reg_1p5v_pcie: regulator-1p5v-pcie { 104 compatible = "regulator-fixed"; 105 regulator-name = "V_1V5_PCIE"; 106 regulator-min-microvolt = <1500000>; 107 regulator-max-microvolt = <1500000>; 108 regulator-always-on; 109 regulator-boot-on; 110 gpio = <&gpio_exp_1p8v 7 GPIO_ACTIVE_HIGH>; 111 enable-active-high; 112 vin-supply = <®_1v5>; 113 }; 114 115 reg_1p5v_wlan: regulator-1p5v-wlan { 116 compatible = "regulator-fixed"; 117 regulator-name = "V_1V5_WLAN"; 118 regulator-min-microvolt = <1500000>; 119 regulator-max-microvolt = <1500000>; 120 regulator-always-on; 121 regulator-boot-on; 122 gpio = <&gpio_exp_1p8v 6 GPIO_ACTIVE_HIGH>; 123 enable-active-high; 124 vin-supply = <®_1v5>; 125 }; 126 127 reg_1v8: regulator-1p8v { 128 compatible = "regulator-fixed"; 129 regulator-name = "V_1V8"; 130 regulator-min-microvolt = <1800000>; 131 regulator-max-microvolt = <1800000>; 132 regulator-always-on; 133 }; 134 135 reg_3v3: regulator-3p3v { 136 compatible = "regulator-fixed"; 137 regulator-name = "3P3V"; 138 regulator-min-microvolt = <3300000>; 139 regulator-max-microvolt = <3300000>; 140 regulator-always-on; 141 }; 142 143 reg_3v3_pcie: regulator-3v3-pcie { 144 compatible = "regulator-fixed"; 145 regulator-name = "V_3V3_PCIE"; 146 regulator-min-microvolt = <3300000>; 147 regulator-max-microvolt = <3300000>; 148 regulator-always-on; 149 regulator-boot-on; 150 gpio = <&gpio_exp_3p3v 3 GPIO_ACTIVE_HIGH>; 151 enable-active-high; 152 vin-supply = <®_3v3>; 153 }; 154 155 reg_3v3_wlan: regulator-3v3-wlan { 156 compatible = "regulator-fixed"; 157 regulator-name = "V_3V3_WLAN"; 158 regulator-min-microvolt = <3300000>; 159 regulator-max-microvolt = <3300000>; 160 regulator-always-on; 161 regulator-boot-on; 162 gpio = <&gpio_exp_3p3v 1 GPIO_ACTIVE_HIGH>; 163 enable-active-high; 164 vin-supply = <®_3v3>; 165 }; 166}; 167 168&duart0 { 169 status = "okay"; 170}; 171 172&esdhc0 { 173 vmmc-supply = <®_3v3>; 174 no-mmc; 175 no-sdio; 176 disable-wp; 177 sd-uhs-sdr12; 178 sd-uhs-sdr25; 179 sd-uhs-sdr50; 180 sd-uhs-sdr104; 181 status = "okay"; 182}; 183 184&i2c0 { 185 gpio_exp_3p3v: gpio@20 { 186 compatible = "nxp,pca9555"; 187 reg = <0x20>; 188 gpio-controller; 189 #gpio-cells = <2>; 190 vcc-supply = <®_3v3>; 191 interrupt-parent = <&gpio0>; 192 interrupts = <24 IRQ_TYPE_EDGE_FALLING>; 193 interrupt-controller; 194 #interrupt-cells = <2>; 195 gpio-line-names = "", "", "GPIO_3V3_3", "", 196 "", "", "", "", 197 "", "GPIO_3V3_1", "GPIO_3V3_2", "", 198 "", "", "", ""; 199 200 wlan-disable-hog { 201 gpio-hog; 202 gpios = <0 GPIO_ACTIVE_HIGH>; 203 output-high; 204 line-name = "WLAN_DISABLE#"; 205 }; 206 207 pcie-rst-hog { 208 gpio-hog; 209 gpios = <4 GPIO_ACTIVE_HIGH>; 210 output-high; 211 line-name = "PCIE_RST#"; 212 }; 213 214 wlan-rst-hog { 215 gpio-hog; 216 gpios = <5 GPIO_ACTIVE_HIGH>; 217 output-high; 218 line-name = "WLAN_RST#"; 219 }; 220 221 pcie-dis-hog { 222 gpio-hog; 223 gpios = <11 GPIO_ACTIVE_HIGH>; 224 output-high; 225 line-name = "PCIE_DIS#"; 226 }; 227 228 pcie-wake-hog { 229 gpio-hog; 230 gpios = <12 GPIO_ACTIVE_HIGH>; 231 input; 232 line-name = "PCIE_WAKE#"; 233 }; 234 }; 235 236 lm75_48: temperature-sensor@48 { 237 compatible = "national,lm75a"; 238 reg = <0x48>; 239 vs-supply = <®_3v3>; 240 }; 241 242 switch@5f { 243 compatible = "microchip,ksz9897"; 244 reg = <0x5f>; 245 reset-gpios = <&gpio_exp_3p3v 7 GPIO_ACTIVE_LOW>; 246 247 ports { 248 #address-cells = <1>; 249 #size-cells = <0>; 250 251 swport0: port@0 { 252 reg = <0>; 253 label = "swp0"; 254 phy-mode = "internal"; 255 }; 256 257 swport1: port@1 { 258 reg = <1>; 259 label = "swp1"; 260 phy-mode = "internal"; 261 }; 262 263 swport2: port@2 { 264 reg = <2>; 265 label = "swp2"; 266 phy-mode = "internal"; 267 }; 268 269 swport3: port@3 { 270 reg = <3>; 271 label = "swp3"; 272 phy-mode = "internal"; 273 }; 274 275 port@6 { 276 reg = <6>; 277 label = "cpu"; 278 /* TODO: PFE */ 279 phy-mode = "rgmii-id"; 280 rx-internal-delay-ps = <1500>; 281 tx-internal-delay-ps = <1500>; 282 283 fixed-link { 284 speed = <1000>; 285 full-duplex; 286 }; 287 }; 288 }; 289 }; 290 291 gpio_exp_1p8v: gpio@70 { 292 compatible = "nxp,pca9538"; 293 reg = <0x70>; 294 gpio-controller; 295 #gpio-cells = <2>; 296 vcc-supply = <®_1v8>; 297 interrupt-parent = <&gpio0>; 298 interrupts = <27 IRQ_TYPE_EDGE_FALLING>; 299 interrupt-controller; 300 #interrupt-cells = <2>; 301 gpio-line-names = "PCIE_CLK_PD#", "PMIC_INT#", "ETH_SW_INT#", "", 302 "", "", "", "", 303 "", "GPIO_3V3_1", "GPIO_3V3_2", "", 304 "", "", "", ""; 305 306 /* do not change PCIE_CLK_PD */ 307 pcie-clk-pd-hog { 308 gpio-hog; 309 gpios = <0 GPIO_ACTIVE_HIGH>; 310 output-high; 311 line-name = "PCIE_CLK_PD#"; 312 }; 313 314 pmic-int-hog { 315 gpio-hog; 316 gpios = <1 GPIO_ACTIVE_HIGH>; 317 input; 318 line-name = "PMIC_INT#"; 319 }; 320 321 eth-sw-int-hog { 322 gpio-hog; 323 gpios = <2 GPIO_ACTIVE_HIGH>; 324 input; 325 line-name = "ETH_SW_INT#"; 326 }; 327 328 eth-link-pwrdwn-hog { 329 gpio-hog; 330 gpios = <3 GPIO_ACTIVE_HIGH>; 331 input; 332 line-name = "ETH_LINK_PWRDWN#"; 333 }; 334 }; 335}; 336 337&pcie1 { 338 status = "okay"; 339}; 340 341/* TODO: PFE */ 342 343&sata { 344 status = "okay"; 345}; 346 347&usb0 { 348 #address-cells = <1>; 349 #size-cells = <0>; 350 351 hub_2_0: hub@1 { 352 compatible = "usb451,8142"; 353 reg = <1>; 354 peer-hub = <&hub_3_0>; 355 reset-gpios = <&gpio_exp_3p3v 6 GPIO_ACTIVE_LOW>; 356 vdd-supply = <®_vcc_3v3>; 357 }; 358 359 hub_3_0: hub@2 { 360 compatible = "usb451,8140"; 361 reg = <2>; 362 peer-hub = <&hub_2_0>; 363 reset-gpios = <&gpio_exp_3p3v 6 GPIO_ACTIVE_LOW>; 364 vdd-supply = <®_vcc_3v3>; 365 }; 366}; 367