1*639f8e36SSungMin Park// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*639f8e36SSungMin Park/* 3*639f8e36SSungMin Park * Axis ARTPEC-8 SoC device tree source 4*639f8e36SSungMin Park * 5*639f8e36SSungMin Park * Copyright (c) 2025 Samsung Electronics Co., Ltd. 6*639f8e36SSungMin Park * https://www.samsung.com 7*639f8e36SSungMin Park * Copyright (c) 2025 Axis Communications AB. 8*639f8e36SSungMin Park * https://www.axis.com 9*639f8e36SSungMin Park */ 10*639f8e36SSungMin Park 11*639f8e36SSungMin Park#include <dt-bindings/interrupt-controller/arm-gic.h> 12*639f8e36SSungMin Park#include <dt-bindings/clock/axis,artpec8-clk.h> 13*639f8e36SSungMin Park 14*639f8e36SSungMin Park/ { 15*639f8e36SSungMin Park compatible = "axis,artpec8"; 16*639f8e36SSungMin Park interrupt-parent = <&gic>; 17*639f8e36SSungMin Park #address-cells = <2>; 18*639f8e36SSungMin Park #size-cells = <2>; 19*639f8e36SSungMin Park 20*639f8e36SSungMin Park aliases { 21*639f8e36SSungMin Park pinctrl0 = &pinctrl_fsys; 22*639f8e36SSungMin Park pinctrl1 = &pinctrl_peric; 23*639f8e36SSungMin Park }; 24*639f8e36SSungMin Park 25*639f8e36SSungMin Park cpus { 26*639f8e36SSungMin Park #address-cells = <1>; 27*639f8e36SSungMin Park #size-cells = <0>; 28*639f8e36SSungMin Park 29*639f8e36SSungMin Park cpu0: cpu@0 { 30*639f8e36SSungMin Park device_type = "cpu"; 31*639f8e36SSungMin Park compatible = "arm,cortex-a53"; 32*639f8e36SSungMin Park reg = <0x0>; 33*639f8e36SSungMin Park enable-method = "psci"; 34*639f8e36SSungMin Park cpu-idle-states = <&cpu_sleep>; 35*639f8e36SSungMin Park clocks = <&cmu_cpucl CLK_GOUT_CPUCL_CLUSTER_CPU>; 36*639f8e36SSungMin Park clock-names = "cpu"; 37*639f8e36SSungMin Park }; 38*639f8e36SSungMin Park 39*639f8e36SSungMin Park cpu1: cpu@1 { 40*639f8e36SSungMin Park device_type = "cpu"; 41*639f8e36SSungMin Park compatible = "arm,cortex-a53"; 42*639f8e36SSungMin Park reg = <0x1>; 43*639f8e36SSungMin Park enable-method = "psci"; 44*639f8e36SSungMin Park cpu-idle-states = <&cpu_sleep>; 45*639f8e36SSungMin Park }; 46*639f8e36SSungMin Park 47*639f8e36SSungMin Park cpu2: cpu@2 { 48*639f8e36SSungMin Park device_type = "cpu"; 49*639f8e36SSungMin Park compatible = "arm,cortex-a53"; 50*639f8e36SSungMin Park reg = <0x2>; 51*639f8e36SSungMin Park enable-method = "psci"; 52*639f8e36SSungMin Park cpu-idle-states = <&cpu_sleep>; 53*639f8e36SSungMin Park }; 54*639f8e36SSungMin Park 55*639f8e36SSungMin Park cpu3: cpu@3 { 56*639f8e36SSungMin Park device_type = "cpu"; 57*639f8e36SSungMin Park compatible = "arm,cortex-a53"; 58*639f8e36SSungMin Park reg = <0x3>; 59*639f8e36SSungMin Park enable-method = "psci"; 60*639f8e36SSungMin Park cpu-idle-states = <&cpu_sleep>; 61*639f8e36SSungMin Park }; 62*639f8e36SSungMin Park 63*639f8e36SSungMin Park idle-states { 64*639f8e36SSungMin Park entry-method = "psci"; 65*639f8e36SSungMin Park 66*639f8e36SSungMin Park cpu_sleep: cpu-sleep { 67*639f8e36SSungMin Park compatible = "arm,idle-state"; 68*639f8e36SSungMin Park arm,psci-suspend-param = <0x0010000>; 69*639f8e36SSungMin Park local-timer-stop; 70*639f8e36SSungMin Park entry-latency-us = <300>; 71*639f8e36SSungMin Park exit-latency-us = <1200>; 72*639f8e36SSungMin Park min-residency-us = <2000>; 73*639f8e36SSungMin Park }; 74*639f8e36SSungMin Park }; 75*639f8e36SSungMin Park }; 76*639f8e36SSungMin Park 77*639f8e36SSungMin Park fin_pll: clock-finpll { 78*639f8e36SSungMin Park compatible = "fixed-factor-clock"; 79*639f8e36SSungMin Park clocks = <&osc_clk>; 80*639f8e36SSungMin Park #clock-cells = <0>; 81*639f8e36SSungMin Park clock-div = <2>; 82*639f8e36SSungMin Park clock-mult = <1>; 83*639f8e36SSungMin Park clock-output-names = "fin_pll"; 84*639f8e36SSungMin Park }; 85*639f8e36SSungMin Park 86*639f8e36SSungMin Park osc_clk: clock-osc { 87*639f8e36SSungMin Park /* XXTI */ 88*639f8e36SSungMin Park compatible = "fixed-clock"; 89*639f8e36SSungMin Park #clock-cells = <0>; 90*639f8e36SSungMin Park clock-output-names = "osc_clk"; 91*639f8e36SSungMin Park }; 92*639f8e36SSungMin Park 93*639f8e36SSungMin Park pmu { 94*639f8e36SSungMin Park compatible = "arm,cortex-a53-pmu"; 95*639f8e36SSungMin Park interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 96*639f8e36SSungMin Park <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 97*639f8e36SSungMin Park <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 98*639f8e36SSungMin Park <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 99*639f8e36SSungMin Park interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 100*639f8e36SSungMin Park }; 101*639f8e36SSungMin Park 102*639f8e36SSungMin Park psci { 103*639f8e36SSungMin Park compatible = "arm,psci-0.2"; 104*639f8e36SSungMin Park method = "smc"; 105*639f8e36SSungMin Park }; 106*639f8e36SSungMin Park 107*639f8e36SSungMin Park soc: soc@0 { 108*639f8e36SSungMin Park compatible = "simple-bus"; 109*639f8e36SSungMin Park ranges = <0x0 0x0 0x0 0x17000000>; 110*639f8e36SSungMin Park #address-cells = <1>; 111*639f8e36SSungMin Park #size-cells = <1>; 112*639f8e36SSungMin Park 113*639f8e36SSungMin Park cmu_imem: clock-controller@10010000 { 114*639f8e36SSungMin Park compatible = "axis,artpec8-cmu-imem"; 115*639f8e36SSungMin Park reg = <0x10010000 0x4000>; 116*639f8e36SSungMin Park #clock-cells = <1>; 117*639f8e36SSungMin Park clocks = <&fin_pll>, 118*639f8e36SSungMin Park <&cmu_cmu CLK_DOUT_CMU_IMEM_ACLK>, 119*639f8e36SSungMin Park <&cmu_cmu CLK_DOUT_CMU_IMEM_JPEG>; 120*639f8e36SSungMin Park clock-names = "fin_pll", "aclk", "jpeg"; 121*639f8e36SSungMin Park }; 122*639f8e36SSungMin Park 123*639f8e36SSungMin Park timer@10040000 { 124*639f8e36SSungMin Park compatible = "axis,artpec8-mct", "samsung,exynos4210-mct"; 125*639f8e36SSungMin Park reg = <0x10040000 0x1000>; 126*639f8e36SSungMin Park clocks = <&fin_pll>, <&cmu_imem CLK_GOUT_IMEM_MCT_PCLK>; 127*639f8e36SSungMin Park clock-names = "fin_pll", "mct"; 128*639f8e36SSungMin Park interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 129*639f8e36SSungMin Park <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 130*639f8e36SSungMin Park <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 131*639f8e36SSungMin Park <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 132*639f8e36SSungMin Park <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 133*639f8e36SSungMin Park <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 134*639f8e36SSungMin Park <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 135*639f8e36SSungMin Park <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 136*639f8e36SSungMin Park <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 137*639f8e36SSungMin Park <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 138*639f8e36SSungMin Park <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 139*639f8e36SSungMin Park <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 140*639f8e36SSungMin Park }; 141*639f8e36SSungMin Park 142*639f8e36SSungMin Park gic: interrupt-controller@10201000 { 143*639f8e36SSungMin Park compatible = "arm,gic-400"; 144*639f8e36SSungMin Park reg = <0x10201000 0x1000>, 145*639f8e36SSungMin Park <0x10202000 0x2000>, 146*639f8e36SSungMin Park <0x10204000 0x2000>, 147*639f8e36SSungMin Park <0x10206000 0x2000>; 148*639f8e36SSungMin Park #interrupt-cells = <3>; 149*639f8e36SSungMin Park interrupt-controller; 150*639f8e36SSungMin Park interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 151*639f8e36SSungMin Park }; 152*639f8e36SSungMin Park 153*639f8e36SSungMin Park cmu_cpucl: clock-controller@11410000 { 154*639f8e36SSungMin Park compatible = "axis,artpec8-cmu-cpucl"; 155*639f8e36SSungMin Park reg = <0x11410000 0x4000>; 156*639f8e36SSungMin Park #clock-cells = <1>; 157*639f8e36SSungMin Park clocks = <&fin_pll>, 158*639f8e36SSungMin Park <&cmu_cmu CLK_DOUT_CMU_CPUCL_SWITCH>; 159*639f8e36SSungMin Park clock-names = "fin_pll", "switch"; 160*639f8e36SSungMin Park }; 161*639f8e36SSungMin Park 162*639f8e36SSungMin Park cmu_cmu: clock-controller@12400000 { 163*639f8e36SSungMin Park compatible = "axis,artpec8-cmu-cmu"; 164*639f8e36SSungMin Park reg = <0x12400000 0x4000>; 165*639f8e36SSungMin Park #clock-cells = <1>; 166*639f8e36SSungMin Park clocks = <&fin_pll>; 167*639f8e36SSungMin Park clock-names = "fin_pll"; 168*639f8e36SSungMin Park }; 169*639f8e36SSungMin Park 170*639f8e36SSungMin Park cmu_core: clock-controller@12410000 { 171*639f8e36SSungMin Park compatible = "axis,artpec8-cmu-core"; 172*639f8e36SSungMin Park reg = <0x12410000 0x4000>; 173*639f8e36SSungMin Park #clock-cells = <1>; 174*639f8e36SSungMin Park clocks = <&fin_pll>, 175*639f8e36SSungMin Park <&cmu_cmu CLK_DOUT_CMU_CORE_MAIN>, 176*639f8e36SSungMin Park <&cmu_cmu CLK_DOUT_CMU_CORE_DLP>; 177*639f8e36SSungMin Park clock-names = "fin_pll", "main", "dlp"; 178*639f8e36SSungMin Park }; 179*639f8e36SSungMin Park 180*639f8e36SSungMin Park cmu_bus: clock-controller@12c10000 { 181*639f8e36SSungMin Park compatible = "axis,artpec8-cmu-bus"; 182*639f8e36SSungMin Park reg = <0x12c10000 0x4000>; 183*639f8e36SSungMin Park #clock-cells = <1>; 184*639f8e36SSungMin Park clocks = <&fin_pll>, 185*639f8e36SSungMin Park <&cmu_cmu CLK_DOUT_CMU_BUS>, 186*639f8e36SSungMin Park <&cmu_cmu CLK_DOUT_CMU_BUS_DLP>; 187*639f8e36SSungMin Park clock-names = "fin_pll", "bus", "dlp"; 188*639f8e36SSungMin Park }; 189*639f8e36SSungMin Park 190*639f8e36SSungMin Park cmu_peri: clock-controller@16410000 { 191*639f8e36SSungMin Park compatible = "axis,artpec8-cmu-peri"; 192*639f8e36SSungMin Park reg = <0x16410000 0x4000>; 193*639f8e36SSungMin Park #clock-cells = <1>; 194*639f8e36SSungMin Park clocks = <&fin_pll>, 195*639f8e36SSungMin Park <&cmu_cmu CLK_DOUT_CMU_PERI_IP>, 196*639f8e36SSungMin Park <&cmu_cmu CLK_DOUT_CMU_PERI_AUDIO>, 197*639f8e36SSungMin Park <&cmu_cmu CLK_DOUT_CMU_PERI_DISP>; 198*639f8e36SSungMin Park clock-names = "fin_pll", "ip", "audio", "disp"; 199*639f8e36SSungMin Park }; 200*639f8e36SSungMin Park 201*639f8e36SSungMin Park pinctrl_peric: pinctrl@165f0000 { 202*639f8e36SSungMin Park compatible = "axis,artpec8-pinctrl"; 203*639f8e36SSungMin Park reg = <0x165f0000 0x1000>; 204*639f8e36SSungMin Park interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 205*639f8e36SSungMin Park }; 206*639f8e36SSungMin Park 207*639f8e36SSungMin Park cmu_fsys: clock-controller@16c10000 { 208*639f8e36SSungMin Park compatible = "axis,artpec8-cmu-fsys"; 209*639f8e36SSungMin Park reg = <0x16c10000 0x4000>; 210*639f8e36SSungMin Park #clock-cells = <1>; 211*639f8e36SSungMin Park clocks = <&fin_pll>, 212*639f8e36SSungMin Park <&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN0>, 213*639f8e36SSungMin Park <&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN1>, 214*639f8e36SSungMin Park <&cmu_cmu CLK_DOUT_CMU_FSYS_BUS>, 215*639f8e36SSungMin Park <&cmu_cmu CLK_DOUT_CMU_FSYS_IP>; 216*639f8e36SSungMin Park clock-names = "fin_pll", "scan0", "scan1", "bus", "ip"; 217*639f8e36SSungMin Park }; 218*639f8e36SSungMin Park 219*639f8e36SSungMin Park pinctrl_fsys: pinctrl@16c30000 { 220*639f8e36SSungMin Park compatible = "axis,artpec8-pinctrl"; 221*639f8e36SSungMin Park reg = <0x16c30000 0x1000>; 222*639f8e36SSungMin Park interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 223*639f8e36SSungMin Park }; 224*639f8e36SSungMin Park 225*639f8e36SSungMin Park serial_0: serial@16cc0000 { 226*639f8e36SSungMin Park compatible = "axis,artpec8-uart"; 227*639f8e36SSungMin Park reg = <0x16cc0000 0x100>; 228*639f8e36SSungMin Park clocks = <&cmu_fsys CLK_GOUT_FSYS_UART0_PCLK>, 229*639f8e36SSungMin Park <&cmu_fsys CLK_GOUT_FSYS_UART0_SCLK_UART>; 230*639f8e36SSungMin Park clock-names = "uart", "clk_uart_baud0"; 231*639f8e36SSungMin Park interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 232*639f8e36SSungMin Park pinctrl-names = "default"; 233*639f8e36SSungMin Park pinctrl-0 = <&serial0_bus>; 234*639f8e36SSungMin Park }; 235*639f8e36SSungMin Park }; 236*639f8e36SSungMin Park 237*639f8e36SSungMin Park timer { 238*639f8e36SSungMin Park compatible = "arm,armv8-timer"; 239*639f8e36SSungMin Park interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 240*639f8e36SSungMin Park <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 241*639f8e36SSungMin Park <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 242*639f8e36SSungMin Park <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 243*639f8e36SSungMin Park }; 244*639f8e36SSungMin Park}; 245