1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Axis ARTPEC-8 SoC device tree source 4 * 5 * Copyright (c) 2025 Samsung Electronics Co., Ltd. 6 * https://www.samsung.com 7 * Copyright (c) 2025 Axis Communications AB. 8 * https://www.axis.com 9 */ 10 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/clock/axis,artpec8-clk.h> 13 14/ { 15 compatible = "axis,artpec8"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 pinctrl0 = &pinctrl_fsys; 22 pinctrl1 = &pinctrl_peric; 23 }; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu0: cpu@0 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a53"; 32 reg = <0x0>; 33 enable-method = "psci"; 34 cpu-idle-states = <&cpu_sleep>; 35 clocks = <&cmu_cpucl CLK_GOUT_CPUCL_CLUSTER_CPU>; 36 clock-names = "cpu"; 37 }; 38 39 cpu1: cpu@1 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53"; 42 reg = <0x1>; 43 enable-method = "psci"; 44 cpu-idle-states = <&cpu_sleep>; 45 }; 46 47 cpu2: cpu@2 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a53"; 50 reg = <0x2>; 51 enable-method = "psci"; 52 cpu-idle-states = <&cpu_sleep>; 53 }; 54 55 cpu3: cpu@3 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a53"; 58 reg = <0x3>; 59 enable-method = "psci"; 60 cpu-idle-states = <&cpu_sleep>; 61 }; 62 63 idle-states { 64 entry-method = "psci"; 65 66 cpu_sleep: cpu-sleep { 67 compatible = "arm,idle-state"; 68 arm,psci-suspend-param = <0x0010000>; 69 local-timer-stop; 70 entry-latency-us = <300>; 71 exit-latency-us = <1200>; 72 min-residency-us = <2000>; 73 }; 74 }; 75 }; 76 77 fin_pll: clock-finpll { 78 compatible = "fixed-factor-clock"; 79 clocks = <&osc_clk>; 80 #clock-cells = <0>; 81 clock-div = <2>; 82 clock-mult = <1>; 83 clock-output-names = "fin_pll"; 84 }; 85 86 osc_clk: clock-osc { 87 /* XXTI */ 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 clock-output-names = "osc_clk"; 91 }; 92 93 pmu { 94 compatible = "arm,cortex-a53-pmu"; 95 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 99 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 100 }; 101 102 psci { 103 compatible = "arm,psci-0.2"; 104 method = "smc"; 105 }; 106 107 soc: soc@0 { 108 compatible = "simple-bus"; 109 ranges = <0x0 0x0 0x0 0x17000000>; 110 #address-cells = <1>; 111 #size-cells = <1>; 112 113 cmu_imem: clock-controller@10010000 { 114 compatible = "axis,artpec8-cmu-imem"; 115 reg = <0x10010000 0x4000>; 116 #clock-cells = <1>; 117 clocks = <&fin_pll>, 118 <&cmu_cmu CLK_DOUT_CMU_IMEM_ACLK>, 119 <&cmu_cmu CLK_DOUT_CMU_IMEM_JPEG>; 120 clock-names = "fin_pll", "aclk", "jpeg"; 121 }; 122 123 timer@10040000 { 124 compatible = "axis,artpec8-mct", "samsung,exynos4210-mct"; 125 reg = <0x10040000 0x1000>; 126 clocks = <&fin_pll>, <&cmu_imem CLK_GOUT_IMEM_MCT_PCLK>; 127 clock-names = "fin_pll", "mct"; 128 interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 140 }; 141 142 gic: interrupt-controller@10201000 { 143 compatible = "arm,gic-400"; 144 reg = <0x10201000 0x1000>, 145 <0x10202000 0x2000>, 146 <0x10204000 0x2000>, 147 <0x10206000 0x2000>; 148 #interrupt-cells = <3>; 149 interrupt-controller; 150 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 151 }; 152 153 cmu_cpucl: clock-controller@11410000 { 154 compatible = "axis,artpec8-cmu-cpucl"; 155 reg = <0x11410000 0x4000>; 156 #clock-cells = <1>; 157 clocks = <&fin_pll>, 158 <&cmu_cmu CLK_DOUT_CMU_CPUCL_SWITCH>; 159 clock-names = "fin_pll", "switch"; 160 }; 161 162 cmu_cmu: clock-controller@12400000 { 163 compatible = "axis,artpec8-cmu-cmu"; 164 reg = <0x12400000 0x4000>; 165 #clock-cells = <1>; 166 clocks = <&fin_pll>; 167 clock-names = "fin_pll"; 168 }; 169 170 cmu_core: clock-controller@12410000 { 171 compatible = "axis,artpec8-cmu-core"; 172 reg = <0x12410000 0x4000>; 173 #clock-cells = <1>; 174 clocks = <&fin_pll>, 175 <&cmu_cmu CLK_DOUT_CMU_CORE_MAIN>, 176 <&cmu_cmu CLK_DOUT_CMU_CORE_DLP>; 177 clock-names = "fin_pll", "main", "dlp"; 178 }; 179 180 cmu_bus: clock-controller@12c10000 { 181 compatible = "axis,artpec8-cmu-bus"; 182 reg = <0x12c10000 0x4000>; 183 #clock-cells = <1>; 184 clocks = <&fin_pll>, 185 <&cmu_cmu CLK_DOUT_CMU_BUS>, 186 <&cmu_cmu CLK_DOUT_CMU_BUS_DLP>; 187 clock-names = "fin_pll", "bus", "dlp"; 188 }; 189 190 cmu_peri: clock-controller@16410000 { 191 compatible = "axis,artpec8-cmu-peri"; 192 reg = <0x16410000 0x4000>; 193 #clock-cells = <1>; 194 clocks = <&fin_pll>, 195 <&cmu_cmu CLK_DOUT_CMU_PERI_IP>, 196 <&cmu_cmu CLK_DOUT_CMU_PERI_AUDIO>, 197 <&cmu_cmu CLK_DOUT_CMU_PERI_DISP>; 198 clock-names = "fin_pll", "ip", "audio", "disp"; 199 }; 200 201 pinctrl_peric: pinctrl@165f0000 { 202 compatible = "axis,artpec8-pinctrl"; 203 reg = <0x165f0000 0x1000>; 204 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 205 }; 206 207 cmu_fsys: clock-controller@16c10000 { 208 compatible = "axis,artpec8-cmu-fsys"; 209 reg = <0x16c10000 0x4000>; 210 #clock-cells = <1>; 211 clocks = <&fin_pll>, 212 <&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN0>, 213 <&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN1>, 214 <&cmu_cmu CLK_DOUT_CMU_FSYS_BUS>, 215 <&cmu_cmu CLK_DOUT_CMU_FSYS_IP>; 216 clock-names = "fin_pll", "scan0", "scan1", "bus", "ip"; 217 }; 218 219 pinctrl_fsys: pinctrl@16c30000 { 220 compatible = "axis,artpec8-pinctrl"; 221 reg = <0x16c30000 0x1000>; 222 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 223 }; 224 225 serial_0: serial@16cc0000 { 226 compatible = "axis,artpec8-uart"; 227 reg = <0x16cc0000 0x100>; 228 clocks = <&cmu_fsys CLK_GOUT_FSYS_UART0_PCLK>, 229 <&cmu_fsys CLK_GOUT_FSYS_UART0_SCLK_UART>; 230 clock-names = "uart", "clk_uart_baud0"; 231 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 232 pinctrl-names = "default"; 233 pinctrl-0 = <&serial0_bus>; 234 }; 235 }; 236 237 timer { 238 compatible = "arm,armv8-timer"; 239 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 240 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 241 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 242 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 243 }; 244}; 245