1*639f8e36SSungMin Park /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2*639f8e36SSungMin Park /* 3*639f8e36SSungMin Park * Axis ARTPEC-8 SoC device tree pinctrl constants 4*639f8e36SSungMin Park * 5*639f8e36SSungMin Park * Copyright (c) 2025 Samsung Electronics Co., Ltd. 6*639f8e36SSungMin Park * https://www.samsung.com 7*639f8e36SSungMin Park * Copyright (c) 2025 Axis Communications AB. 8*639f8e36SSungMin Park * https://www.axis.com 9*639f8e36SSungMin Park */ 10*639f8e36SSungMin Park 11*639f8e36SSungMin Park #ifndef __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ 12*639f8e36SSungMin Park #define __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ 13*639f8e36SSungMin Park 14*639f8e36SSungMin Park #define ARTPEC_PIN_PULL_NONE 0 15*639f8e36SSungMin Park #define ARTPEC_PIN_PULL_DOWN 1 16*639f8e36SSungMin Park #define ARTPEC_PIN_PULL_UP 3 17*639f8e36SSungMin Park 18*639f8e36SSungMin Park #define ARTPEC_PIN_FUNC_INPUT 0 19*639f8e36SSungMin Park #define ARTPEC_PIN_FUNC_OUTPUT 1 20*639f8e36SSungMin Park #define ARTPEC_PIN_FUNC_2 2 21*639f8e36SSungMin Park #define ARTPEC_PIN_FUNC_3 3 22*639f8e36SSungMin Park #define ARTPEC_PIN_FUNC_4 4 23*639f8e36SSungMin Park #define ARTPEC_PIN_FUNC_5 5 24*639f8e36SSungMin Park #define ARTPEC_PIN_FUNC_6 6 25*639f8e36SSungMin Park #define ARTPEC_PIN_FUNC_EINT 0xf 26*639f8e36SSungMin Park #define ARTPEC_PIN_FUNC_F ARTPEC_PIN_FUNC_EINT 27*639f8e36SSungMin Park 28*639f8e36SSungMin Park /* Drive strength for ARTPEC */ 29*639f8e36SSungMin Park #define ARTPEC_PIN_DRV_SR1 0x8 30*639f8e36SSungMin Park #define ARTPEC_PIN_DRV_SR2 0x9 31*639f8e36SSungMin Park #define ARTPEC_PIN_DRV_SR3 0xa 32*639f8e36SSungMin Park #define ARTPEC_PIN_DRV_SR4 0xb 33*639f8e36SSungMin Park #define ARTPEC_PIN_DRV_SR5 0xc 34*639f8e36SSungMin Park #define ARTPEC_PIN_DRV_SR6 0xd 35*639f8e36SSungMin Park 36*639f8e36SSungMin Park #endif /* __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ */ 37