1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 /* 3 * Axis ARTPEC-8 SoC device tree pinctrl constants 4 * 5 * Copyright (c) 2025 Samsung Electronics Co., Ltd. 6 * https://www.samsung.com 7 * Copyright (c) 2025 Axis Communications AB. 8 * https://www.axis.com 9 */ 10 11 #ifndef __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ 12 #define __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ 13 14 #define ARTPEC_PIN_PULL_NONE 0 15 #define ARTPEC_PIN_PULL_DOWN 1 16 #define ARTPEC_PIN_PULL_UP 3 17 18 #define ARTPEC_PIN_FUNC_INPUT 0 19 #define ARTPEC_PIN_FUNC_OUTPUT 1 20 #define ARTPEC_PIN_FUNC_2 2 21 #define ARTPEC_PIN_FUNC_3 3 22 #define ARTPEC_PIN_FUNC_4 4 23 #define ARTPEC_PIN_FUNC_5 5 24 #define ARTPEC_PIN_FUNC_6 6 25 #define ARTPEC_PIN_FUNC_EINT 0xf 26 #define ARTPEC_PIN_FUNC_F ARTPEC_PIN_FUNC_EINT 27 28 /* Drive strength for ARTPEC */ 29 #define ARTPEC_PIN_DRV_SR1 0x8 30 #define ARTPEC_PIN_DRV_SR2 0x9 31 #define ARTPEC_PIN_DRV_SR3 0xa 32 #define ARTPEC_PIN_DRV_SR4 0xb 33 #define ARTPEC_PIN_DRV_SR5 0xc 34 #define ARTPEC_PIN_DRV_SR6 0xd 35 36 #endif /* __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ */ 37