1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for AST27xx SoC Family 4 * 5 * Copyright (C) 2026 ASPEED Technology Inc. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9 10/ { 11 compatible = "aspeed,ast2700"; 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus { 17 #address-cells = <2>; 18 #size-cells = <0>; 19 20 cpu0: cpu@0 { 21 device_type = "cpu"; 22 compatible = "arm,cortex-a35"; 23 reg = <0x0 0x0>; 24 enable-method = "psci"; 25 i-cache-size = <0x8000>; 26 i-cache-line-size = <64>; 27 i-cache-sets = <256>; 28 d-cache-size = <0x8000>; 29 d-cache-line-size = <64>; 30 d-cache-sets = <128>; 31 next-level-cache = <&l2>; 32 }; 33 34 cpu1: cpu@1 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-a35"; 37 reg = <0x0 0x1>; 38 enable-method = "psci"; 39 i-cache-size = <0x8000>; 40 i-cache-line-size = <64>; 41 i-cache-sets = <256>; 42 d-cache-size = <0x8000>; 43 d-cache-line-size = <64>; 44 d-cache-sets = <128>; 45 next-level-cache = <&l2>; 46 }; 47 48 cpu2: cpu@2 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a35"; 51 reg = <0x0 0x2>; 52 enable-method = "psci"; 53 i-cache-size = <0x8000>; 54 i-cache-line-size = <64>; 55 i-cache-sets = <256>; 56 d-cache-size = <0x8000>; 57 d-cache-line-size = <64>; 58 d-cache-sets = <128>; 59 next-level-cache = <&l2>; 60 }; 61 62 cpu3: cpu@3 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a35"; 65 reg = <0x0 0x3>; 66 enable-method = "psci"; 67 i-cache-size = <0x8000>; 68 i-cache-line-size = <64>; 69 i-cache-sets = <256>; 70 d-cache-size = <0x8000>; 71 d-cache-line-size = <64>; 72 d-cache-sets = <128>; 73 next-level-cache = <&l2>; 74 }; 75 76 l2: l2-cache0 { 77 compatible = "cache"; 78 cache-level = <2>; 79 cache-unified; 80 cache-size = <0x80000>; 81 cache-line-size = <64>; 82 cache-sets = <1024>; 83 }; 84 }; 85 86 secondary { 87 #address-cells = <1>; 88 #size-cells = <0>; 89 90 ssp_nvic: interrupt-controller@e000e100 { 91 compatible = "arm,v7m-nvic"; 92 #interrupt-cells = <2>; 93 #address-cells = <0>; 94 interrupt-controller; 95 reg = <0xe000e100>; 96 arm,num-irq-priority-bits = <3>; 97 status = "disabled"; 98 }; 99 }; 100 101 tertiary { 102 #address-cells = <1>; 103 #size-cells = <0>; 104 105 tsp_nvic: interrupt-controller@e000e100 { 106 compatible = "arm,v7m-nvic"; 107 #interrupt-cells = <2>; 108 #address-cells = <0>; 109 interrupt-controller; 110 reg = <0xe000e100>; 111 arm,num-irq-priority-bits = <3>; 112 status = "disabled"; 113 }; 114 }; 115 116 bootmcu { 117 bootmcu_hlic: interrupt-controller { 118 compatible = "riscv,cpu-intc"; 119 interrupt-controller; 120 #interrupt-cells = <1>; 121 status = "disabled"; 122 }; 123 }; 124 125 firmware { 126 optee: optee { 127 compatible = "linaro,optee-tz"; 128 method = "smc"; 129 }; 130 131 psci { 132 compatible = "arm,psci-1.0"; 133 method = "smc"; 134 }; 135 }; 136 137 reserved-memory { 138 #address-cells = <2>; 139 #size-cells = <2>; 140 ranges; 141 142 atf: trusted-firmware-a@430000000 { 143 reg = <0x4 0x30000000 0x0 0x80000>; 144 no-map; 145 }; 146 147 optee_core: optee-core@430080000 { 148 reg = <0x4 0x30080000 0x0 0x1000000>; 149 no-map; 150 }; 151 }; 152 153 arm-pmu { 154 compatible = "arm,cortex-a35-pmu"; 155 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 156 }; 157 158 timer { 159 compatible = "arm,armv8-timer"; 160 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 161 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 162 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 163 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 164 arm,cpu-registers-not-fw-configured; 165 always-on; 166 }; 167 168 gic: interrupt-controller@12200000 { 169 compatible = "arm,gic-v3"; 170 reg = <0 0x12200000 0 0x10000>, /* GICD */ 171 <0 0x12280000 0 0x80000>, /* GICR */ 172 <0 0x40440000 0 0x1000>; /* GICC */ 173 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 174 #interrupt-cells = <3>; 175 interrupt-controller; 176 }; 177 178 soc0: bus@10000000 { 179 compatible = "simple-bus"; 180 #address-cells = <2>; 181 #size-cells = <2>; 182 ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x4000000>; 183 }; 184 185 soc1: bus@14000000 { 186 compatible = "simple-bus"; 187 #address-cells = <2>; 188 #size-cells = <2>; 189 ranges = <0x0 0x14000000 0x0 0x14000000 0x2 0xec000000>; 190 }; 191}; 192 193#include "aspeed-g7-soc0.dtsi" 194#include "aspeed-g7-soc1.dtsi" 195