1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T8122 "M3" SoC 4 * 5 * Other names: H15G 6 * 7 * Copyright The Asahi Linux Contributors 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14#include <dt-bindings/phy/phy.h> 15#include <dt-bindings/spmi/spmi.h> 16 17/ { 18 compatible = "apple,t8122", "apple,arm-platform"; 19 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 cpus { 24 #address-cells = <2>; 25 #size-cells = <0>; 26 27 cpu-map { 28 cluster0 { 29 core0 { 30 cpu = <&cpu_e0>; 31 }; 32 core1 { 33 cpu = <&cpu_e1>; 34 }; 35 core2 { 36 cpu = <&cpu_e2>; 37 }; 38 core3 { 39 cpu = <&cpu_e3>; 40 }; 41 }; 42 43 cluster1 { 44 core0 { 45 cpu = <&cpu_p0>; 46 }; 47 core1 { 48 cpu = <&cpu_p1>; 49 }; 50 core2 { 51 cpu = <&cpu_p2>; 52 }; 53 core3 { 54 cpu = <&cpu_p3>; 55 }; 56 }; 57 }; 58 59 cpu_e0: cpu@0 { 60 compatible = "apple,sawtooth"; 61 device_type = "cpu"; 62 reg = <0x0 0x0>; 63 enable-method = "spin-table"; 64 cpu-release-addr = <0 0>; /* To be filled by loader */ 65 next-level-cache = <&l2_cache_0>; 66 i-cache-size = <0x20000>; 67 d-cache-size = <0x10000>; 68 }; 69 70 cpu_e1: cpu@1 { 71 compatible = "apple,sawtooth"; 72 device_type = "cpu"; 73 reg = <0x0 0x1>; 74 enable-method = "spin-table"; 75 cpu-release-addr = <0 0>; /* To be filled by loader */ 76 next-level-cache = <&l2_cache_0>; 77 i-cache-size = <0x20000>; 78 d-cache-size = <0x10000>; 79 }; 80 81 cpu_e2: cpu@2 { 82 compatible = "apple,sawtooth"; 83 device_type = "cpu"; 84 reg = <0x0 0x2>; 85 enable-method = "spin-table"; 86 cpu-release-addr = <0 0>; /* To be filled by loader */ 87 next-level-cache = <&l2_cache_0>; 88 i-cache-size = <0x20000>; 89 d-cache-size = <0x10000>; 90 }; 91 92 cpu_e3: cpu@3 { 93 compatible = "apple,sawtooth"; 94 device_type = "cpu"; 95 reg = <0x0 0x3>; 96 enable-method = "spin-table"; 97 cpu-release-addr = <0 0>; /* To be filled by loader */ 98 next-level-cache = <&l2_cache_0>; 99 i-cache-size = <0x20000>; 100 d-cache-size = <0x10000>; 101 }; 102 103 cpu_p0: cpu@10100 { 104 compatible = "apple,everest"; 105 device_type = "cpu"; 106 reg = <0x0 0x10100>; 107 enable-method = "spin-table"; 108 cpu-release-addr = <0 0>; /* To be filled by loader */ 109 next-level-cache = <&l2_cache_1>; 110 i-cache-size = <0x30000>; 111 d-cache-size = <0x20000>; 112 }; 113 114 cpu_p1: cpu@10101 { 115 compatible = "apple,everest"; 116 device_type = "cpu"; 117 reg = <0x0 0x10101>; 118 enable-method = "spin-table"; 119 cpu-release-addr = <0 0>; /* To be filled by loader */ 120 next-level-cache = <&l2_cache_1>; 121 i-cache-size = <0x30000>; 122 d-cache-size = <0x20000>; 123 }; 124 125 cpu_p2: cpu@10102 { 126 compatible = "apple,everest"; 127 device_type = "cpu"; 128 reg = <0x0 0x10102>; 129 enable-method = "spin-table"; 130 cpu-release-addr = <0 0>; /* To be filled by loader */ 131 next-level-cache = <&l2_cache_1>; 132 i-cache-size = <0x30000>; 133 d-cache-size = <0x20000>; 134 }; 135 136 cpu_p3: cpu@10103 { 137 compatible = "apple,everest"; 138 device_type = "cpu"; 139 reg = <0x0 0x10103>; 140 enable-method = "spin-table"; 141 cpu-release-addr = <0 0>; /* To be filled by loader */ 142 next-level-cache = <&l2_cache_1>; 143 i-cache-size = <0x30000>; 144 d-cache-size = <0x20000>; 145 }; 146 147 l2_cache_0: l2-cache-0 { 148 compatible = "cache"; 149 cache-level = <2>; 150 cache-unified; 151 cache-size = <0x400000>; 152 }; 153 154 l2_cache_1: l2-cache-1 { 155 compatible = "cache"; 156 cache-level = <2>; 157 cache-unified; 158 cache-size = <0x1000000>; 159 }; 160 }; 161 162 timer { 163 compatible = "arm,armv8-timer"; 164 interrupt-parent = <&aic>; 165 interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; 166 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 167 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>, 168 <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>, 169 <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>; 170 }; 171 172 clkref: clock-ref { 173 compatible = "fixed-clock"; 174 #clock-cells = <0>; 175 clock-frequency = <24000000>; 176 clock-output-names = "clkref"; 177 }; 178 179 soc { 180 compatible = "simple-bus"; 181 #address-cells = <2>; 182 #size-cells = <2>; 183 184 ranges; 185 nonposted-mmio; 186 /* Required to get >32-bit DMA via DARTs */ 187 dma-ranges = <0 0 0 0 0xffffffff 0xffffc000>; 188 189 i2c0: i2c@235010000 { 190 compatible = "apple,t8122-i2c", "apple,t8103-i2c"; 191 reg = <0x2 0x35010000 0x0 0x4000>; 192 clocks = <&clkref>; 193 interrupt-parent = <&aic>; 194 interrupts = <AIC_IRQ 761 IRQ_TYPE_LEVEL_HIGH>; 195 pinctrl-0 = <&i2c0_pins>; 196 pinctrl-names = "default"; 197 #address-cells = <0x1>; 198 #size-cells = <0x0>; 199 power-domains = <&ps_i2c0>; 200 status = "disabled"; 201 }; 202 203 i2c1: i2c@235014000 { 204 compatible = "apple,t8122-i2c", "apple,t8103-i2c"; 205 reg = <0x2 0x35014000 0x0 0x4000>; 206 clocks = <&clkref>; 207 interrupt-parent = <&aic>; 208 interrupts = <AIC_IRQ 762 IRQ_TYPE_LEVEL_HIGH>; 209 pinctrl-0 = <&i2c1_pins>; 210 pinctrl-names = "default"; 211 #address-cells = <0x1>; 212 #size-cells = <0x0>; 213 power-domains = <&ps_i2c1>; 214 status = "disabled"; 215 }; 216 217 i2c2: i2c@235018000 { 218 compatible = "apple,t8122-i2c", "apple,t8103-i2c"; 219 reg = <0x2 0x35018000 0x0 0x4000>; 220 clocks = <&clkref>; 221 interrupt-parent = <&aic>; 222 interrupts = <AIC_IRQ 763 IRQ_TYPE_LEVEL_HIGH>; 223 pinctrl-0 = <&i2c2_pins>; 224 pinctrl-names = "default"; 225 #address-cells = <0x1>; 226 #size-cells = <0x0>; 227 power-domains = <&ps_i2c2>; 228 status = "disabled"; 229 }; 230 231 i2c3: i2c@23501c000 { 232 compatible = "apple,t8122-i2c", "apple,t8103-i2c"; 233 reg = <0x2 0x3501c000 0x0 0x4000>; 234 clocks = <&clkref>; 235 interrupt-parent = <&aic>; 236 interrupts = <AIC_IRQ 764 IRQ_TYPE_LEVEL_HIGH>; 237 pinctrl-0 = <&i2c3_pins>; 238 pinctrl-names = "default"; 239 #address-cells = <0x1>; 240 #size-cells = <0x0>; 241 power-domains = <&ps_i2c3>; 242 status = "disabled"; 243 }; 244 245 i2c4: i2c@235020000 { 246 compatible = "apple,t8122-i2c", "apple,t8103-i2c"; 247 reg = <0x2 0x35020000 0x0 0x4000>; 248 clocks = <&clkref>; 249 interrupt-parent = <&aic>; 250 interrupts = <AIC_IRQ 765 IRQ_TYPE_LEVEL_HIGH>; 251 pinctrl-0 = <&i2c4_pins>; 252 pinctrl-names = "default"; 253 #address-cells = <0x1>; 254 #size-cells = <0x0>; 255 power-domains = <&ps_i2c4>; 256 status = "disabled"; 257 }; 258 259 fpwm1: pwm@2a1044000 { 260 compatible = "apple,t8122-fpwm", "apple,s5l-fpwm"; 261 reg = <0x2 0xa1044000 0x0 0x4000>; 262 power-domains = <&ps_fpwm1>; 263 clocks = <&clkref>; 264 #pwm-cells = <2>; 265 status = "disabled"; 266 }; 267 268 serial0: serial@2a1200000 { 269 compatible = "apple,s5l-uart"; 270 reg = <0x2 0xa1200000 0x0 0x1000>; 271 reg-io-width = <4>; 272 interrupt-parent = <&aic>; 273 interrupts = <AIC_IRQ 757 IRQ_TYPE_LEVEL_HIGH>; 274 /* 275 * TODO: figure out the clocking properly, there may 276 * be a third selectable clock. 277 */ 278 clocks = <&clkref>, <&clkref>; 279 clock-names = "uart", "clk_uart_baud0"; 280 power-domains = <&ps_uart0>; 281 status = "disabled"; 282 }; 283 284 aic: interrupt-controller@2d1000000 { 285 compatible = "apple,t8122-aic3"; 286 #interrupt-cells = <3>; 287 interrupt-controller; 288 reg = <0x2 0xd1000000 0x0 0x184000>, 289 <0x2 0xd1040000 0x0 0x4>; 290 reg-names = "core", "event"; 291 power-domains = <&ps_aic>; 292 293 affinities { 294 e-core-pmu-affinity { 295 apple,fiq-index = <AIC_CPU_PMU_E>; 296 cpus = <&cpu_e0 &cpu_e1 &cpu_e2 &cpu_e3>; 297 }; 298 299 p-core-pmu-affinity { 300 apple,fiq-index = <AIC_CPU_PMU_P>; 301 cpus = <&cpu_p0 &cpu_p1 &cpu_p2 &cpu_p3>; 302 }; 303 }; 304 }; 305 306 pmgr: power-management@2d0700000 { 307 compatible = "apple,t8122-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd"; 308 #address-cells = <1>; 309 #size-cells = <1>; 310 reg = <0x2 0xd0700000 0 0x14000>; 311 /* child nodes are added in t8122-pmgr.dtsi */ 312 }; 313 314 pinctrl_ap: pinctrl@2c7100000 { 315 compatible = "apple,t8122-pinctrl", "apple,t8103-pinctrl"; 316 reg = <0x2 0xc7100000 0x0 0x100000>; 317 power-domains = <&ps_gpio>; 318 319 gpio-controller; 320 #gpio-cells = <2>; 321 gpio-ranges = <&pinctrl_ap 0 0 224>; 322 apple,npins = <224>; 323 324 interrupt-controller; 325 #interrupt-cells = <2>; 326 interrupt-parent = <&aic>; 327 interrupts = <AIC_IRQ 241 IRQ_TYPE_LEVEL_HIGH>, 328 <AIC_IRQ 242 IRQ_TYPE_LEVEL_HIGH>, 329 <AIC_IRQ 243 IRQ_TYPE_LEVEL_HIGH>, 330 <AIC_IRQ 244 IRQ_TYPE_LEVEL_HIGH>, 331 <AIC_IRQ 245 IRQ_TYPE_LEVEL_HIGH>, 332 <AIC_IRQ 246 IRQ_TYPE_LEVEL_HIGH>, 333 <AIC_IRQ 247 IRQ_TYPE_LEVEL_HIGH>; 334 335 i2c0_pins: i2c0-pins { 336 pinmux = <APPLE_PINMUX(145, 1)>, 337 <APPLE_PINMUX(144, 1)>; 338 }; 339 340 i2c1_pins: i2c1-pins { 341 pinmux = <APPLE_PINMUX(147, 1)>, 342 <APPLE_PINMUX(146, 1)>; 343 }; 344 345 i2c2_pins: i2c2-pins { 346 pinmux = <APPLE_PINMUX(56, 1)>, 347 <APPLE_PINMUX(55, 1)>; 348 }; 349 350 i2c3_pins: i2c3-pins { 351 pinmux = <APPLE_PINMUX(54, 1)>, 352 <APPLE_PINMUX(53, 1)>; 353 }; 354 355 i2c4_pins: i2c4-pins { 356 pinmux = <APPLE_PINMUX(149, 1)>, 357 <APPLE_PINMUX(148, 1)>; 358 }; 359 360 }; 361 362 pinctrl_nub: pinctrl@2e41f0000 { 363 compatible = "apple,t8122-pinctrl", "apple,t8103-pinctrl"; 364 reg = <0x2 0xe41f0000 0x0 0x4000>; 365 power-domains = <&ps_nub_gpio>; 366 367 gpio-controller; 368 #gpio-cells = <2>; 369 gpio-ranges = <&pinctrl_nub 0 0 32>; 370 apple,npins = <32>; 371 372 interrupt-controller; 373 #interrupt-cells = <2>; 374 interrupt-parent = <&aic>; 375 interrupts = <AIC_IRQ 424 IRQ_TYPE_LEVEL_HIGH>, 376 <AIC_IRQ 425 IRQ_TYPE_LEVEL_HIGH>, 377 <AIC_IRQ 426 IRQ_TYPE_LEVEL_HIGH>, 378 <AIC_IRQ 427 IRQ_TYPE_LEVEL_HIGH>, 379 <AIC_IRQ 428 IRQ_TYPE_LEVEL_HIGH>, 380 <AIC_IRQ 429 IRQ_TYPE_LEVEL_HIGH>, 381 <AIC_IRQ 430 IRQ_TYPE_LEVEL_HIGH>; 382 }; 383 384 pmgr_mini: power-management@2e4280000 { 385 compatible = "apple,t8122-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd"; 386 #address-cells = <1>; 387 #size-cells = <1>; 388 reg = <0x2 0xe4280000 0 0x4000>; 389 /* child nodes are added in t8122-pmgr.dtsi */ 390 }; 391 392 wdt: watchdog@2e42b0000 { 393 compatible = "apple,t8122-wdt", "apple,t8103-wdt"; 394 reg = <0x2 0xe42b0000 0x0 0x4000>; 395 clocks = <&clkref>; 396 interrupt-parent = <&aic>; 397 interrupts = <AIC_IRQ 432 IRQ_TYPE_LEVEL_HIGH>; 398 }; 399 400 pinctrl_smc: pinctrl@2ec820000 { 401 compatible = "apple,t8122-pinctrl", "apple,t8103-pinctrl"; 402 reg = <0x2 0xec820000 0x0 0x4000>; 403 404 gpio-controller; 405 #gpio-cells = <2>; 406 gpio-ranges = <&pinctrl_smc 0 0 18>; 407 apple,npins = <18>; 408 409 interrupt-controller; 410 #interrupt-cells = <2>; 411 interrupt-parent = <&aic>; 412 interrupts = <AIC_IRQ 493 IRQ_TYPE_LEVEL_HIGH>, 413 <AIC_IRQ 494 IRQ_TYPE_LEVEL_HIGH>, 414 <AIC_IRQ 495 IRQ_TYPE_LEVEL_HIGH>, 415 <AIC_IRQ 496 IRQ_TYPE_LEVEL_HIGH>, 416 <AIC_IRQ 497 IRQ_TYPE_LEVEL_HIGH>, 417 <AIC_IRQ 498 IRQ_TYPE_LEVEL_HIGH>, 418 <AIC_IRQ 499 IRQ_TYPE_LEVEL_HIGH>; 419 }; 420 421 pinctrl_aop: pinctrl@2f4824000 { 422 compatible = "apple,t8122-pinctrl", "apple,t8103-pinctrl"; 423 reg = <0x2 0xf4824000 0x0 0x4000>; 424 425 gpio-controller; 426 #gpio-cells = <2>; 427 gpio-ranges = <&pinctrl_aop 0 0 54>; 428 apple,npins = <54>; 429 430 interrupt-controller; 431 #interrupt-cells = <2>; 432 interrupt-parent = <&aic>; 433 interrupts = <AIC_IRQ 346 IRQ_TYPE_LEVEL_HIGH>, 434 <AIC_IRQ 347 IRQ_TYPE_LEVEL_HIGH>, 435 <AIC_IRQ 348 IRQ_TYPE_LEVEL_HIGH>, 436 <AIC_IRQ 349 IRQ_TYPE_LEVEL_HIGH>, 437 <AIC_IRQ 350 IRQ_TYPE_LEVEL_HIGH>, 438 <AIC_IRQ 351 IRQ_TYPE_LEVEL_HIGH>, 439 <AIC_IRQ 352 IRQ_TYPE_LEVEL_HIGH>; 440 }; 441 }; 442}; 443 444#include "t8122-pmgr.dtsi" 445