1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T8112 "M2" SoC 4 * 5 * Other names: H14G 6 * 7 * Copyright The Asahi Linux Contributors 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14#include <dt-bindings/spmi/spmi.h> 15 16/ { 17 compatible = "apple,t8112", "apple,arm-platform"; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 gpu = &gpu; 24 }; 25 26 cpus { 27 #address-cells = <2>; 28 #size-cells = <0>; 29 30 cpu-map { 31 cluster0 { 32 core0 { 33 cpu = <&cpu_e0>; 34 }; 35 core1 { 36 cpu = <&cpu_e1>; 37 }; 38 core2 { 39 cpu = <&cpu_e2>; 40 }; 41 core3 { 42 cpu = <&cpu_e3>; 43 }; 44 }; 45 46 cluster1 { 47 core0 { 48 cpu = <&cpu_p0>; 49 }; 50 core1 { 51 cpu = <&cpu_p1>; 52 }; 53 core2 { 54 cpu = <&cpu_p2>; 55 }; 56 core3 { 57 cpu = <&cpu_p3>; 58 }; 59 }; 60 }; 61 62 cpu_e0: cpu@0 { 63 compatible = "apple,blizzard"; 64 device_type = "cpu"; 65 reg = <0x0 0x0>; 66 enable-method = "spin-table"; 67 cpu-release-addr = <0 0>; /* To be filled by loader */ 68 operating-points-v2 = <&ecluster_opp>; 69 capacity-dmips-mhz = <756>; 70 performance-domains = <&cpufreq_e>; 71 next-level-cache = <&l2_cache_0>; 72 i-cache-size = <0x20000>; 73 d-cache-size = <0x10000>; 74 }; 75 76 cpu_e1: cpu@1 { 77 compatible = "apple,blizzard"; 78 device_type = "cpu"; 79 reg = <0x0 0x1>; 80 enable-method = "spin-table"; 81 cpu-release-addr = <0 0>; /* To be filled by loader */ 82 operating-points-v2 = <&ecluster_opp>; 83 capacity-dmips-mhz = <756>; 84 performance-domains = <&cpufreq_e>; 85 next-level-cache = <&l2_cache_0>; 86 i-cache-size = <0x20000>; 87 d-cache-size = <0x10000>; 88 }; 89 90 cpu_e2: cpu@2 { 91 compatible = "apple,blizzard"; 92 device_type = "cpu"; 93 reg = <0x0 0x2>; 94 enable-method = "spin-table"; 95 cpu-release-addr = <0 0>; /* To be filled by loader */ 96 operating-points-v2 = <&ecluster_opp>; 97 capacity-dmips-mhz = <756>; 98 performance-domains = <&cpufreq_e>; 99 next-level-cache = <&l2_cache_0>; 100 i-cache-size = <0x20000>; 101 d-cache-size = <0x10000>; 102 }; 103 104 cpu_e3: cpu@3 { 105 compatible = "apple,blizzard"; 106 device_type = "cpu"; 107 reg = <0x0 0x3>; 108 enable-method = "spin-table"; 109 cpu-release-addr = <0 0>; /* To be filled by loader */ 110 operating-points-v2 = <&ecluster_opp>; 111 capacity-dmips-mhz = <756>; 112 performance-domains = <&cpufreq_e>; 113 next-level-cache = <&l2_cache_0>; 114 i-cache-size = <0x20000>; 115 d-cache-size = <0x10000>; 116 }; 117 118 cpu_p0: cpu@10100 { 119 compatible = "apple,avalanche"; 120 device_type = "cpu"; 121 reg = <0x0 0x10100>; 122 enable-method = "spin-table"; 123 cpu-release-addr = <0 0>; /* To be filled by loader */ 124 operating-points-v2 = <&pcluster_opp>; 125 capacity-dmips-mhz = <1024>; 126 performance-domains = <&cpufreq_p>; 127 next-level-cache = <&l2_cache_1>; 128 i-cache-size = <0x30000>; 129 d-cache-size = <0x20000>; 130 }; 131 132 cpu_p1: cpu@10101 { 133 compatible = "apple,avalanche"; 134 device_type = "cpu"; 135 reg = <0x0 0x10101>; 136 enable-method = "spin-table"; 137 cpu-release-addr = <0 0>; /* To be filled by loader */ 138 operating-points-v2 = <&pcluster_opp>; 139 capacity-dmips-mhz = <1024>; 140 performance-domains = <&cpufreq_p>; 141 next-level-cache = <&l2_cache_1>; 142 i-cache-size = <0x30000>; 143 d-cache-size = <0x20000>; 144 }; 145 146 cpu_p2: cpu@10102 { 147 compatible = "apple,avalanche"; 148 device_type = "cpu"; 149 reg = <0x0 0x10102>; 150 enable-method = "spin-table"; 151 cpu-release-addr = <0 0>; /* To be filled by loader */ 152 operating-points-v2 = <&pcluster_opp>; 153 capacity-dmips-mhz = <1024>; 154 performance-domains = <&cpufreq_p>; 155 next-level-cache = <&l2_cache_1>; 156 i-cache-size = <0x30000>; 157 d-cache-size = <0x20000>; 158 }; 159 160 cpu_p3: cpu@10103 { 161 compatible = "apple,avalanche"; 162 device_type = "cpu"; 163 reg = <0x0 0x10103>; 164 enable-method = "spin-table"; 165 cpu-release-addr = <0 0>; /* To be filled by loader */ 166 operating-points-v2 = <&pcluster_opp>; 167 capacity-dmips-mhz = <1024>; 168 performance-domains = <&cpufreq_p>; 169 next-level-cache = <&l2_cache_1>; 170 i-cache-size = <0x30000>; 171 d-cache-size = <0x20000>; 172 }; 173 174 l2_cache_0: l2-cache-0 { 175 compatible = "cache"; 176 cache-level = <2>; 177 cache-unified; 178 cache-size = <0x400000>; 179 }; 180 181 l2_cache_1: l2-cache-1 { 182 compatible = "cache"; 183 cache-level = <2>; 184 cache-unified; 185 cache-size = <0x1000000>; 186 }; 187 }; 188 189 ecluster_opp: opp-table-0 { 190 compatible = "operating-points-v2"; 191 opp-shared; 192 193 opp01 { 194 opp-hz = /bits/ 64 <600000000>; 195 opp-level = <1>; 196 clock-latency-ns = <7500>; 197 }; 198 opp02 { 199 opp-hz = /bits/ 64 <912000000>; 200 opp-level = <2>; 201 clock-latency-ns = <20000>; 202 }; 203 opp03 { 204 opp-hz = /bits/ 64 <1284000000>; 205 opp-level = <3>; 206 clock-latency-ns = <22000>; 207 }; 208 opp04 { 209 opp-hz = /bits/ 64 <1752000000>; 210 opp-level = <4>; 211 clock-latency-ns = <30000>; 212 }; 213 opp05 { 214 opp-hz = /bits/ 64 <2004000000>; 215 opp-level = <5>; 216 clock-latency-ns = <35000>; 217 }; 218 opp06 { 219 opp-hz = /bits/ 64 <2256000000>; 220 opp-level = <6>; 221 clock-latency-ns = <39000>; 222 }; 223 opp07 { 224 opp-hz = /bits/ 64 <2424000000>; 225 opp-level = <7>; 226 clock-latency-ns = <53000>; 227 }; 228 }; 229 230 pcluster_opp: opp-table-1 { 231 compatible = "operating-points-v2"; 232 opp-shared; 233 234 opp01 { 235 opp-hz = /bits/ 64 <660000000>; 236 opp-level = <1>; 237 clock-latency-ns = <9000>; 238 }; 239 opp02 { 240 opp-hz = /bits/ 64 <924000000>; 241 opp-level = <2>; 242 clock-latency-ns = <19000>; 243 }; 244 opp03 { 245 opp-hz = /bits/ 64 <1188000000>; 246 opp-level = <3>; 247 clock-latency-ns = <22000>; 248 }; 249 opp04 { 250 opp-hz = /bits/ 64 <1452000000>; 251 opp-level = <4>; 252 clock-latency-ns = <24000>; 253 }; 254 opp05 { 255 opp-hz = /bits/ 64 <1704000000>; 256 opp-level = <5>; 257 clock-latency-ns = <26000>; 258 }; 259 opp06 { 260 opp-hz = /bits/ 64 <1968000000>; 261 opp-level = <6>; 262 clock-latency-ns = <28000>; 263 }; 264 opp07 { 265 opp-hz = /bits/ 64 <2208000000>; 266 opp-level = <7>; 267 clock-latency-ns = <30000>; 268 }; 269 opp08 { 270 opp-hz = /bits/ 64 <2400000000>; 271 opp-level = <8>; 272 clock-latency-ns = <33000>; 273 }; 274 opp09 { 275 opp-hz = /bits/ 64 <2568000000>; 276 opp-level = <9>; 277 clock-latency-ns = <34000>; 278 }; 279 opp10 { 280 opp-hz = /bits/ 64 <2724000000>; 281 opp-level = <10>; 282 clock-latency-ns = <36000>; 283 }; 284 opp11 { 285 opp-hz = /bits/ 64 <2868000000>; 286 opp-level = <11>; 287 clock-latency-ns = <41000>; 288 }; 289 opp12 { 290 opp-hz = /bits/ 64 <2988000000>; 291 opp-level = <12>; 292 clock-latency-ns = <42000>; 293 }; 294 opp13 { 295 opp-hz = /bits/ 64 <3096000000>; 296 opp-level = <13>; 297 clock-latency-ns = <44000>; 298 }; 299 opp14 { 300 opp-hz = /bits/ 64 <3204000000>; 301 opp-level = <14>; 302 clock-latency-ns = <46000>; 303 }; 304 /* Not available until CPU deep sleep is implemented */ 305#if 0 306 opp15 { 307 opp-hz = /bits/ 64 <3324000000>; 308 opp-level = <15>; 309 clock-latency-ns = <62000>; 310 turbo-mode; 311 }; 312 opp16 { 313 opp-hz = /bits/ 64 <3408000000>; 314 opp-level = <16>; 315 clock-latency-ns = <62000>; 316 turbo-mode; 317 }; 318 opp17 { 319 opp-hz = /bits/ 64 <3504000000>; 320 opp-level = <17>; 321 clock-latency-ns = <62000>; 322 turbo-mode; 323 }; 324#endif 325 }; 326 327 timer { 328 compatible = "arm,armv8-timer"; 329 interrupt-parent = <&aic>; 330 interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; 331 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 332 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>, 333 <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>, 334 <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>; 335 }; 336 337 pmu-e { 338 compatible = "apple,blizzard-pmu"; 339 interrupt-parent = <&aic>; 340 interrupts = <AIC_FIQ AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>; 341 }; 342 343 pmu-p { 344 compatible = "apple,avalanche-pmu"; 345 interrupt-parent = <&aic>; 346 interrupts = <AIC_FIQ AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>; 347 }; 348 349 clkref: clock-ref { 350 compatible = "fixed-clock"; 351 #clock-cells = <0>; 352 clock-frequency = <24000000>; 353 clock-output-names = "clkref"; 354 }; 355 356 clk_200m: clock-200m { 357 compatible = "fixed-clock"; 358 #clock-cells = <0>; 359 clock-frequency = <200000000>; 360 clock-output-names = "clk_200m"; 361 }; 362 363 /* 364 * This is a fabulated representation of the input clock 365 * to NCO since we don't know the true clock tree. 366 */ 367 nco_clkref: clock-ref-nco { 368 compatible = "fixed-clock"; 369 #clock-cells = <0>; 370 clock-output-names = "nco_ref"; 371 }; 372 373 reserved-memory { 374 #address-cells = <2>; 375 #size-cells = <2>; 376 ranges; 377 378 gpu_globals: globals { 379 status = "disabled"; 380 }; 381 382 gpu_hw_cal_a: hw-cal-a { 383 status = "disabled"; 384 }; 385 386 gpu_hw_cal_b: hw-cal-b { 387 status = "disabled"; 388 }; 389 390 uat_handoff: uat-handoff { 391 status = "disabled"; 392 }; 393 394 uat_pagetables: uat-pagetables { 395 status = "disabled"; 396 }; 397 398 uat_ttbs: uat-ttbs { 399 status = "disabled"; 400 }; 401 }; 402 403 soc { 404 compatible = "simple-bus"; 405 #address-cells = <2>; 406 #size-cells = <2>; 407 408 ranges; 409 nonposted-mmio; 410 411 gpu: gpu@206400000 { 412 compatible = "apple,agx-g14g"; 413 reg = <0x2 0x6400000 0 0x40000>, 414 <0x2 0x4000000 0 0x1000000>; 415 reg-names = "asc", "sgx"; 416 mboxes = <&agx_mbox>; 417 power-domains = <&ps_gfx>; 418 memory-region = <&uat_ttbs>, <&uat_pagetables>, <&uat_handoff>, 419 <&gpu_hw_cal_a>, <&gpu_hw_cal_b>, <&gpu_globals>; 420 memory-region-names = "ttbs", "pagetables", "handoff", 421 "hw-cal-a", "hw-cal-b", "globals"; 422 423 apple,firmware-abi = <0 0 0>; 424 }; 425 426 agx_mbox: mbox@206408000 { 427 compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4"; 428 reg = <0x2 0x6408000 0x0 0x4000>; 429 interrupt-parent = <&aic>; 430 interrupts = <AIC_IRQ 709 IRQ_TYPE_LEVEL_HIGH>, 431 <AIC_IRQ 710 IRQ_TYPE_LEVEL_HIGH>, 432 <AIC_IRQ 711 IRQ_TYPE_LEVEL_HIGH>, 433 <AIC_IRQ 712 IRQ_TYPE_LEVEL_HIGH>; 434 interrupt-names = "send-empty", "send-not-empty", 435 "recv-empty", "recv-not-empty"; 436 #mbox-cells = <0>; 437 }; 438 439 cpufreq_e: cpufreq@210e20000 { 440 compatible = "apple,t8112-cluster-cpufreq", "apple,cluster-cpufreq"; 441 reg = <0x2 0x10e20000 0 0x1000>; 442 #performance-domain-cells = <0>; 443 }; 444 445 cpufreq_p: cpufreq@211e20000 { 446 compatible = "apple,t8112-cluster-cpufreq", "apple,cluster-cpufreq"; 447 reg = <0x2 0x11e20000 0 0x1000>; 448 #performance-domain-cells = <0>; 449 }; 450 451 display_dfr: display-pipe@228200000 { 452 compatible = "apple,t8112-display-pipe", "apple,h7-display-pipe"; 453 reg = <0x2 0x28200000 0x0 0xc000>, 454 <0x2 0x28400000 0x0 0x4000>; 455 reg-names = "be", "fe"; 456 power-domains = <&ps_dispdfr_fe>, <&ps_dispdfr_be>; 457 interrupt-parent = <&aic>; 458 interrupts = <AIC_IRQ 614 IRQ_TYPE_LEVEL_HIGH>, 459 <AIC_IRQ 618 IRQ_TYPE_LEVEL_HIGH>; 460 interrupt-names = "be", "fe"; 461 iommus = <&displaydfr_dart 0>; 462 status = "disabled"; 463 464 port { 465 dfr_adp_out_mipi: endpoint { 466 remote-endpoint = <&dfr_mipi_in_adp>; 467 }; 468 }; 469 }; 470 471 displaydfr_dart: iommu@228304000 { 472 compatible = "apple,t8110-dart"; 473 reg = <0x2 0x28304000 0x0 0x4000>; 474 interrupt-parent = <&aic>; 475 interrupts = <AIC_IRQ 616 IRQ_TYPE_LEVEL_HIGH>; 476 #iommu-cells = <1>; 477 power-domains = <&ps_dispdfr_fe>; 478 status = "disabled"; 479 }; 480 481 displaydfr_mipi: dsi@228600000 { 482 compatible = "apple,t8112-display-pipe-mipi", "apple,h7-display-pipe-mipi"; 483 reg = <0x2 0x28600000 0x0 0x100000>; 484 power-domains = <&ps_mipi_dsi>; 485 status = "disabled"; 486 487 ports { 488 #address-cells = <1>; 489 #size-cells = <0>; 490 491 dfr_mipi_in: port@0 { 492 reg = <0>; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 496 dfr_mipi_in_adp: endpoint@0 { 497 reg = <0>; 498 remote-endpoint = <&dfr_adp_out_mipi>; 499 }; 500 }; 501 502 dfr_mipi_out: port@1 { 503 reg = <1>; 504 #address-cells = <1>; 505 #size-cells = <0>; 506 }; 507 }; 508 }; 509 510 sio_dart: iommu@235004000 { 511 compatible = "apple,t8110-dart"; 512 reg = <0x2 0x35004000 0x0 0x4000>; 513 interrupt-parent = <&aic>; 514 interrupts = <AIC_IRQ 769 IRQ_TYPE_LEVEL_HIGH>; 515 #iommu-cells = <1>; 516 power-domains = <&ps_sio_cpu>; 517 }; 518 519 i2c0: i2c@235010000 { 520 compatible = "apple,t8112-i2c", "apple,i2c"; 521 reg = <0x2 0x35010000 0x0 0x4000>; 522 clocks = <&clkref>; 523 interrupt-parent = <&aic>; 524 interrupts = <AIC_IRQ 761 IRQ_TYPE_LEVEL_HIGH>; 525 pinctrl-0 = <&i2c0_pins>; 526 pinctrl-names = "default"; 527 #address-cells = <0x1>; 528 #size-cells = <0x0>; 529 power-domains = <&ps_i2c0>; 530 status = "disabled"; 531 }; 532 533 i2c1: i2c@235014000 { 534 compatible = "apple,t8112-i2c", "apple,i2c"; 535 reg = <0x2 0x35014000 0x0 0x4000>; 536 clocks = <&clkref>; 537 interrupt-parent = <&aic>; 538 interrupts = <AIC_IRQ 762 IRQ_TYPE_LEVEL_HIGH>; 539 pinctrl-0 = <&i2c1_pins>; 540 pinctrl-names = "default"; 541 #address-cells = <0x1>; 542 #size-cells = <0x0>; 543 power-domains = <&ps_i2c1>; 544 status = "disabled"; 545 }; 546 547 i2c2: i2c@235018000 { 548 compatible = "apple,t8112-i2c", "apple,i2c"; 549 reg = <0x2 0x35018000 0x0 0x4000>; 550 clocks = <&clkref>; 551 interrupt-parent = <&aic>; 552 interrupts = <AIC_IRQ 763 IRQ_TYPE_LEVEL_HIGH>; 553 pinctrl-0 = <&i2c2_pins>; 554 pinctrl-names = "default"; 555 #address-cells = <0x1>; 556 #size-cells = <0x0>; 557 power-domains = <&ps_i2c2>; 558 status = "disabled"; 559 }; 560 561 i2c3: i2c@23501c000 { 562 compatible = "apple,t8112-i2c", "apple,i2c"; 563 reg = <0x2 0x3501c000 0x0 0x4000>; 564 clocks = <&clkref>; 565 interrupt-parent = <&aic>; 566 interrupts = <AIC_IRQ 764 IRQ_TYPE_LEVEL_HIGH>; 567 pinctrl-0 = <&i2c3_pins>; 568 pinctrl-names = "default"; 569 #address-cells = <0x1>; 570 #size-cells = <0x0>; 571 power-domains = <&ps_i2c3>; 572 status = "disabled"; 573 }; 574 575 i2c4: i2c@235020000 { 576 compatible = "apple,t8112-i2c", "apple,i2c"; 577 reg = <0x2 0x35020000 0x0 0x4000>; 578 clocks = <&clkref>; 579 interrupt-parent = <&aic>; 580 interrupts = <AIC_IRQ 765 IRQ_TYPE_LEVEL_HIGH>; 581 pinctrl-0 = <&i2c4_pins>; 582 pinctrl-names = "default"; 583 #address-cells = <0x1>; 584 #size-cells = <0x0>; 585 power-domains = <&ps_i2c4>; 586 status = "disabled"; 587 }; 588 589 fpwm1: pwm@235044000 { 590 compatible = "apple,t8112-fpwm", "apple,s5l-fpwm"; 591 reg = <0x2 0x35044000 0x0 0x4000>; 592 power-domains = <&ps_fpwm1>; 593 clocks = <&clkref>; 594 #pwm-cells = <2>; 595 status = "disabled"; 596 }; 597 598 spi1: spi@235104000 { 599 compatible = "apple,t8112-spi", "apple,spi"; 600 reg = <0x2 0x35104000 0x0 0x4000>; 601 interrupt-parent = <&aic>; 602 interrupts = <AIC_IRQ 749 IRQ_TYPE_LEVEL_HIGH>; 603 clocks = <&clk_200m>; 604 pinctrl-0 = <&spi1_pins>; 605 pinctrl-names = "default"; 606 power-domains = <&ps_spi1>; 607 #address-cells = <1>; 608 #size-cells = <0>; 609 status = "disabled"; 610 }; 611 612 spi3: spi@23510c000 { 613 compatible = "apple,t8112-spi", "apple,spi"; 614 reg = <0x2 0x3510c000 0x0 0x4000>; 615 interrupt-parent = <&aic>; 616 interrupts = <AIC_IRQ 751 IRQ_TYPE_LEVEL_HIGH>; 617 clocks = <&clkref>; 618 pinctrl-0 = <&spi3_pins>; 619 pinctrl-names = "default"; 620 power-domains = <&ps_spi3>; 621 #address-cells = <1>; 622 #size-cells = <0>; 623 status = "disabled"; /* only used in J493 */ 624 }; 625 626 serial0: serial@235200000 { 627 compatible = "apple,s5l-uart"; 628 reg = <0x2 0x35200000 0x0 0x1000>; 629 reg-io-width = <4>; 630 interrupt-parent = <&aic>; 631 interrupts = <AIC_IRQ 739 IRQ_TYPE_LEVEL_HIGH>; 632 /* 633 * TODO: figure out the clocking properly, there may 634 * be a third selectable clock. 635 */ 636 clocks = <&clkref>, <&clkref>; 637 clock-names = "uart", "clk_uart_baud0"; 638 power-domains = <&ps_uart0>; 639 status = "disabled"; 640 }; 641 642 serial2: serial@235208000 { 643 compatible = "apple,s5l-uart"; 644 reg = <0x2 0x35208000 0x0 0x1000>; 645 reg-io-width = <4>; 646 interrupt-parent = <&aic>; 647 interrupts = <AIC_IRQ 741 IRQ_TYPE_LEVEL_HIGH>; 648 clocks = <&clkref>, <&clkref>; 649 clock-names = "uart", "clk_uart_baud0"; 650 power-domains = <&ps_uart2>; 651 status = "disabled"; 652 }; 653 654 admac: dma-controller@238200000 { 655 compatible = "apple,t8112-admac", "apple,admac"; 656 reg = <0x2 0x38200000 0x0 0x34000>; 657 dma-channels = <24>; 658 interrupts-extended = <0>, 659 <&aic AIC_IRQ 760 IRQ_TYPE_LEVEL_HIGH>, 660 <0>, 661 <0>; 662 #dma-cells = <1>; 663 iommus = <&sio_dart 2>; 664 power-domains = <&ps_sio_adma>; 665 resets = <&ps_audio_p>; 666 }; 667 668 mca: i2s@238400000 { 669 compatible = "apple,t8112-mca", "apple,mca"; 670 reg = <0x2 0x38400000 0x0 0x18000>, 671 <0x2 0x38300000 0x0 0x30000>; 672 673 interrupt-parent = <&aic>; 674 interrupts = <AIC_IRQ 753 IRQ_TYPE_LEVEL_HIGH>, 675 <AIC_IRQ 754 IRQ_TYPE_LEVEL_HIGH>, 676 <AIC_IRQ 755 IRQ_TYPE_LEVEL_HIGH>, 677 <AIC_IRQ 756 IRQ_TYPE_LEVEL_HIGH>, 678 <AIC_IRQ 757 IRQ_TYPE_LEVEL_HIGH>, 679 <AIC_IRQ 758 IRQ_TYPE_LEVEL_HIGH>; 680 681 resets = <&ps_audio_p>; 682 clocks = <&nco 0>, <&nco 1>, <&nco 2>, 683 <&nco 3>, <&nco 4>, <&nco 4>; 684 power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>, 685 <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>; 686 dmas = <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>, 687 <&admac 4>, <&admac 5>, <&admac 6>, <&admac 7>, 688 <&admac 8>, <&admac 9>, <&admac 10>, <&admac 11>, 689 <&admac 12>, <&admac 13>, <&admac 14>, <&admac 15>, 690 <&admac 16>, <&admac 17>, <&admac 18>, <&admac 19>, 691 <&admac 20>, <&admac 21>, <&admac 22>, <&admac 23>; 692 dma-names = "tx0a", "rx0a", "tx0b", "rx0b", 693 "tx1a", "rx1a", "tx1b", "rx1b", 694 "tx2a", "rx2a", "tx2b", "rx2b", 695 "tx3a", "rx3a", "tx3b", "rx3b", 696 "tx4a", "rx4a", "tx4b", "rx4b", 697 "tx5a", "rx5a", "tx5b", "rx5b"; 698 699 #sound-dai-cells = <1>; 700 }; 701 702 nco: clock-controller@23b044000 { 703 compatible = "apple,t8112-nco", "apple,nco"; 704 reg = <0x2 0x3b044000 0x0 0x14000>; 705 clocks = <&nco_clkref>; 706 #clock-cells = <1>; 707 }; 708 709 aic: interrupt-controller@23b0c0000 { 710 compatible = "apple,t8112-aic", "apple,aic2"; 711 #interrupt-cells = <3>; 712 interrupt-controller; 713 reg = <0x2 0x3b0c0000 0x0 0x8000>, 714 <0x2 0x3b0c8000 0x0 0x4>; 715 reg-names = "core", "event"; 716 power-domains = <&ps_aic>; 717 718 affinities { 719 e-core-pmu-affinity { 720 apple,fiq-index = <AIC_CPU_PMU_E>; 721 cpus = <&cpu_e0 &cpu_e1 &cpu_e2 &cpu_e3>; 722 }; 723 724 p-core-pmu-affinity { 725 apple,fiq-index = <AIC_CPU_PMU_P>; 726 cpus = <&cpu_p0 &cpu_p1 &cpu_p2 &cpu_p3>; 727 }; 728 }; 729 }; 730 731 pmgr: power-management@23b700000 { 732 compatible = "apple,t8112-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 733 #address-cells = <1>; 734 #size-cells = <1>; 735 reg = <0x2 0x3b700000 0 0x14000>; 736 /* child nodes are added in t8103-pmgr.dtsi */ 737 }; 738 739 pinctrl_ap: pinctrl@23c100000 { 740 compatible = "apple,t8112-pinctrl", "apple,pinctrl"; 741 reg = <0x2 0x3c100000 0x0 0x100000>; 742 power-domains = <&ps_gpio>; 743 744 gpio-controller; 745 #gpio-cells = <2>; 746 gpio-ranges = <&pinctrl_ap 0 0 213>; 747 apple,npins = <213>; 748 749 interrupt-controller; 750 #interrupt-cells = <2>; 751 interrupt-parent = <&aic>; 752 interrupts = <AIC_IRQ 199 IRQ_TYPE_LEVEL_HIGH>, 753 <AIC_IRQ 200 IRQ_TYPE_LEVEL_HIGH>, 754 <AIC_IRQ 201 IRQ_TYPE_LEVEL_HIGH>, 755 <AIC_IRQ 202 IRQ_TYPE_LEVEL_HIGH>, 756 <AIC_IRQ 203 IRQ_TYPE_LEVEL_HIGH>, 757 <AIC_IRQ 204 IRQ_TYPE_LEVEL_HIGH>, 758 <AIC_IRQ 205 IRQ_TYPE_LEVEL_HIGH>; 759 760 i2c0_pins: i2c0-pins { 761 pinmux = <APPLE_PINMUX(111, 1)>, 762 <APPLE_PINMUX(110, 1)>; 763 }; 764 765 i2c1_pins: i2c1-pins { 766 pinmux = <APPLE_PINMUX(113, 1)>, 767 <APPLE_PINMUX(112, 1)>; 768 }; 769 770 i2c2_pins: i2c2-pins { 771 pinmux = <APPLE_PINMUX(87, 1)>, 772 <APPLE_PINMUX(86, 1)>; 773 }; 774 775 i2c3_pins: i2c3-pins { 776 pinmux = <APPLE_PINMUX(54, 1)>, 777 <APPLE_PINMUX(53, 1)>; 778 }; 779 780 i2c4_pins: i2c4-pins { 781 pinmux = <APPLE_PINMUX(131, 1)>, 782 <APPLE_PINMUX(130, 1)>; 783 }; 784 785 spi1_pins: spi1-pins { 786 pinmux = <APPLE_PINMUX(46, 1)>, 787 <APPLE_PINMUX(47, 1)>, 788 <APPLE_PINMUX(48, 1)>, 789 <APPLE_PINMUX(49, 1)>; 790 }; 791 792 spi3_pins: spi3-pins { 793 pinmux = <APPLE_PINMUX(93, 1)>, 794 <APPLE_PINMUX(94, 1)>, 795 <APPLE_PINMUX(95, 1)>, 796 <APPLE_PINMUX(96, 1)>; 797 }; 798 799 pcie_pins: pcie-pins { 800 pinmux = <APPLE_PINMUX(162, 1)>, 801 <APPLE_PINMUX(163, 1)>, 802 <APPLE_PINMUX(164, 1)>; 803 // TODO: 1 more CLKREQs 804 }; 805 }; 806 807 pinctrl_nub: pinctrl@23d1f0000 { 808 compatible = "apple,t8112-pinctrl", "apple,pinctrl"; 809 reg = <0x2 0x3d1f0000 0x0 0x4000>; 810 power-domains = <&ps_nub_gpio>; 811 812 gpio-controller; 813 #gpio-cells = <2>; 814 gpio-ranges = <&pinctrl_nub 0 0 24>; 815 apple,npins = <24>; 816 817 interrupt-controller; 818 #interrupt-cells = <2>; 819 interrupt-parent = <&aic>; 820 interrupts = <AIC_IRQ 371 IRQ_TYPE_LEVEL_HIGH>, 821 <AIC_IRQ 372 IRQ_TYPE_LEVEL_HIGH>, 822 <AIC_IRQ 373 IRQ_TYPE_LEVEL_HIGH>, 823 <AIC_IRQ 374 IRQ_TYPE_LEVEL_HIGH>, 824 <AIC_IRQ 375 IRQ_TYPE_LEVEL_HIGH>, 825 <AIC_IRQ 376 IRQ_TYPE_LEVEL_HIGH>, 826 <AIC_IRQ 377 IRQ_TYPE_LEVEL_HIGH>; 827 }; 828 829 pmgr_mini: power-management@23d280000 { 830 compatible = "apple,t8112-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 831 #address-cells = <1>; 832 #size-cells = <1>; 833 reg = <0x2 0x3d280000 0 0x4000>; 834 /* child nodes are added in t8103-pmgr.dtsi */ 835 }; 836 837 wdt: watchdog@23d2b0000 { 838 compatible = "apple,t8112-wdt", "apple,wdt"; 839 reg = <0x2 0x3d2b0000 0x0 0x4000>; 840 clocks = <&clkref>; 841 interrupt-parent = <&aic>; 842 interrupts = <AIC_IRQ 379 IRQ_TYPE_LEVEL_HIGH>; 843 }; 844 845 nub_spmi: spmi@23d714000 { 846 compatible = "apple,t8112-spmi", "apple,spmi"; 847 reg = <0x2 0x3d714000 0x0 0x100>; 848 #address-cells = <2>; 849 #size-cells = <0>; 850 851 pmic1: pmic@e { 852 compatible = "apple,stowe-pmic", "apple,spmi-nvmem"; 853 reg = <0xe SPMI_USID>; 854 855 nvmem-layout { 856 compatible = "fixed-layout"; 857 #address-cells = <1>; 858 #size-cells = <1>; 859 860 fault_shadow: fault-shadow@867b { 861 reg = <0x867b 0x10>; 862 }; 863 864 socd: socd@8b00 { 865 reg = <0x8b00 0x400>; 866 }; 867 868 boot_stage: boot-stage@f701 { 869 reg = <0xf701 0x1>; 870 }; 871 872 boot_error_count: boot-error-count@f702,0 { 873 reg = <0xf702 0x1>; 874 bits = <0 4>; 875 }; 876 877 panic_count: panic-count@f702,4 { 878 reg = <0xf702 0x1>; 879 bits = <4 4>; 880 }; 881 882 boot_error_stage: boot-error-stage@f703 { 883 reg = <0xf703 0x1>; 884 }; 885 886 shutdown_flag: shutdown-flag@f70f,3 { 887 reg = <0xf70f 0x1>; 888 bits = <3 1>; 889 }; 890 891 pm_setting: pm-setting@f801 { 892 reg = <0xf801 0x1>; 893 }; 894 895 rtc_offset: rtc-offset@f900 { 896 reg = <0xf900 0x6>; 897 }; 898 }; 899 }; 900 }; 901 902 pinctrl_smc: pinctrl@23e820000 { 903 compatible = "apple,t8112-pinctrl", "apple,pinctrl"; 904 reg = <0x2 0x3e820000 0x0 0x4000>; 905 906 gpio-controller; 907 #gpio-cells = <2>; 908 gpio-ranges = <&pinctrl_smc 0 0 18>; 909 apple,npins = <18>; 910 911 interrupt-controller; 912 #interrupt-cells = <2>; 913 interrupt-parent = <&aic>; 914 interrupts = <AIC_IRQ 490 IRQ_TYPE_LEVEL_HIGH>, 915 <AIC_IRQ 491 IRQ_TYPE_LEVEL_HIGH>, 916 <AIC_IRQ 492 IRQ_TYPE_LEVEL_HIGH>, 917 <AIC_IRQ 493 IRQ_TYPE_LEVEL_HIGH>, 918 <AIC_IRQ 494 IRQ_TYPE_LEVEL_HIGH>, 919 <AIC_IRQ 495 IRQ_TYPE_LEVEL_HIGH>, 920 <AIC_IRQ 496 IRQ_TYPE_LEVEL_HIGH>; 921 }; 922 923 pinctrl_aop: pinctrl@24a820000 { 924 compatible = "apple,t8112-pinctrl", "apple,pinctrl"; 925 reg = <0x2 0x4a820000 0x0 0x4000>; 926 927 gpio-controller; 928 #gpio-cells = <2>; 929 gpio-ranges = <&pinctrl_aop 0 0 54>; 930 apple,npins = <54>; 931 932 interrupt-controller; 933 #interrupt-cells = <2>; 934 interrupt-parent = <&aic>; 935 interrupts = <AIC_IRQ 301 IRQ_TYPE_LEVEL_HIGH>, 936 <AIC_IRQ 302 IRQ_TYPE_LEVEL_HIGH>, 937 <AIC_IRQ 303 IRQ_TYPE_LEVEL_HIGH>, 938 <AIC_IRQ 304 IRQ_TYPE_LEVEL_HIGH>, 939 <AIC_IRQ 305 IRQ_TYPE_LEVEL_HIGH>, 940 <AIC_IRQ 306 IRQ_TYPE_LEVEL_HIGH>, 941 <AIC_IRQ 307 IRQ_TYPE_LEVEL_HIGH>; 942 }; 943 944 ans_mbox: mbox@277408000 { 945 compatible = "apple,t8112-asc-mailbox", "apple,asc-mailbox-v4"; 946 reg = <0x2 0x77408000 0x0 0x4000>; 947 interrupt-parent = <&aic>; 948 interrupts = <AIC_IRQ 717 IRQ_TYPE_LEVEL_HIGH>, 949 <AIC_IRQ 718 IRQ_TYPE_LEVEL_HIGH>, 950 <AIC_IRQ 719 IRQ_TYPE_LEVEL_HIGH>, 951 <AIC_IRQ 720 IRQ_TYPE_LEVEL_HIGH>; 952 interrupt-names = "send-empty", "send-not-empty", 953 "recv-empty", "recv-not-empty"; 954 #mbox-cells = <0>; 955 power-domains = <&ps_ans>; 956 }; 957 958 sart: sart@27bc50000 { 959 compatible = "apple,t8112-sart", "apple,t6000-sart"; 960 reg = <0x2 0x7bc50000 0x0 0x10000>; 961 power-domains = <&ps_ans>; 962 }; 963 964 nvme@27bcc0000 { 965 compatible = "apple,t8112-nvme-ans2", "apple,nvme-ans2"; 966 reg = <0x2 0x7bcc0000 0x0 0x40000>, 967 <0x2 0x77400000 0x0 0x4000>; 968 reg-names = "nvme", "ans"; 969 interrupt-parent = <&aic>; 970 interrupts = <AIC_IRQ 724 IRQ_TYPE_LEVEL_HIGH>; 971 mboxes = <&ans_mbox>; 972 apple,sart = <&sart>; 973 power-domains = <&ps_ans>, <&ps_apcie_st>; 974 power-domain-names = "ans", "apcie0"; 975 resets = <&ps_ans>; 976 }; 977 978 pcie0_dart: iommu@681008000 { 979 compatible = "apple,t8110-dart"; 980 reg = <0x6 0x81008000 0x0 0x4000>; 981 #iommu-cells = <1>; 982 interrupt-parent = <&aic>; 983 interrupts = <AIC_IRQ 782 IRQ_TYPE_LEVEL_HIGH>; 984 power-domains = <&ps_apcie_gp>; 985 }; 986 987 pcie1_dart: iommu@682008000 { 988 compatible = "apple,t8110-dart"; 989 reg = <0x6 0x82008000 0x0 0x4000>; 990 #iommu-cells = <1>; 991 interrupt-parent = <&aic>; 992 interrupts = <AIC_IRQ 785 IRQ_TYPE_LEVEL_HIGH>; 993 power-domains = <&ps_apcie_gp>; 994 status = "disabled"; 995 }; 996 997 pcie2_dart: iommu@683008000 { 998 compatible = "apple,t8110-dart"; 999 reg = <0x6 0x83008000 0x0 0x4000>; 1000 #iommu-cells = <1>; 1001 interrupt-parent = <&aic>; 1002 interrupts = <AIC_IRQ 788 IRQ_TYPE_LEVEL_HIGH>; 1003 power-domains = <&ps_apcie_gp>; 1004 status = "disabled"; 1005 }; 1006 1007 pcie3_dart: iommu@684008000 { 1008 compatible = "apple,t8110-dart"; 1009 reg = <0x6 0x84008000 0x0 0x4000>; 1010 #iommu-cells = <1>; 1011 interrupt-parent = <&aic>; 1012 interrupts = <AIC_IRQ 791 IRQ_TYPE_LEVEL_HIGH>; 1013 power-domains = <&ps_apcie_gp>; 1014 status = "disabled"; 1015 }; 1016 1017 pcie0: pcie@690000000 { 1018 compatible = "apple,t8112-pcie", "apple,pcie"; 1019 device_type = "pci"; 1020 1021 reg = <0x6 0x90000000 0x0 0x1000000>, 1022 <0x6 0x80000000 0x0 0x100000>, 1023 <0x6 0x81000000 0x0 0x4000>, 1024 <0x6 0x82000000 0x0 0x4000>, 1025 <0x6 0x83000000 0x0 0x4000>, 1026 <0x6 0x84000000 0x0 0x4000>; 1027 reg-names = "config", "rc", "port0", "port1", "port2", "port3"; 1028 1029 interrupt-parent = <&aic>; 1030 interrupts = <AIC_IRQ 781 IRQ_TYPE_LEVEL_HIGH>, 1031 <AIC_IRQ 784 IRQ_TYPE_LEVEL_HIGH>, 1032 <AIC_IRQ 787 IRQ_TYPE_LEVEL_HIGH>, 1033 <AIC_IRQ 790 IRQ_TYPE_LEVEL_HIGH>; 1034 1035 msi-controller; 1036 msi-parent = <&pcie0>; 1037 msi-ranges = <&aic AIC_IRQ 793 IRQ_TYPE_EDGE_RISING 32>; 1038 1039 iommu-map = <0x100 &pcie0_dart 0 1>, 1040 <0x200 &pcie1_dart 1 1>, 1041 <0x300 &pcie2_dart 2 1>, 1042 <0x400 &pcie3_dart 3 1>; 1043 iommu-map-mask = <0xff00>; 1044 1045 bus-range = <0 4>; 1046 #address-cells = <3>; 1047 #size-cells = <2>; 1048 ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, 1049 <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; 1050 1051 power-domains = <&ps_apcie_gp>; 1052 pinctrl-0 = <&pcie_pins>; 1053 pinctrl-names = "default"; 1054 1055 port00: pci@0,0 { 1056 device_type = "pci"; 1057 reg = <0x0 0x0 0x0 0x0 0x0>; 1058 reset-gpios = <&pinctrl_ap 166 GPIO_ACTIVE_LOW>; 1059 1060 #address-cells = <3>; 1061 #size-cells = <2>; 1062 ranges; 1063 1064 interrupt-controller; 1065 #interrupt-cells = <1>; 1066 1067 interrupt-map-mask = <0 0 0 7>; 1068 interrupt-map = <0 0 0 1 &port00 0 0 0 0>, 1069 <0 0 0 2 &port00 0 0 0 1>, 1070 <0 0 0 3 &port00 0 0 0 2>, 1071 <0 0 0 4 &port00 0 0 0 3>; 1072 }; 1073 1074 port01: pci@1,0 { 1075 device_type = "pci"; 1076 reg = <0x800 0x0 0x0 0x0 0x0>; 1077 reset-gpios = <&pinctrl_ap 167 GPIO_ACTIVE_LOW>; 1078 1079 #address-cells = <3>; 1080 #size-cells = <2>; 1081 ranges; 1082 1083 interrupt-controller; 1084 #interrupt-cells = <1>; 1085 1086 interrupt-map-mask = <0 0 0 7>; 1087 interrupt-map = <0 0 0 1 &port01 0 0 0 0>, 1088 <0 0 0 2 &port01 0 0 0 1>, 1089 <0 0 0 3 &port01 0 0 0 2>, 1090 <0 0 0 4 &port01 0 0 0 3>; 1091 1092 status = "disabled"; 1093 }; 1094 1095 port02: pci@2,0 { 1096 device_type = "pci"; 1097 reg = <0x1000 0x0 0x0 0x0 0x0>; 1098 reset-gpios = <&pinctrl_ap 168 GPIO_ACTIVE_LOW>; 1099 1100 #address-cells = <3>; 1101 #size-cells = <2>; 1102 ranges; 1103 1104 interrupt-controller; 1105 #interrupt-cells = <1>; 1106 1107 interrupt-map-mask = <0 0 0 7>; 1108 interrupt-map = <0 0 0 1 &port02 0 0 0 0>, 1109 <0 0 0 2 &port02 0 0 0 1>, 1110 <0 0 0 3 &port02 0 0 0 2>, 1111 <0 0 0 4 &port02 0 0 0 3>; 1112 1113 status = "disabled"; 1114 }; 1115 1116 /* TODO: GPIO unknown */ 1117 port03: pci@3,0 { 1118 device_type = "pci"; 1119 reg = <0x1800 0x0 0x0 0x0 0x0>; 1120 //reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>; 1121 1122 #address-cells = <3>; 1123 #size-cells = <2>; 1124 ranges; 1125 1126 interrupt-controller; 1127 #interrupt-cells = <1>; 1128 1129 interrupt-map-mask = <0 0 0 7>; 1130 interrupt-map = <0 0 0 1 &port03 0 0 0 0>, 1131 <0 0 0 2 &port03 0 0 0 1>, 1132 <0 0 0 3 &port03 0 0 0 2>, 1133 <0 0 0 4 &port03 0 0 0 3>; 1134 1135 status = "disabled"; 1136 }; 1137 }; 1138 }; 1139}; 1140 1141#include "t8112-pmgr.dtsi" 1142