1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T8012 "T2" SoC 4 * 5 * Other names: H9M, "Gibraltar" 6 * 7 * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14 15/ { 16 interrupt-parent = <&aic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 clkref: clock-ref { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <24000000>; 24 clock-output-names = "clkref"; 25 }; 26 27 cpus { 28 #address-cells = <2>; 29 #size-cells = <0>; 30 31 cpu0: cpu@10000 { 32 compatible = "apple,hurricane-zephyr"; 33 reg = <0x0 0x10000>; 34 cpu-release-addr = <0 0>; /* To be filled by loader */ 35 operating-points-v2 = <&fusion_opp>; 36 performance-domains = <&cpufreq>; 37 enable-method = "spin-table"; 38 device_type = "cpu"; 39 next-level-cache = <&l2_cache>; 40 i-cache-size = <0x10000>; /* P-core */ 41 d-cache-size = <0x10000>; /* P-core */ 42 }; 43 44 cpu1: cpu@10001 { 45 compatible = "apple,hurricane-zephyr"; 46 reg = <0x0 0x10001>; 47 cpu-release-addr = <0 0>; /* To be filled by loader */ 48 operating-points-v2 = <&fusion_opp>; 49 performance-domains = <&cpufreq>; 50 enable-method = "spin-table"; 51 device_type = "cpu"; 52 next-level-cache = <&l2_cache>; 53 i-cache-size = <0x10000>; /* P-core */ 54 d-cache-size = <0x10000>; /* P-core */ 55 }; 56 57 l2_cache: l2-cache { 58 compatible = "cache"; 59 cache-level = <2>; 60 cache-unified; 61 cache-size = <0x300000>; /* P-cluster */ 62 }; 63 }; 64 65 fusion_opp: opp-table { 66 compatible = "operating-points-v2"; 67 68 /* 69 * Apple Fusion Architecture: Hardware big.LITTLE switcher 70 * that use p-state transitions to switch between cores. 71 * Only one type of core can be active at a given time. 72 * 73 * The E-core frequencies are adjusted so performance scales 74 * linearly with reported clock speed. 75 */ 76 77 opp01 { 78 opp-hz = /bits/ 64 <172000000>; /* 300 MHz, E-core */ 79 opp-level = <1>; 80 clock-latency-ns = <11000>; 81 }; 82 opp02 { 83 opp-hz = /bits/ 64 <230000000>; /* 396 MHz, E-core */ 84 opp-level = <2>; 85 clock-latency-ns = <140000>; 86 }; 87 opp03 { 88 opp-hz = /bits/ 64 <425000000>; /* 732 MHz, E-core */ 89 opp-level = <3>; 90 clock-latency-ns = <110000>; 91 }; 92 opp04 { 93 opp-hz = /bits/ 64 <637000000>; /* 1092 MHz, E-core */ 94 opp-level = <4>; 95 clock-latency-ns = <130000>; 96 }; 97 opp05 { 98 opp-hz = /bits/ 64 <756000000>; 99 opp-level = <5>; 100 clock-latency-ns = <130000>; 101 }; 102 opp06 { 103 opp-hz = /bits/ 64 <1056000000>; 104 opp-level = <6>; 105 clock-latency-ns = <130000>; 106 }; 107 opp07 { 108 opp-hz = /bits/ 64 <1356000000>; 109 opp-level = <7>; 110 clock-latency-ns = <130000>; 111 }; 112 opp08 { 113 opp-hz = /bits/ 64 <1644000000>; 114 opp-level = <8>; 115 clock-latency-ns = <135000>; 116 }; 117 opp09 { 118 opp-hz = /bits/ 64 <1944000000>; 119 opp-level = <9>; 120 clock-latency-ns = <140000>; 121 }; 122 opp10 { 123 opp-hz = /bits/ 64 <2244000000>; 124 opp-level = <10>; 125 clock-latency-ns = <150000>; 126 }; 127#if 0 128 /* Not available until CPU deep sleep is implemented */ 129 opp11 { 130 opp-hz = /bits/ 64 <2340000000>; 131 opp-level = <11>; 132 clock-latency-ns = <150000>; 133 turbo-mode; 134 }; 135#endif 136 }; 137 138 soc { 139 compatible = "simple-bus"; 140 #address-cells = <2>; 141 #size-cells = <2>; 142 nonposted-mmio; 143 ranges; 144 145 cpufreq: performance-controller@202f20000 { 146 compatible = "apple,t8010-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; 147 reg = <0x2 0x02f20000 0 0x1000>; 148 #performance-domain-cells = <0>; 149 }; 150 151 serial0: serial@20a600000 { 152 compatible = "apple,s5l-uart"; 153 reg = <0x2 0x0a600000 0x0 0x4000>; 154 reg-io-width = <4>; 155 interrupt-parent = <&aic>; 156 interrupts = <AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>; 157 /* Use the bootloader-enabled clocks for now. */ 158 clocks = <&clkref>, <&clkref>; 159 clock-names = "uart", "clk_uart_baud0"; 160 power-domains = <&ps_uart0>; 161 status = "disabled"; 162 }; 163 164 pmgr: power-management@20e000000 { 165 compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 166 #address-cells = <1>; 167 #size-cells = <1>; 168 169 reg = <0x2 0xe000000 0 0x8c000>; 170 }; 171 172 aic: interrupt-controller@20e100000 { 173 compatible = "apple,t8010-aic", "apple,aic"; 174 reg = <0x2 0x0e100000 0x0 0x100000>; 175 #interrupt-cells = <3>; 176 interrupt-controller; 177 power-domains = <&ps_aic>; 178 }; 179 180 pinctrl_ap: pinctrl@20f100000 { 181 compatible = "apple,t8010-pinctrl", "apple,pinctrl"; 182 reg = <0x2 0x0f100000 0x0 0x100000>; 183 power-domains = <&ps_gpio>; 184 185 gpio-controller; 186 #gpio-cells = <2>; 187 gpio-ranges = <&pinctrl_ap 0 0 221>; 188 apple,npins = <221>; 189 190 interrupt-controller; 191 #interrupt-cells = <2>; 192 interrupt-parent = <&aic>; 193 interrupts = <AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH>, 194 <AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>, 195 <AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>, 196 <AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>, 197 <AIC_IRQ 49 IRQ_TYPE_LEVEL_HIGH>, 198 <AIC_IRQ 50 IRQ_TYPE_LEVEL_HIGH>, 199 <AIC_IRQ 51 IRQ_TYPE_LEVEL_HIGH>; 200 }; 201 202 pinctrl_aop: pinctrl@2100f0000 { 203 compatible = "apple,t8010-pinctrl", "apple,pinctrl"; 204 reg = <0x2 0x0100f0000 0x0 0x10000>; 205 206 gpio-controller; 207 #gpio-cells = <2>; 208 gpio-ranges = <&pinctrl_aop 0 0 41>; 209 apple,npins = <41>; 210 211 interrupt-controller; 212 #interrupt-cells = <2>; 213 interrupt-parent = <&aic>; 214 interrupts = <AIC_IRQ 131 IRQ_TYPE_LEVEL_HIGH>, 215 <AIC_IRQ 132 IRQ_TYPE_LEVEL_HIGH>, 216 <AIC_IRQ 133 IRQ_TYPE_LEVEL_HIGH>, 217 <AIC_IRQ 134 IRQ_TYPE_LEVEL_HIGH>, 218 <AIC_IRQ 135 IRQ_TYPE_LEVEL_HIGH>, 219 <AIC_IRQ 136 IRQ_TYPE_LEVEL_HIGH>, 220 <AIC_IRQ 137 IRQ_TYPE_LEVEL_HIGH>; 221 }; 222 223 pinctrl_nub: pinctrl@2111f0000 { 224 compatible = "apple,t8010-pinctrl", "apple,pinctrl"; 225 reg = <0x2 0x111f0000 0x0 0x1000>; 226 227 gpio-controller; 228 #gpio-cells = <2>; 229 gpio-ranges = <&pinctrl_nub 0 0 19>; 230 apple,npins = <19>; 231 232 interrupt-controller; 233 #interrupt-cells = <2>; 234 interrupt-parent = <&aic>; 235 interrupts = <AIC_IRQ 164 IRQ_TYPE_LEVEL_HIGH>, 236 <AIC_IRQ 165 IRQ_TYPE_LEVEL_HIGH>, 237 <AIC_IRQ 166 IRQ_TYPE_LEVEL_HIGH>; 238 }; 239 240 pmgr_mini: power-management@211200000 { 241 compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 242 #address-cells = <1>; 243 #size-cells = <1>; 244 245 reg = <0x2 0x11200000 0 0x84000>; 246 }; 247 248 wdt: watchdog@2112b0000 { 249 compatible = "apple,t8010-wdt", "apple,wdt"; 250 reg = <0x2 0x112b0000 0x0 0x4000>; 251 clocks = <&clkref>; 252 interrupt-parent = <&aic>; 253 interrupts = <AIC_IRQ 168 IRQ_TYPE_LEVEL_HIGH>; 254 }; 255 256 pinctrl_smc: pinctrl@212024000 { 257 compatible = "apple,t8010-pinctrl", "apple,pinctrl"; 258 reg = <0x2 0x12024000 0x0 0x1000>; 259 power-domains = <&ps_smc_cpu>; 260 261 gpio-controller; 262 #gpio-cells = <2>; 263 gpio-ranges = <&pinctrl_smc 0 0 81>; 264 apple,npins = <81>; 265 266 interrupt-controller; 267 #interrupt-cells = <2>; 268 interrupt-parent = <&aic>; 269 interrupts = <AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>, 270 <AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>, 271 <AIC_IRQ 197 IRQ_TYPE_LEVEL_HIGH>, 272 <AIC_IRQ 198 IRQ_TYPE_LEVEL_HIGH>, 273 <AIC_IRQ 199 IRQ_TYPE_LEVEL_HIGH>, 274 <AIC_IRQ 200 IRQ_TYPE_LEVEL_HIGH>, 275 <AIC_IRQ 201 IRQ_TYPE_LEVEL_HIGH>; 276 /* 277 * SMC is not yet supported and accessing this pinctrl while SMC is 278 * suspended results in a hang. 279 */ 280 status = "disabled"; 281 }; 282 }; 283 284 timer { 285 compatible = "arm,armv8-timer"; 286 interrupt-parent = <&aic>; 287 interrupt-names = "phys", "virt"; 288 /* Note that T2 doesn't actually have a hypervisor (EL2 is not implemented). */ 289 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 290 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; 291 }; 292}; 293 294#include "t8012-pmgr.dtsi" 295