1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T7000 "A8" SoC 4 * 5 * Other names: H7P, "Fiji" 6 * 7 * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> 8 * Based on Asahi Linux's M1 (t8103.dtsi) and Corellium's A10 efforts. 9 */ 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/apple-aic.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/pinctrl/apple.h> 15 16/ { 17 interrupt-parent = <&aic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 clkref: clock-ref { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 clock-frequency = <24000000>; 25 clock-output-names = "clkref"; 26 }; 27 28 cpus { 29 #address-cells = <2>; 30 #size-cells = <0>; 31 32 cpu0: cpu@0 { 33 compatible = "apple,typhoon"; 34 reg = <0x0 0x0>; 35 cpu-release-addr = <0 0>; /* To be filled in by loader */ 36 performance-domains = <&cpufreq>; 37 operating-points-v2 = <&typhoon_opp>; 38 enable-method = "spin-table"; 39 device_type = "cpu"; 40 next-level-cache = <&l2_cache>; 41 i-cache-size = <0x10000>; 42 d-cache-size = <0x10000>; 43 }; 44 45 cpu1: cpu@1 { 46 compatible = "apple,typhoon"; 47 reg = <0x0 0x1>; 48 cpu-release-addr = <0 0>; /* To be filled in by loader */ 49 performance-domains = <&cpufreq>; 50 operating-points-v2 = <&typhoon_opp>; 51 enable-method = "spin-table"; 52 device_type = "cpu"; 53 next-level-cache = <&l2_cache>; 54 i-cache-size = <0x10000>; 55 d-cache-size = <0x10000>; 56 }; 57 58 l2_cache: l2-cache { 59 compatible = "cache"; 60 cache-level = <2>; 61 cache-unified; 62 cache-size = <0x100000>; 63 }; 64 }; 65 66 typhoon_opp: opp-table { 67 compatible = "operating-points-v2"; 68 69 opp01 { 70 opp-hz = /bits/ 64 <300000000>; 71 opp-level = <1>; 72 clock-latency-ns = <300>; 73 }; 74 opp02 { 75 opp-hz = /bits/ 64 <396000000>; 76 opp-level = <2>; 77 clock-latency-ns = <50000>; 78 }; 79 opp03 { 80 opp-hz = /bits/ 64 <600000000>; 81 opp-level = <3>; 82 clock-latency-ns = <29000>; 83 }; 84 opp04 { 85 opp-hz = /bits/ 64 <840000000>; 86 opp-level = <4>; 87 clock-latency-ns = <29000>; 88 }; 89 opp05 { 90 opp-hz = /bits/ 64 <1128000000>; 91 opp-level = <5>; 92 clock-latency-ns = <36000>; 93 }; 94 typhoon_opp06: opp06 { 95 opp-hz = /bits/ 64 <1392000000>; 96 opp-level = <6>; 97 clock-latency-ns = <42000>; 98 status = "disabled"; /* Not available on N102 */ 99 }; 100 typhoon_opp07: opp07 { 101 opp-hz = /bits/ 64 <1512000000>; 102 opp-level = <7>; 103 clock-latency-ns = <49000>; 104 status = "disabled"; /* J96 and J97 only */ 105 }; 106 }; 107 108 soc { 109 compatible = "simple-bus"; 110 #address-cells = <2>; 111 #size-cells = <2>; 112 nonposted-mmio; 113 ranges; 114 115 cpufreq: performance-controller@202220000 { 116 compatible = "apple,t7000-cluster-cpufreq", "apple,s5l8960x-cluster-cpufreq"; 117 reg = <0x2 0x02220000 0 0x1000>; 118 #performance-domain-cells = <0>; 119 }; 120 121 serial0: serial@20a0c0000 { 122 compatible = "apple,s5l-uart"; 123 reg = <0x2 0x0a0c0000 0x0 0x4000>; 124 reg-io-width = <4>; 125 interrupt-parent = <&aic>; 126 interrupts = <AIC_IRQ 158 IRQ_TYPE_LEVEL_HIGH>; 127 /* Use the bootloader-enabled clocks for now. */ 128 clocks = <&clkref>, <&clkref>; 129 clock-names = "uart", "clk_uart_baud0"; 130 power-domains = <&ps_uart0>; 131 status = "disabled"; 132 }; 133 134 serial6: serial@20a0d8000 { 135 compatible = "apple,s5l-uart"; 136 reg = <0x2 0x0a0d8000 0x0 0x4000>; 137 reg-io-width = <4>; 138 interrupt-parent = <&aic>; 139 interrupts = <AIC_IRQ 164 IRQ_TYPE_LEVEL_HIGH>; 140 /* Use the bootloader-enabled clocks for now. */ 141 clocks = <&clkref>, <&clkref>; 142 clock-names = "uart", "clk_uart_baud0"; 143 power-domains = <&ps_uart6>; 144 status = "disabled"; 145 }; 146 147 pmgr: power-management@20e000000 { 148 compatible = "apple,t7000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 149 #address-cells = <1>; 150 #size-cells = <1>; 151 152 reg = <0x2 0xe000000 0 0x24000>; 153 }; 154 155 wdt: watchdog@20e027000 { 156 compatible = "apple,t7000-wdt", "apple,wdt"; 157 reg = <0x2 0x0e027000 0x0 0x1000>; 158 clocks = <&clkref>; 159 interrupt-parent = <&aic>; 160 interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>; 161 }; 162 163 aic: interrupt-controller@20e100000 { 164 compatible = "apple,t7000-aic", "apple,aic"; 165 reg = <0x2 0x0e100000 0x0 0x100000>; 166 #interrupt-cells = <3>; 167 interrupt-controller; 168 power-domains = <&ps_aic>; 169 }; 170 171 dwi_bl: backlight@20e200010 { 172 compatible = "apple,t7000-dwi-bl", "apple,dwi-bl"; 173 reg = <0x2 0x0e200010 0x0 0x8>; 174 power-domains = <&ps_dwi>; 175 status = "disabled"; 176 }; 177 178 pinctrl: pinctrl@20e300000 { 179 compatible = "apple,t7000-pinctrl", "apple,pinctrl"; 180 reg = <0x2 0x0e300000 0x0 0x100000>; 181 power-domains = <&ps_gpio>; 182 183 gpio-controller; 184 #gpio-cells = <2>; 185 gpio-ranges = <&pinctrl 0 0 208>; 186 apple,npins = <208>; 187 188 interrupt-controller; 189 #interrupt-cells = <2>; 190 interrupt-parent = <&aic>; 191 interrupts = <AIC_IRQ 62 IRQ_TYPE_LEVEL_HIGH>, 192 <AIC_IRQ 63 IRQ_TYPE_LEVEL_HIGH>, 193 <AIC_IRQ 64 IRQ_TYPE_LEVEL_HIGH>, 194 <AIC_IRQ 65 IRQ_TYPE_LEVEL_HIGH>, 195 <AIC_IRQ 66 IRQ_TYPE_LEVEL_HIGH>, 196 <AIC_IRQ 67 IRQ_TYPE_LEVEL_HIGH>, 197 <AIC_IRQ 68 IRQ_TYPE_LEVEL_HIGH>; 198 }; 199 }; 200 201 timer { 202 compatible = "arm,armv8-timer"; 203 interrupt-parent = <&aic>; 204 interrupt-names = "phys", "virt"; 205 /* Note that A8 doesn't actually have a hypervisor (EL2 is not implemented). */ 206 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 207 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; 208 }; 209}; 210 211#include "t7000-pmgr.dtsi" 212