xref: /linux/scripts/dtc/include-prefixes/arm64/apple/t602x-common.dtsi (revision 0f048c878ee32a4259dbf28e0ad8fd0b71ee0085)
1*a8f20eb6SHector Martin// SPDX-License-Identifier: GPL-2.0+ OR MIT
2*a8f20eb6SHector Martin/*
3*a8f20eb6SHector Martin * Nodes common to all T602x family SoCs (M2 Pro/Max/Ultra)
4*a8f20eb6SHector Martin *
5*a8f20eb6SHector Martin * Other names: H14J, "Rhodes Chop", "Rhodes", "Rhodes 2C"
6*a8f20eb6SHector Martin *
7*a8f20eb6SHector Martin * Copyright The Asahi Linux Contributors
8*a8f20eb6SHector Martin */
9*a8f20eb6SHector Martin
10*a8f20eb6SHector Martin/ {
11*a8f20eb6SHector Martin	#address-cells = <2>;
12*a8f20eb6SHector Martin	#size-cells = <2>;
13*a8f20eb6SHector Martin
14*a8f20eb6SHector Martin	aliases {
15*a8f20eb6SHector Martin		gpu = &gpu;
16*a8f20eb6SHector Martin	};
17*a8f20eb6SHector Martin
18*a8f20eb6SHector Martin	cpus {
19*a8f20eb6SHector Martin		#address-cells = <2>;
20*a8f20eb6SHector Martin		#size-cells = <0>;
21*a8f20eb6SHector Martin
22*a8f20eb6SHector Martin		cpu-map {
23*a8f20eb6SHector Martin			cluster0 {
24*a8f20eb6SHector Martin				core0 {
25*a8f20eb6SHector Martin					cpu = <&cpu_e00>;
26*a8f20eb6SHector Martin				};
27*a8f20eb6SHector Martin				core1 {
28*a8f20eb6SHector Martin					cpu = <&cpu_e01>;
29*a8f20eb6SHector Martin				};
30*a8f20eb6SHector Martin				core2 {
31*a8f20eb6SHector Martin					cpu = <&cpu_e02>;
32*a8f20eb6SHector Martin				};
33*a8f20eb6SHector Martin				core3 {
34*a8f20eb6SHector Martin					cpu = <&cpu_e03>;
35*a8f20eb6SHector Martin				};
36*a8f20eb6SHector Martin			};
37*a8f20eb6SHector Martin
38*a8f20eb6SHector Martin			cluster1 {
39*a8f20eb6SHector Martin				core0 {
40*a8f20eb6SHector Martin					cpu = <&cpu_p00>;
41*a8f20eb6SHector Martin				};
42*a8f20eb6SHector Martin				core1 {
43*a8f20eb6SHector Martin					cpu = <&cpu_p01>;
44*a8f20eb6SHector Martin				};
45*a8f20eb6SHector Martin				core2 {
46*a8f20eb6SHector Martin					cpu = <&cpu_p02>;
47*a8f20eb6SHector Martin				};
48*a8f20eb6SHector Martin				core3 {
49*a8f20eb6SHector Martin					cpu = <&cpu_p03>;
50*a8f20eb6SHector Martin				};
51*a8f20eb6SHector Martin			};
52*a8f20eb6SHector Martin
53*a8f20eb6SHector Martin			cluster2 {
54*a8f20eb6SHector Martin				core0 {
55*a8f20eb6SHector Martin					cpu = <&cpu_p10>;
56*a8f20eb6SHector Martin				};
57*a8f20eb6SHector Martin				core1 {
58*a8f20eb6SHector Martin					cpu = <&cpu_p11>;
59*a8f20eb6SHector Martin				};
60*a8f20eb6SHector Martin				core2 {
61*a8f20eb6SHector Martin					cpu = <&cpu_p12>;
62*a8f20eb6SHector Martin				};
63*a8f20eb6SHector Martin				core3 {
64*a8f20eb6SHector Martin					cpu = <&cpu_p13>;
65*a8f20eb6SHector Martin				};
66*a8f20eb6SHector Martin			};
67*a8f20eb6SHector Martin		};
68*a8f20eb6SHector Martin
69*a8f20eb6SHector Martin		cpu_e00: cpu@0 {
70*a8f20eb6SHector Martin			compatible = "apple,blizzard";
71*a8f20eb6SHector Martin			device_type = "cpu";
72*a8f20eb6SHector Martin			reg = <0x0 0x0>;
73*a8f20eb6SHector Martin			enable-method = "spin-table";
74*a8f20eb6SHector Martin			cpu-release-addr = <0 0>; /* to be filled by loader */
75*a8f20eb6SHector Martin			next-level-cache = <&l2_cache_0>;
76*a8f20eb6SHector Martin			i-cache-size = <0x20000>;
77*a8f20eb6SHector Martin			d-cache-size = <0x10000>;
78*a8f20eb6SHector Martin			operating-points-v2 = <&blizzard_opp>;
79*a8f20eb6SHector Martin			capacity-dmips-mhz = <756>;
80*a8f20eb6SHector Martin			performance-domains = <&cpufreq_e>;
81*a8f20eb6SHector Martin		};
82*a8f20eb6SHector Martin
83*a8f20eb6SHector Martin		cpu_e01: cpu@1 {
84*a8f20eb6SHector Martin			compatible = "apple,blizzard";
85*a8f20eb6SHector Martin			device_type = "cpu";
86*a8f20eb6SHector Martin			reg = <0x0 0x1>;
87*a8f20eb6SHector Martin			enable-method = "spin-table";
88*a8f20eb6SHector Martin			cpu-release-addr = <0 0>; /* to be filled by loader */
89*a8f20eb6SHector Martin			next-level-cache = <&l2_cache_0>;
90*a8f20eb6SHector Martin			i-cache-size = <0x20000>;
91*a8f20eb6SHector Martin			d-cache-size = <0x10000>;
92*a8f20eb6SHector Martin			operating-points-v2 = <&blizzard_opp>;
93*a8f20eb6SHector Martin			capacity-dmips-mhz = <756>;
94*a8f20eb6SHector Martin			performance-domains = <&cpufreq_e>;
95*a8f20eb6SHector Martin		};
96*a8f20eb6SHector Martin
97*a8f20eb6SHector Martin		cpu_e02: cpu@2 {
98*a8f20eb6SHector Martin			compatible = "apple,blizzard";
99*a8f20eb6SHector Martin			device_type = "cpu";
100*a8f20eb6SHector Martin			reg = <0x0 0x2>;
101*a8f20eb6SHector Martin			enable-method = "spin-table";
102*a8f20eb6SHector Martin			cpu-release-addr = <0 0>; /* to be filled by loader */
103*a8f20eb6SHector Martin			next-level-cache = <&l2_cache_0>;
104*a8f20eb6SHector Martin			i-cache-size = <0x20000>;
105*a8f20eb6SHector Martin			d-cache-size = <0x10000>;
106*a8f20eb6SHector Martin			operating-points-v2 = <&blizzard_opp>;
107*a8f20eb6SHector Martin			capacity-dmips-mhz = <756>;
108*a8f20eb6SHector Martin			performance-domains = <&cpufreq_e>;
109*a8f20eb6SHector Martin		};
110*a8f20eb6SHector Martin
111*a8f20eb6SHector Martin		cpu_e03: cpu@3 {
112*a8f20eb6SHector Martin			compatible = "apple,blizzard";
113*a8f20eb6SHector Martin			device_type = "cpu";
114*a8f20eb6SHector Martin			reg = <0x0 0x3>;
115*a8f20eb6SHector Martin			enable-method = "spin-table";
116*a8f20eb6SHector Martin			cpu-release-addr = <0 0>; /* to be filled by loader */
117*a8f20eb6SHector Martin			next-level-cache = <&l2_cache_0>;
118*a8f20eb6SHector Martin			i-cache-size = <0x20000>;
119*a8f20eb6SHector Martin			d-cache-size = <0x10000>;
120*a8f20eb6SHector Martin			operating-points-v2 = <&blizzard_opp>;
121*a8f20eb6SHector Martin			capacity-dmips-mhz = <756>;
122*a8f20eb6SHector Martin			performance-domains = <&cpufreq_e>;
123*a8f20eb6SHector Martin		};
124*a8f20eb6SHector Martin
125*a8f20eb6SHector Martin		cpu_p00: cpu@10100 {
126*a8f20eb6SHector Martin			compatible = "apple,avalanche";
127*a8f20eb6SHector Martin			device_type = "cpu";
128*a8f20eb6SHector Martin			reg = <0x0 0x10100>;
129*a8f20eb6SHector Martin			enable-method = "spin-table";
130*a8f20eb6SHector Martin			cpu-release-addr = <0 0>; /* To be filled by loader */
131*a8f20eb6SHector Martin			next-level-cache = <&l2_cache_1>;
132*a8f20eb6SHector Martin			i-cache-size = <0x30000>;
133*a8f20eb6SHector Martin			d-cache-size = <0x20000>;
134*a8f20eb6SHector Martin			operating-points-v2 = <&avalanche_opp>;
135*a8f20eb6SHector Martin			capacity-dmips-mhz = <1024>;
136*a8f20eb6SHector Martin			performance-domains = <&cpufreq_p0>;
137*a8f20eb6SHector Martin		};
138*a8f20eb6SHector Martin
139*a8f20eb6SHector Martin		cpu_p01: cpu@10101 {
140*a8f20eb6SHector Martin			compatible = "apple,avalanche";
141*a8f20eb6SHector Martin			device_type = "cpu";
142*a8f20eb6SHector Martin			reg = <0x0 0x10101>;
143*a8f20eb6SHector Martin			enable-method = "spin-table";
144*a8f20eb6SHector Martin			cpu-release-addr = <0 0>; /* To be filled by loader */
145*a8f20eb6SHector Martin			next-level-cache = <&l2_cache_1>;
146*a8f20eb6SHector Martin			i-cache-size = <0x30000>;
147*a8f20eb6SHector Martin			d-cache-size = <0x20000>;
148*a8f20eb6SHector Martin			operating-points-v2 = <&avalanche_opp>;
149*a8f20eb6SHector Martin			capacity-dmips-mhz = <1024>;
150*a8f20eb6SHector Martin			performance-domains = <&cpufreq_p0>;
151*a8f20eb6SHector Martin		};
152*a8f20eb6SHector Martin
153*a8f20eb6SHector Martin		cpu_p02: cpu@10102 {
154*a8f20eb6SHector Martin			compatible = "apple,avalanche";
155*a8f20eb6SHector Martin			device_type = "cpu";
156*a8f20eb6SHector Martin			reg = <0x0 0x10102>;
157*a8f20eb6SHector Martin			enable-method = "spin-table";
158*a8f20eb6SHector Martin			cpu-release-addr = <0 0>; /* To be filled by loader */
159*a8f20eb6SHector Martin			next-level-cache = <&l2_cache_1>;
160*a8f20eb6SHector Martin			i-cache-size = <0x30000>;
161*a8f20eb6SHector Martin			d-cache-size = <0x20000>;
162*a8f20eb6SHector Martin			operating-points-v2 = <&avalanche_opp>;
163*a8f20eb6SHector Martin			capacity-dmips-mhz = <1024>;
164*a8f20eb6SHector Martin			performance-domains = <&cpufreq_p0>;
165*a8f20eb6SHector Martin		};
166*a8f20eb6SHector Martin
167*a8f20eb6SHector Martin		cpu_p03: cpu@10103 {
168*a8f20eb6SHector Martin			compatible = "apple,avalanche";
169*a8f20eb6SHector Martin			device_type = "cpu";
170*a8f20eb6SHector Martin			reg = <0x0 0x10103>;
171*a8f20eb6SHector Martin			enable-method = "spin-table";
172*a8f20eb6SHector Martin			cpu-release-addr = <0 0>; /* To be filled by loader */
173*a8f20eb6SHector Martin			next-level-cache = <&l2_cache_1>;
174*a8f20eb6SHector Martin			i-cache-size = <0x30000>;
175*a8f20eb6SHector Martin			d-cache-size = <0x20000>;
176*a8f20eb6SHector Martin			operating-points-v2 = <&avalanche_opp>;
177*a8f20eb6SHector Martin			capacity-dmips-mhz = <1024>;
178*a8f20eb6SHector Martin			performance-domains = <&cpufreq_p0>;
179*a8f20eb6SHector Martin		};
180*a8f20eb6SHector Martin
181*a8f20eb6SHector Martin		cpu_p10: cpu@10200 {
182*a8f20eb6SHector Martin			compatible = "apple,avalanche";
183*a8f20eb6SHector Martin			device_type = "cpu";
184*a8f20eb6SHector Martin			reg = <0x0 0x10200>;
185*a8f20eb6SHector Martin			enable-method = "spin-table";
186*a8f20eb6SHector Martin			cpu-release-addr = <0 0>; /* To be filled by loader */
187*a8f20eb6SHector Martin			next-level-cache = <&l2_cache_2>;
188*a8f20eb6SHector Martin			i-cache-size = <0x30000>;
189*a8f20eb6SHector Martin			d-cache-size = <0x20000>;
190*a8f20eb6SHector Martin			operating-points-v2 = <&avalanche_opp>;
191*a8f20eb6SHector Martin			capacity-dmips-mhz = <1024>;
192*a8f20eb6SHector Martin			performance-domains = <&cpufreq_p1>;
193*a8f20eb6SHector Martin		};
194*a8f20eb6SHector Martin
195*a8f20eb6SHector Martin		cpu_p11: cpu@10201 {
196*a8f20eb6SHector Martin			compatible = "apple,avalanche";
197*a8f20eb6SHector Martin			device_type = "cpu";
198*a8f20eb6SHector Martin			reg = <0x0 0x10201>;
199*a8f20eb6SHector Martin			enable-method = "spin-table";
200*a8f20eb6SHector Martin			cpu-release-addr = <0 0>; /* To be filled by loader */
201*a8f20eb6SHector Martin			next-level-cache = <&l2_cache_2>;
202*a8f20eb6SHector Martin			i-cache-size = <0x30000>;
203*a8f20eb6SHector Martin			d-cache-size = <0x20000>;
204*a8f20eb6SHector Martin			operating-points-v2 = <&avalanche_opp>;
205*a8f20eb6SHector Martin			capacity-dmips-mhz = <1024>;
206*a8f20eb6SHector Martin			performance-domains = <&cpufreq_p1>;
207*a8f20eb6SHector Martin		};
208*a8f20eb6SHector Martin
209*a8f20eb6SHector Martin		cpu_p12: cpu@10202 {
210*a8f20eb6SHector Martin			compatible = "apple,avalanche";
211*a8f20eb6SHector Martin			device_type = "cpu";
212*a8f20eb6SHector Martin			reg = <0x0 0x10202>;
213*a8f20eb6SHector Martin			enable-method = "spin-table";
214*a8f20eb6SHector Martin			cpu-release-addr = <0 0>; /* To be filled by loader */
215*a8f20eb6SHector Martin			next-level-cache = <&l2_cache_2>;
216*a8f20eb6SHector Martin			i-cache-size = <0x30000>;
217*a8f20eb6SHector Martin			d-cache-size = <0x20000>;
218*a8f20eb6SHector Martin			operating-points-v2 = <&avalanche_opp>;
219*a8f20eb6SHector Martin			capacity-dmips-mhz = <1024>;
220*a8f20eb6SHector Martin			performance-domains = <&cpufreq_p1>;
221*a8f20eb6SHector Martin		};
222*a8f20eb6SHector Martin
223*a8f20eb6SHector Martin		cpu_p13: cpu@10203 {
224*a8f20eb6SHector Martin			compatible = "apple,avalanche";
225*a8f20eb6SHector Martin			device_type = "cpu";
226*a8f20eb6SHector Martin			reg = <0x0 0x10203>;
227*a8f20eb6SHector Martin			enable-method = "spin-table";
228*a8f20eb6SHector Martin			cpu-release-addr = <0 0>; /* To be filled by loader */
229*a8f20eb6SHector Martin			next-level-cache = <&l2_cache_2>;
230*a8f20eb6SHector Martin			i-cache-size = <0x30000>;
231*a8f20eb6SHector Martin			d-cache-size = <0x20000>;
232*a8f20eb6SHector Martin			operating-points-v2 = <&avalanche_opp>;
233*a8f20eb6SHector Martin			capacity-dmips-mhz = <1024>;
234*a8f20eb6SHector Martin			performance-domains = <&cpufreq_p1>;
235*a8f20eb6SHector Martin		};
236*a8f20eb6SHector Martin
237*a8f20eb6SHector Martin		l2_cache_0: l2-cache-0 {
238*a8f20eb6SHector Martin			compatible = "cache";
239*a8f20eb6SHector Martin			cache-level = <2>;
240*a8f20eb6SHector Martin			cache-unified;
241*a8f20eb6SHector Martin			cache-size = <0x400000>;
242*a8f20eb6SHector Martin		};
243*a8f20eb6SHector Martin
244*a8f20eb6SHector Martin		l2_cache_1: l2-cache-1 {
245*a8f20eb6SHector Martin			compatible = "cache";
246*a8f20eb6SHector Martin			cache-level = <2>;
247*a8f20eb6SHector Martin			cache-unified;
248*a8f20eb6SHector Martin			cache-size = <0x1000000>;
249*a8f20eb6SHector Martin		};
250*a8f20eb6SHector Martin
251*a8f20eb6SHector Martin		l2_cache_2: l2-cache-2 {
252*a8f20eb6SHector Martin			compatible = "cache";
253*a8f20eb6SHector Martin			cache-level = <2>;
254*a8f20eb6SHector Martin			cache-unified;
255*a8f20eb6SHector Martin			cache-size = <0x1000000>;
256*a8f20eb6SHector Martin		};
257*a8f20eb6SHector Martin	 };
258*a8f20eb6SHector Martin
259*a8f20eb6SHector Martin	blizzard_opp: opp-table-0 {
260*a8f20eb6SHector Martin		compatible = "operating-points-v2";
261*a8f20eb6SHector Martin		opp-shared;
262*a8f20eb6SHector Martin
263*a8f20eb6SHector Martin		/* pstate #1 is a dummy clone of #2 */
264*a8f20eb6SHector Martin		opp02 {
265*a8f20eb6SHector Martin			opp-hz = /bits/ 64 <912000000>;
266*a8f20eb6SHector Martin			opp-level = <2>;
267*a8f20eb6SHector Martin			clock-latency-ns = <7700>;
268*a8f20eb6SHector Martin		};
269*a8f20eb6SHector Martin		opp03 {
270*a8f20eb6SHector Martin			opp-hz = /bits/ 64 <1284000000>;
271*a8f20eb6SHector Martin			opp-level = <3>;
272*a8f20eb6SHector Martin			clock-latency-ns = <25000>;
273*a8f20eb6SHector Martin		};
274*a8f20eb6SHector Martin		opp04 {
275*a8f20eb6SHector Martin			opp-hz = /bits/ 64 <1752000000>;
276*a8f20eb6SHector Martin			opp-level = <4>;
277*a8f20eb6SHector Martin			clock-latency-ns = <33000>;
278*a8f20eb6SHector Martin		};
279*a8f20eb6SHector Martin		opp05 {
280*a8f20eb6SHector Martin			opp-hz = /bits/ 64 <2004000000>;
281*a8f20eb6SHector Martin			opp-level = <5>;
282*a8f20eb6SHector Martin			clock-latency-ns = <38000>;
283*a8f20eb6SHector Martin		};
284*a8f20eb6SHector Martin		opp06 {
285*a8f20eb6SHector Martin			opp-hz = /bits/ 64 <2256000000>;
286*a8f20eb6SHector Martin			opp-level = <6>;
287*a8f20eb6SHector Martin			clock-latency-ns = <44000>;
288*a8f20eb6SHector Martin		};
289*a8f20eb6SHector Martin		opp07 {
290*a8f20eb6SHector Martin			opp-hz = /bits/ 64 <2424000000>;
291*a8f20eb6SHector Martin			opp-level = <7>;
292*a8f20eb6SHector Martin			clock-latency-ns = <48000>;
293*a8f20eb6SHector Martin		};
294*a8f20eb6SHector Martin	};
295*a8f20eb6SHector Martin
296*a8f20eb6SHector Martin	avalanche_opp: opp-table-1 {
297*a8f20eb6SHector Martin		compatible = "operating-points-v2";
298*a8f20eb6SHector Martin		opp-shared;
299*a8f20eb6SHector Martin
300*a8f20eb6SHector Martin		opp01 {
301*a8f20eb6SHector Martin			opp-hz = /bits/ 64 <702000000>;
302*a8f20eb6SHector Martin			opp-level = <1>;
303*a8f20eb6SHector Martin			clock-latency-ns = <7400>;
304*a8f20eb6SHector Martin		};
305*a8f20eb6SHector Martin		opp02 {
306*a8f20eb6SHector Martin			opp-hz = /bits/ 64 <948000000>;
307*a8f20eb6SHector Martin			opp-level = <2>;
308*a8f20eb6SHector Martin			clock-latency-ns = <18000>;
309*a8f20eb6SHector Martin		};
310*a8f20eb6SHector Martin		opp03 {
311*a8f20eb6SHector Martin			opp-hz = /bits/ 64 <1188000000>;
312*a8f20eb6SHector Martin			opp-level = <3>;
313*a8f20eb6SHector Martin			clock-latency-ns = <21000>;
314*a8f20eb6SHector Martin		};
315*a8f20eb6SHector Martin		opp04 {
316*a8f20eb6SHector Martin			opp-hz = /bits/ 64 <1452000000>;
317*a8f20eb6SHector Martin			opp-level = <4>;
318*a8f20eb6SHector Martin			clock-latency-ns = <24000>;
319*a8f20eb6SHector Martin		};
320*a8f20eb6SHector Martin		opp05 {
321*a8f20eb6SHector Martin			opp-hz = /bits/ 64 <1704000000>;
322*a8f20eb6SHector Martin			opp-level = <5>;
323*a8f20eb6SHector Martin			clock-latency-ns = <28000>;
324*a8f20eb6SHector Martin		};
325*a8f20eb6SHector Martin		opp06 {
326*a8f20eb6SHector Martin			opp-hz = /bits/ 64 <1968000000>;
327*a8f20eb6SHector Martin			opp-level = <6>;
328*a8f20eb6SHector Martin			clock-latency-ns = <31000>;
329*a8f20eb6SHector Martin		};
330*a8f20eb6SHector Martin		opp07 {
331*a8f20eb6SHector Martin			opp-hz = /bits/ 64 <2208000000>;
332*a8f20eb6SHector Martin			opp-level = <7>;
333*a8f20eb6SHector Martin			clock-latency-ns = <33000>;
334*a8f20eb6SHector Martin		};
335*a8f20eb6SHector Martin		opp08 {
336*a8f20eb6SHector Martin			opp-hz = /bits/ 64 <2400000000>;
337*a8f20eb6SHector Martin			opp-level = <8>;
338*a8f20eb6SHector Martin			clock-latency-ns = <45000>;
339*a8f20eb6SHector Martin		};
340*a8f20eb6SHector Martin		opp09 {
341*a8f20eb6SHector Martin			opp-hz = /bits/ 64 <2568000000>;
342*a8f20eb6SHector Martin			opp-level = <9>;
343*a8f20eb6SHector Martin			clock-latency-ns = <47000>;
344*a8f20eb6SHector Martin		};
345*a8f20eb6SHector Martin		opp10 {
346*a8f20eb6SHector Martin			opp-hz = /bits/ 64 <2724000000>;
347*a8f20eb6SHector Martin			opp-level = <10>;
348*a8f20eb6SHector Martin			clock-latency-ns = <50000>;
349*a8f20eb6SHector Martin		};
350*a8f20eb6SHector Martin		opp11 {
351*a8f20eb6SHector Martin			opp-hz = /bits/ 64 <2868000000>;
352*a8f20eb6SHector Martin			opp-level = <11>;
353*a8f20eb6SHector Martin			clock-latency-ns = <52000>;
354*a8f20eb6SHector Martin		};
355*a8f20eb6SHector Martin		opp12 {
356*a8f20eb6SHector Martin			opp-hz = /bits/ 64 <3000000000>;
357*a8f20eb6SHector Martin			opp-level = <12>;
358*a8f20eb6SHector Martin			clock-latency-ns = <57000>;
359*a8f20eb6SHector Martin		};
360*a8f20eb6SHector Martin		opp13 {
361*a8f20eb6SHector Martin			opp-hz = /bits/ 64 <3132000000>;
362*a8f20eb6SHector Martin			opp-level = <13>;
363*a8f20eb6SHector Martin			clock-latency-ns = <60000>;
364*a8f20eb6SHector Martin		};
365*a8f20eb6SHector Martin		opp14 {
366*a8f20eb6SHector Martin			opp-hz = /bits/ 64 <3264000000>;
367*a8f20eb6SHector Martin			opp-level = <14>;
368*a8f20eb6SHector Martin			clock-latency-ns = <64000>;
369*a8f20eb6SHector Martin		};
370*a8f20eb6SHector Martin		opp15 {
371*a8f20eb6SHector Martin			opp-hz = /bits/ 64 <3360000000>;
372*a8f20eb6SHector Martin			opp-level = <15>;
373*a8f20eb6SHector Martin			clock-latency-ns = <64000>;
374*a8f20eb6SHector Martin			turbo-mode;
375*a8f20eb6SHector Martin		};
376*a8f20eb6SHector Martin		opp16 {
377*a8f20eb6SHector Martin			opp-hz = /bits/ 64 <3408000000>;
378*a8f20eb6SHector Martin			opp-level = <16>;
379*a8f20eb6SHector Martin			clock-latency-ns = <64000>;
380*a8f20eb6SHector Martin			turbo-mode;
381*a8f20eb6SHector Martin		};
382*a8f20eb6SHector Martin		opp17 {
383*a8f20eb6SHector Martin			opp-hz = /bits/ 64 <3504000000>;
384*a8f20eb6SHector Martin			opp-level = <17>;
385*a8f20eb6SHector Martin			clock-latency-ns = <64000>;
386*a8f20eb6SHector Martin			turbo-mode;
387*a8f20eb6SHector Martin		};
388*a8f20eb6SHector Martin	};
389*a8f20eb6SHector Martin
390*a8f20eb6SHector Martin	pmu-e {
391*a8f20eb6SHector Martin		compatible = "apple,blizzard-pmu";
392*a8f20eb6SHector Martin		interrupt-parent = <&aic>;
393*a8f20eb6SHector Martin		interrupts = <AIC_FIQ 0 AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>;
394*a8f20eb6SHector Martin	};
395*a8f20eb6SHector Martin
396*a8f20eb6SHector Martin	pmu-p {
397*a8f20eb6SHector Martin		compatible = "apple,avalanche-pmu";
398*a8f20eb6SHector Martin		interrupt-parent = <&aic>;
399*a8f20eb6SHector Martin		interrupts = <AIC_FIQ 0 AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>;
400*a8f20eb6SHector Martin	};
401*a8f20eb6SHector Martin
402*a8f20eb6SHector Martin	timer {
403*a8f20eb6SHector Martin		compatible = "arm,armv8-timer";
404*a8f20eb6SHector Martin		interrupt-parent = <&aic>;
405*a8f20eb6SHector Martin		interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt";
406*a8f20eb6SHector Martin		interrupts = <AIC_FIQ 0 AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
407*a8f20eb6SHector Martin			     <AIC_FIQ 0 AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>,
408*a8f20eb6SHector Martin			     <AIC_FIQ 0 AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>,
409*a8f20eb6SHector Martin			     <AIC_FIQ 0 AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>;
410*a8f20eb6SHector Martin	};
411*a8f20eb6SHector Martin
412*a8f20eb6SHector Martin	clkref: clock-ref {
413*a8f20eb6SHector Martin		compatible = "fixed-clock";
414*a8f20eb6SHector Martin		#clock-cells = <0>;
415*a8f20eb6SHector Martin		clock-frequency = <24000000>;
416*a8f20eb6SHector Martin		clock-output-names = "clkref";
417*a8f20eb6SHector Martin	};
418*a8f20eb6SHector Martin
419*a8f20eb6SHector Martin	clk_200m: clock-200m {
420*a8f20eb6SHector Martin		compatible = "fixed-clock";
421*a8f20eb6SHector Martin		#clock-cells = <0>;
422*a8f20eb6SHector Martin		clock-frequency = <200000000>;
423*a8f20eb6SHector Martin		clock-output-names = "clk_200m";
424*a8f20eb6SHector Martin	};
425*a8f20eb6SHector Martin
426*a8f20eb6SHector Martin	/*
427*a8f20eb6SHector Martin	 * This is a fabulated representation of the input clock
428*a8f20eb6SHector Martin	 * to NCO since we don't know the true clock tree.
429*a8f20eb6SHector Martin	 */
430*a8f20eb6SHector Martin	nco_clkref: clock-ref-nco {
431*a8f20eb6SHector Martin		compatible = "fixed-clock";
432*a8f20eb6SHector Martin		#clock-cells = <0>;
433*a8f20eb6SHector Martin		clock-output-names = "nco_ref";
434*a8f20eb6SHector Martin	};
435*a8f20eb6SHector Martin
436*a8f20eb6SHector Martin	reserved-memory {
437*a8f20eb6SHector Martin		#address-cells = <2>;
438*a8f20eb6SHector Martin		#size-cells = <2>;
439*a8f20eb6SHector Martin		ranges;
440*a8f20eb6SHector Martin
441*a8f20eb6SHector Martin		gpu_globals: globals {
442*a8f20eb6SHector Martin			status = "disabled";
443*a8f20eb6SHector Martin		};
444*a8f20eb6SHector Martin
445*a8f20eb6SHector Martin		gpu_hw_cal_a: hw-cal-a {
446*a8f20eb6SHector Martin			status = "disabled";
447*a8f20eb6SHector Martin		};
448*a8f20eb6SHector Martin
449*a8f20eb6SHector Martin		gpu_hw_cal_b: hw-cal-b {
450*a8f20eb6SHector Martin			status = "disabled";
451*a8f20eb6SHector Martin		};
452*a8f20eb6SHector Martin
453*a8f20eb6SHector Martin		uat_handoff: uat-handoff {
454*a8f20eb6SHector Martin			status = "disabled";
455*a8f20eb6SHector Martin		};
456*a8f20eb6SHector Martin
457*a8f20eb6SHector Martin		uat_pagetables: uat-pagetables {
458*a8f20eb6SHector Martin			status = "disabled";
459*a8f20eb6SHector Martin		};
460*a8f20eb6SHector Martin
461*a8f20eb6SHector Martin		uat_ttbs: uat-ttbs {
462*a8f20eb6SHector Martin			status = "disabled";
463*a8f20eb6SHector Martin		};
464*a8f20eb6SHector Martin	};
465*a8f20eb6SHector Martin};
466