1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Nodes common to all T602x family SoCs (M2 Pro/Max/Ultra) 4 * 5 * Other names: H14J, "Rhodes Chop", "Rhodes", "Rhodes 2C" 6 * 7 * Copyright The Asahi Linux Contributors 8 */ 9 10/ { 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 aliases { 15 gpu = &gpu; 16 }; 17 18 cpus { 19 #address-cells = <2>; 20 #size-cells = <0>; 21 22 cpu-map { 23 cluster0 { 24 core0 { 25 cpu = <&cpu_e00>; 26 }; 27 core1 { 28 cpu = <&cpu_e01>; 29 }; 30 core2 { 31 cpu = <&cpu_e02>; 32 }; 33 core3 { 34 cpu = <&cpu_e03>; 35 }; 36 }; 37 38 cluster1 { 39 core0 { 40 cpu = <&cpu_p00>; 41 }; 42 core1 { 43 cpu = <&cpu_p01>; 44 }; 45 core2 { 46 cpu = <&cpu_p02>; 47 }; 48 core3 { 49 cpu = <&cpu_p03>; 50 }; 51 }; 52 53 cluster2 { 54 core0 { 55 cpu = <&cpu_p10>; 56 }; 57 core1 { 58 cpu = <&cpu_p11>; 59 }; 60 core2 { 61 cpu = <&cpu_p12>; 62 }; 63 core3 { 64 cpu = <&cpu_p13>; 65 }; 66 }; 67 }; 68 69 cpu_e00: cpu@0 { 70 compatible = "apple,blizzard"; 71 device_type = "cpu"; 72 reg = <0x0 0x0>; 73 enable-method = "spin-table"; 74 cpu-release-addr = <0 0>; /* to be filled by loader */ 75 next-level-cache = <&l2_cache_0>; 76 i-cache-size = <0x20000>; 77 d-cache-size = <0x10000>; 78 operating-points-v2 = <&blizzard_opp>; 79 capacity-dmips-mhz = <756>; 80 performance-domains = <&cpufreq_e>; 81 }; 82 83 cpu_e01: cpu@1 { 84 compatible = "apple,blizzard"; 85 device_type = "cpu"; 86 reg = <0x0 0x1>; 87 enable-method = "spin-table"; 88 cpu-release-addr = <0 0>; /* to be filled by loader */ 89 next-level-cache = <&l2_cache_0>; 90 i-cache-size = <0x20000>; 91 d-cache-size = <0x10000>; 92 operating-points-v2 = <&blizzard_opp>; 93 capacity-dmips-mhz = <756>; 94 performance-domains = <&cpufreq_e>; 95 }; 96 97 cpu_e02: cpu@2 { 98 compatible = "apple,blizzard"; 99 device_type = "cpu"; 100 reg = <0x0 0x2>; 101 enable-method = "spin-table"; 102 cpu-release-addr = <0 0>; /* to be filled by loader */ 103 next-level-cache = <&l2_cache_0>; 104 i-cache-size = <0x20000>; 105 d-cache-size = <0x10000>; 106 operating-points-v2 = <&blizzard_opp>; 107 capacity-dmips-mhz = <756>; 108 performance-domains = <&cpufreq_e>; 109 }; 110 111 cpu_e03: cpu@3 { 112 compatible = "apple,blizzard"; 113 device_type = "cpu"; 114 reg = <0x0 0x3>; 115 enable-method = "spin-table"; 116 cpu-release-addr = <0 0>; /* to be filled by loader */ 117 next-level-cache = <&l2_cache_0>; 118 i-cache-size = <0x20000>; 119 d-cache-size = <0x10000>; 120 operating-points-v2 = <&blizzard_opp>; 121 capacity-dmips-mhz = <756>; 122 performance-domains = <&cpufreq_e>; 123 }; 124 125 cpu_p00: cpu@10100 { 126 compatible = "apple,avalanche"; 127 device_type = "cpu"; 128 reg = <0x0 0x10100>; 129 enable-method = "spin-table"; 130 cpu-release-addr = <0 0>; /* To be filled by loader */ 131 next-level-cache = <&l2_cache_1>; 132 i-cache-size = <0x30000>; 133 d-cache-size = <0x20000>; 134 operating-points-v2 = <&avalanche_opp>; 135 capacity-dmips-mhz = <1024>; 136 performance-domains = <&cpufreq_p0>; 137 }; 138 139 cpu_p01: cpu@10101 { 140 compatible = "apple,avalanche"; 141 device_type = "cpu"; 142 reg = <0x0 0x10101>; 143 enable-method = "spin-table"; 144 cpu-release-addr = <0 0>; /* To be filled by loader */ 145 next-level-cache = <&l2_cache_1>; 146 i-cache-size = <0x30000>; 147 d-cache-size = <0x20000>; 148 operating-points-v2 = <&avalanche_opp>; 149 capacity-dmips-mhz = <1024>; 150 performance-domains = <&cpufreq_p0>; 151 }; 152 153 cpu_p02: cpu@10102 { 154 compatible = "apple,avalanche"; 155 device_type = "cpu"; 156 reg = <0x0 0x10102>; 157 enable-method = "spin-table"; 158 cpu-release-addr = <0 0>; /* To be filled by loader */ 159 next-level-cache = <&l2_cache_1>; 160 i-cache-size = <0x30000>; 161 d-cache-size = <0x20000>; 162 operating-points-v2 = <&avalanche_opp>; 163 capacity-dmips-mhz = <1024>; 164 performance-domains = <&cpufreq_p0>; 165 }; 166 167 cpu_p03: cpu@10103 { 168 compatible = "apple,avalanche"; 169 device_type = "cpu"; 170 reg = <0x0 0x10103>; 171 enable-method = "spin-table"; 172 cpu-release-addr = <0 0>; /* To be filled by loader */ 173 next-level-cache = <&l2_cache_1>; 174 i-cache-size = <0x30000>; 175 d-cache-size = <0x20000>; 176 operating-points-v2 = <&avalanche_opp>; 177 capacity-dmips-mhz = <1024>; 178 performance-domains = <&cpufreq_p0>; 179 }; 180 181 cpu_p10: cpu@10200 { 182 compatible = "apple,avalanche"; 183 device_type = "cpu"; 184 reg = <0x0 0x10200>; 185 enable-method = "spin-table"; 186 cpu-release-addr = <0 0>; /* To be filled by loader */ 187 next-level-cache = <&l2_cache_2>; 188 i-cache-size = <0x30000>; 189 d-cache-size = <0x20000>; 190 operating-points-v2 = <&avalanche_opp>; 191 capacity-dmips-mhz = <1024>; 192 performance-domains = <&cpufreq_p1>; 193 }; 194 195 cpu_p11: cpu@10201 { 196 compatible = "apple,avalanche"; 197 device_type = "cpu"; 198 reg = <0x0 0x10201>; 199 enable-method = "spin-table"; 200 cpu-release-addr = <0 0>; /* To be filled by loader */ 201 next-level-cache = <&l2_cache_2>; 202 i-cache-size = <0x30000>; 203 d-cache-size = <0x20000>; 204 operating-points-v2 = <&avalanche_opp>; 205 capacity-dmips-mhz = <1024>; 206 performance-domains = <&cpufreq_p1>; 207 }; 208 209 cpu_p12: cpu@10202 { 210 compatible = "apple,avalanche"; 211 device_type = "cpu"; 212 reg = <0x0 0x10202>; 213 enable-method = "spin-table"; 214 cpu-release-addr = <0 0>; /* To be filled by loader */ 215 next-level-cache = <&l2_cache_2>; 216 i-cache-size = <0x30000>; 217 d-cache-size = <0x20000>; 218 operating-points-v2 = <&avalanche_opp>; 219 capacity-dmips-mhz = <1024>; 220 performance-domains = <&cpufreq_p1>; 221 }; 222 223 cpu_p13: cpu@10203 { 224 compatible = "apple,avalanche"; 225 device_type = "cpu"; 226 reg = <0x0 0x10203>; 227 enable-method = "spin-table"; 228 cpu-release-addr = <0 0>; /* To be filled by loader */ 229 next-level-cache = <&l2_cache_2>; 230 i-cache-size = <0x30000>; 231 d-cache-size = <0x20000>; 232 operating-points-v2 = <&avalanche_opp>; 233 capacity-dmips-mhz = <1024>; 234 performance-domains = <&cpufreq_p1>; 235 }; 236 237 l2_cache_0: l2-cache-0 { 238 compatible = "cache"; 239 cache-level = <2>; 240 cache-unified; 241 cache-size = <0x400000>; 242 }; 243 244 l2_cache_1: l2-cache-1 { 245 compatible = "cache"; 246 cache-level = <2>; 247 cache-unified; 248 cache-size = <0x1000000>; 249 }; 250 251 l2_cache_2: l2-cache-2 { 252 compatible = "cache"; 253 cache-level = <2>; 254 cache-unified; 255 cache-size = <0x1000000>; 256 }; 257 }; 258 259 blizzard_opp: opp-table-0 { 260 compatible = "operating-points-v2"; 261 opp-shared; 262 263 /* pstate #1 is a dummy clone of #2 */ 264 opp02 { 265 opp-hz = /bits/ 64 <912000000>; 266 opp-level = <2>; 267 clock-latency-ns = <7700>; 268 }; 269 opp03 { 270 opp-hz = /bits/ 64 <1284000000>; 271 opp-level = <3>; 272 clock-latency-ns = <25000>; 273 }; 274 opp04 { 275 opp-hz = /bits/ 64 <1752000000>; 276 opp-level = <4>; 277 clock-latency-ns = <33000>; 278 }; 279 opp05 { 280 opp-hz = /bits/ 64 <2004000000>; 281 opp-level = <5>; 282 clock-latency-ns = <38000>; 283 }; 284 opp06 { 285 opp-hz = /bits/ 64 <2256000000>; 286 opp-level = <6>; 287 clock-latency-ns = <44000>; 288 }; 289 opp07 { 290 opp-hz = /bits/ 64 <2424000000>; 291 opp-level = <7>; 292 clock-latency-ns = <48000>; 293 }; 294 }; 295 296 avalanche_opp: opp-table-1 { 297 compatible = "operating-points-v2"; 298 opp-shared; 299 300 opp01 { 301 opp-hz = /bits/ 64 <702000000>; 302 opp-level = <1>; 303 clock-latency-ns = <7400>; 304 }; 305 opp02 { 306 opp-hz = /bits/ 64 <948000000>; 307 opp-level = <2>; 308 clock-latency-ns = <18000>; 309 }; 310 opp03 { 311 opp-hz = /bits/ 64 <1188000000>; 312 opp-level = <3>; 313 clock-latency-ns = <21000>; 314 }; 315 opp04 { 316 opp-hz = /bits/ 64 <1452000000>; 317 opp-level = <4>; 318 clock-latency-ns = <24000>; 319 }; 320 opp05 { 321 opp-hz = /bits/ 64 <1704000000>; 322 opp-level = <5>; 323 clock-latency-ns = <28000>; 324 }; 325 opp06 { 326 opp-hz = /bits/ 64 <1968000000>; 327 opp-level = <6>; 328 clock-latency-ns = <31000>; 329 }; 330 opp07 { 331 opp-hz = /bits/ 64 <2208000000>; 332 opp-level = <7>; 333 clock-latency-ns = <33000>; 334 }; 335 opp08 { 336 opp-hz = /bits/ 64 <2400000000>; 337 opp-level = <8>; 338 clock-latency-ns = <45000>; 339 }; 340 opp09 { 341 opp-hz = /bits/ 64 <2568000000>; 342 opp-level = <9>; 343 clock-latency-ns = <47000>; 344 }; 345 opp10 { 346 opp-hz = /bits/ 64 <2724000000>; 347 opp-level = <10>; 348 clock-latency-ns = <50000>; 349 }; 350 opp11 { 351 opp-hz = /bits/ 64 <2868000000>; 352 opp-level = <11>; 353 clock-latency-ns = <52000>; 354 }; 355 opp12 { 356 opp-hz = /bits/ 64 <3000000000>; 357 opp-level = <12>; 358 clock-latency-ns = <57000>; 359 }; 360 opp13 { 361 opp-hz = /bits/ 64 <3132000000>; 362 opp-level = <13>; 363 clock-latency-ns = <60000>; 364 }; 365 opp14 { 366 opp-hz = /bits/ 64 <3264000000>; 367 opp-level = <14>; 368 clock-latency-ns = <64000>; 369 }; 370 opp15 { 371 opp-hz = /bits/ 64 <3360000000>; 372 opp-level = <15>; 373 clock-latency-ns = <64000>; 374 turbo-mode; 375 }; 376 opp16 { 377 opp-hz = /bits/ 64 <3408000000>; 378 opp-level = <16>; 379 clock-latency-ns = <64000>; 380 turbo-mode; 381 }; 382 opp17 { 383 opp-hz = /bits/ 64 <3504000000>; 384 opp-level = <17>; 385 clock-latency-ns = <64000>; 386 turbo-mode; 387 }; 388 }; 389 390 pmu-e { 391 compatible = "apple,blizzard-pmu"; 392 interrupt-parent = <&aic>; 393 interrupts = <AIC_FIQ 0 AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>; 394 }; 395 396 pmu-p { 397 compatible = "apple,avalanche-pmu"; 398 interrupt-parent = <&aic>; 399 interrupts = <AIC_FIQ 0 AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>; 400 }; 401 402 timer { 403 compatible = "arm,armv8-timer"; 404 interrupt-parent = <&aic>; 405 interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; 406 interrupts = <AIC_FIQ 0 AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 407 <AIC_FIQ 0 AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>, 408 <AIC_FIQ 0 AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>, 409 <AIC_FIQ 0 AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>; 410 }; 411 412 clkref: clock-ref { 413 compatible = "fixed-clock"; 414 #clock-cells = <0>; 415 clock-frequency = <24000000>; 416 clock-output-names = "clkref"; 417 }; 418 419 clk_200m: clock-200m { 420 compatible = "fixed-clock"; 421 #clock-cells = <0>; 422 clock-frequency = <200000000>; 423 clock-output-names = "clk_200m"; 424 }; 425 426 /* 427 * This is a fabulated representation of the input clock 428 * to NCO since we don't know the true clock tree. 429 */ 430 nco_clkref: clock-ref-nco { 431 compatible = "fixed-clock"; 432 #clock-cells = <0>; 433 clock-output-names = "nco_ref"; 434 }; 435 436 reserved-memory { 437 #address-cells = <2>; 438 #size-cells = <2>; 439 ranges; 440 441 gpu_globals: globals { 442 status = "disabled"; 443 }; 444 445 gpu_hw_cal_a: hw-cal-a { 446 status = "disabled"; 447 }; 448 449 gpu_hw_cal_b: hw-cal-b { 450 status = "disabled"; 451 }; 452 453 uat_handoff: uat-handoff { 454 status = "disabled"; 455 }; 456 457 uat_pagetables: uat-pagetables { 458 status = "disabled"; 459 }; 460 461 uat_ttbs: uat-ttbs { 462 status = "disabled"; 463 }; 464 }; 465}; 466