1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple S8000/S8003 "A9" SoC 4 * 5 * This file contains parts common to both variants of A9 6 * 7 * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14 15/ { 16 interrupt-parent = <&aic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 clkref: clock-ref { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <24000000>; 24 clock-output-names = "clkref"; 25 }; 26 27 cpus { 28 #address-cells = <2>; 29 #size-cells = <0>; 30 31 cpu0: cpu@0 { 32 compatible = "apple,twister"; 33 reg = <0x0 0x0>; 34 cpu-release-addr = <0 0>; /* To be filled in by loader */ 35 operating-points-v2 = <&twister_opp>; 36 performance-domains = <&cpufreq>; 37 enable-method = "spin-table"; 38 device_type = "cpu"; 39 next-level-cache = <&l2_cache>; 40 i-cache-size = <0x10000>; 41 d-cache-size = <0x10000>; 42 }; 43 44 cpu1: cpu@1 { 45 compatible = "apple,twister"; 46 reg = <0x0 0x1>; 47 cpu-release-addr = <0 0>; /* To be filled in by loader */ 48 operating-points-v2 = <&twister_opp>; 49 performance-domains = <&cpufreq>; 50 enable-method = "spin-table"; 51 device_type = "cpu"; 52 next-level-cache = <&l2_cache>; 53 i-cache-size = <0x10000>; 54 d-cache-size = <0x10000>; 55 }; 56 57 l2_cache: l2-cache { 58 compatible = "cache"; 59 cache-level = <2>; 60 cache-unified; 61 cache-size = <0x300000>; 62 }; 63 }; 64 65 soc { 66 compatible = "simple-bus"; 67 #address-cells = <2>; 68 #size-cells = <2>; 69 nonposted-mmio; 70 ranges; 71 72 cpufreq: performance-controller@202220000 { 73 compatible = "apple,s8000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; 74 reg = <0x2 0x02220000 0 0x1000>; 75 #performance-domain-cells = <0>; 76 }; 77 78 serial0: serial@20a0c0000 { 79 compatible = "apple,s5l-uart"; 80 reg = <0x2 0x0a0c0000 0x0 0x4000>; 81 reg-io-width = <4>; 82 interrupt-parent = <&aic>; 83 interrupts = <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>; 84 /* Use the bootloader-enabled clocks for now. */ 85 clocks = <&clkref>, <&clkref>; 86 clock-names = "uart", "clk_uart_baud0"; 87 power-domains = <&ps_uart0>; 88 status = "disabled"; 89 }; 90 91 pmgr: power-management@20e000000 { 92 compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 93 #address-cells = <1>; 94 #size-cells = <1>; 95 96 reg = <0x2 0xe000000 0 0x8c000>; 97 }; 98 99 aic: interrupt-controller@20e100000 { 100 compatible = "apple,s8000-aic", "apple,aic"; 101 reg = <0x2 0x0e100000 0x0 0x100000>; 102 #interrupt-cells = <3>; 103 interrupt-controller; 104 power-domains = <&ps_aic>; 105 }; 106 107 dwi_bl: backlight@20e200080 { 108 compatible = "apple,s8000-dwi-bl", "apple,dwi-bl"; 109 reg = <0x2 0x0e200080 0x0 0x8>; 110 power-domains = <&ps_dwi>; 111 status = "disabled"; 112 }; 113 114 pinctrl_ap: pinctrl@20f100000 { 115 compatible = "apple,s8000-pinctrl", "apple,pinctrl"; 116 reg = <0x2 0x0f100000 0x0 0x100000>; 117 power-domains = <&ps_gpio>; 118 119 gpio-controller; 120 #gpio-cells = <2>; 121 gpio-ranges = <&pinctrl_ap 0 0 208>; 122 apple,npins = <208>; 123 124 interrupt-controller; 125 #interrupt-cells = <2>; 126 interrupt-parent = <&aic>; 127 interrupts = <AIC_IRQ 42 IRQ_TYPE_LEVEL_HIGH>, 128 <AIC_IRQ 43 IRQ_TYPE_LEVEL_HIGH>, 129 <AIC_IRQ 44 IRQ_TYPE_LEVEL_HIGH>, 130 <AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH>, 131 <AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>, 132 <AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>, 133 <AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>; 134 }; 135 136 pinctrl_aop: pinctrl@2100f0000 { 137 compatible = "apple,s8000-pinctrl", "apple,pinctrl"; 138 reg = <0x2 0x100f0000 0x0 0x100000>; 139 power-domains = <&ps_aop_gpio>; 140 141 gpio-controller; 142 #gpio-cells = <2>; 143 gpio-ranges = <&pinctrl_aop 0 0 42>; 144 apple,npins = <42>; 145 146 interrupt-controller; 147 #interrupt-cells = <2>; 148 interrupt-parent = <&aic>; 149 interrupts = <AIC_IRQ 113 IRQ_TYPE_LEVEL_HIGH>, 150 <AIC_IRQ 114 IRQ_TYPE_LEVEL_HIGH>, 151 <AIC_IRQ 115 IRQ_TYPE_LEVEL_HIGH>, 152 <AIC_IRQ 116 IRQ_TYPE_LEVEL_HIGH>, 153 <AIC_IRQ 117 IRQ_TYPE_LEVEL_HIGH>, 154 <AIC_IRQ 118 IRQ_TYPE_LEVEL_HIGH>, 155 <AIC_IRQ 119 IRQ_TYPE_LEVEL_HIGH>; 156 }; 157 158 pmgr_mini: power-management@210200000 { 159 compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 160 #address-cells = <1>; 161 #size-cells = <1>; 162 163 reg = <0x2 0x10200000 0 0x84000>; 164 }; 165 166 wdt: watchdog@2102b0000 { 167 compatible = "apple,s8000-wdt", "apple,wdt"; 168 reg = <0x2 0x102b0000 0x0 0x4000>; 169 clocks = <&clkref>; 170 interrupt-parent = <&aic>; 171 interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>; 172 }; 173 }; 174 175 timer { 176 compatible = "arm,armv8-timer"; 177 interrupt-parent = <&aic>; 178 interrupt-names = "phys", "virt"; 179 /* Note that A9 doesn't actually have a hypervisor (EL2 is not implemented). */ 180 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 181 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; 182 }; 183}; 184 185#include "s800-0-3-pmgr.dtsi" 186 187/* 188 * The A9 was made by two separate fabs on two different process 189 * nodes: Samsung made the S8000 (APL0898) on 14nm and TSMC made 190 * the S8003 (APL1022) on 16nm. There are some minor differences 191 * such as timing in cpufreq state transistions. 192 */ 193