1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2025 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/pinctrl/amlogic,pinctrl.h> 10 11/ { 12 cpus { 13 #address-cells = <2>; 14 #size-cells = <0>; 15 16 cpu0: cpu@0 { 17 device_type = "cpu"; 18 compatible = "arm,cortex-a55"; 19 reg = <0x0 0x0>; 20 enable-method = "psci"; 21 }; 22 23 cpu1: cpu@100 { 24 device_type = "cpu"; 25 compatible = "arm,cortex-a55"; 26 reg = <0x0 0x100>; 27 enable-method = "psci"; 28 }; 29 30 cpu2: cpu@200 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a55"; 33 reg = <0x0 0x200>; 34 enable-method = "psci"; 35 }; 36 37 cpu3: cpu@300 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a55"; 40 reg = <0x0 0x300>; 41 enable-method = "psci"; 42 }; 43 44 }; 45 46 timer { 47 compatible = "arm,armv8-timer"; 48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 52 }; 53 54 psci { 55 compatible = "arm,psci-1.0"; 56 method = "smc"; 57 }; 58 59 xtal: xtal-clk { 60 compatible = "fixed-clock"; 61 clock-frequency = <24000000>; 62 clock-output-names = "xtal"; 63 #clock-cells = <0>; 64 }; 65 66 soc { 67 compatible = "simple-bus"; 68 #address-cells = <2>; 69 #size-cells = <2>; 70 ranges; 71 72 gic: interrupt-controller@fff01000 { 73 compatible = "arm,gic-400"; 74 #interrupt-cells = <3>; 75 #address-cells = <0>; 76 interrupt-controller; 77 reg = <0x0 0xfff01000 0 0x1000>, 78 <0x0 0xfff02000 0 0x0100>; 79 interrupts = <GIC_PPI 9 0xf04>; 80 }; 81 82 apb: bus@fe000000 { 83 compatible = "simple-bus"; 84 reg = <0x0 0xfe000000 0x0 0x480000>; 85 #address-cells = <2>; 86 #size-cells = <2>; 87 ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; 88 89 uart_b: serial@7a000 { 90 compatible = "amlogic,s7d-uart", 91 "amlogic,meson-s4-uart"; 92 reg = <0x0 0x7a000 0x0 0x18>; 93 interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; 94 clocks = <&xtal>, <&xtal>, <&xtal>; 95 clock-names = "xtal", "pclk", "baud"; 96 status = "disabled"; 97 }; 98 99 periphs_pinctrl: pinctrl@4000 { 100 compatible = "amlogic,pinctrl-s7d", 101 "amlogic,pinctrl-s7"; 102 #address-cells = <2>; 103 #size-cells = <2>; 104 ranges = <0x0 0x0 0x0 0x4000 0x0 0x340>; 105 106 gpioz: gpio@c0 { 107 reg = <0 0xc0 0 0x20>, <0 0x18 0 0x8>; 108 reg-names = "gpio", "mux"; 109 gpio-controller; 110 #gpio-cells = <2>; 111 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_Z<<8) 13>; 112 }; 113 114 gpiox: gpio@100 { 115 reg = <0 0x100 0 0x30>, <0 0xc 0 0x8>; 116 reg-names = "gpio", "mux"; 117 gpio-controller; 118 #gpio-cells = <2>; 119 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 20>; 120 }; 121 122 gpioh: gpio@140 { 123 reg = <0 0x140 0 0x20>, <0 0x2c 0 0x8>; 124 reg-names = "gpio", "mux"; 125 gpio-controller; 126 #gpio-cells = <2>; 127 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_H<<8) 12>; 128 }; 129 130 gpiod: gpio@180 { 131 reg = <0 0x180 0 0x20>, <0 0x40 0 0x4>; 132 reg-names = "gpio", "mux"; 133 gpio-controller; 134 #gpio-cells = <2>; 135 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_D<<8) 5>; 136 }; 137 138 gpioe: gpio@1c0 { 139 reg = <0 0x1c0 0 0x20>, <0 0x48 0 0x4>; 140 reg-names = "gpio", "mux"; 141 gpio-controller; 142 #gpio-cells = <2>; 143 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_E<<8) 2>; 144 }; 145 146 gpioc: gpio@200 { 147 reg = <0 0x200 0 0x20>, <0 0x24 0 0x4>; 148 reg-names = "gpio", "mux"; 149 gpio-controller; 150 #gpio-cells = <2>; 151 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_C<<8) 8>; 152 }; 153 154 gpiob: gpio@240 { 155 reg = <0 0x240 0 0x20>, <0 0x0 0 0x8>; 156 reg-names = "gpio", "mux"; 157 gpio-controller; 158 #gpio-cells = <2>; 159 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_B<<8) 14>; 160 }; 161 162 gpiodv: gpio@280 { 163 reg = <0 0x280 0 0x20>, <0 0x8 0 0x4>; 164 reg-names = "gpio", "mux"; 165 gpio-controller; 166 #gpio-cells = <2>; 167 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_DV<<8) 7>; 168 }; 169 170 test_n: gpio@2c0 { 171 reg = <0 0x2c0 0 0x20>; 172 reg-names = "gpio"; 173 gpio-controller; 174 #gpio-cells = <2>; 175 gpio-ranges = 176 <&periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N<<8) 1>; 177 }; 178 179 gpiocc: gpio@300 { 180 reg = <0 0x300 0 0x20>, <0 0x14 0 0x4>; 181 reg-names = "gpio", "mux"; 182 gpio-controller; 183 #gpio-cells = <2>; 184 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_CC<<8) 2>; 185 }; 186 }; 187 }; 188 }; 189}; 190