1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2025 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/pinctrl/amlogic,pinctrl.h> 10/ { 11 cpus { 12 #address-cells = <2>; 13 #size-cells = <0>; 14 15 cpu0: cpu@0 { 16 device_type = "cpu"; 17 compatible = "arm,cortex-a510"; 18 reg = <0x0 0x0>; 19 enable-method = "psci"; 20 }; 21 22 cpu1: cpu@100 { 23 device_type = "cpu"; 24 compatible = "arm,cortex-a510"; 25 reg = <0x0 0x100>; 26 enable-method = "psci"; 27 }; 28 29 cpu2: cpu@200 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a510"; 32 reg = <0x0 0x200>; 33 enable-method = "psci"; 34 }; 35 36 cpu3: cpu@300 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a510"; 39 reg = <0x0 0x300>; 40 enable-method = "psci"; 41 }; 42 }; 43 44 timer { 45 compatible = "arm,armv8-timer"; 46 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 47 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 48 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 49 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 50 }; 51 52 psci { 53 compatible = "arm,psci-1.0"; 54 method = "smc"; 55 }; 56 57 xtal: xtal-clk { 58 compatible = "fixed-clock"; 59 clock-frequency = <24000000>; 60 clock-output-names = "xtal"; 61 #clock-cells = <0>; 62 }; 63 64 soc { 65 compatible = "simple-bus"; 66 #address-cells = <2>; 67 #size-cells = <2>; 68 ranges; 69 70 gic: interrupt-controller@ff200000 { 71 compatible = "arm,gic-v3"; 72 #interrupt-cells = <3>; 73 #address-cells = <0>; 74 interrupt-controller; 75 reg = <0x0 0xff200000 0 0x10000>, 76 <0x0 0xff240000 0 0x80000>; 77 interrupts = <GIC_PPI 9 0xf04>; 78 }; 79 80 apb: bus@fe000000 { 81 compatible = "simple-bus"; 82 reg = <0x0 0xfe000000 0x0 0x480000>; 83 #address-cells = <2>; 84 #size-cells = <2>; 85 ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; 86 87 uart_b: serial@7a000 { 88 compatible = "amlogic,s6-uart", 89 "amlogic,meson-s4-uart"; 90 reg = <0x0 0x7a000 0x0 0x18>; 91 interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; 92 clocks = <&xtal>, <&xtal>, <&xtal>; 93 clock-names = "xtal", "pclk", "baud"; 94 status = "disabled"; 95 }; 96 97 periphs_pinctrl: pinctrl@4000 { 98 compatible = "amlogic,pinctrl-s6"; 99 #address-cells = <2>; 100 #size-cells = <2>; 101 ranges = <0x0 0x0 0x0 0x4000 0x0 0x340>; 102 103 gpioz: gpio@c0 { 104 reg = <0 0xc0 0 0x20>, <0 0x18 0 0x8>; 105 reg-names = "gpio", "mux"; 106 gpio-controller; 107 #gpio-cells = <2>; 108 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_Z<<8) 16>; 109 }; 110 111 gpiox: gpio@100 { 112 reg = <0 0x100 0 0x30>, <0 0xc 0 0x8>; 113 reg-names = "gpio", "mux"; 114 gpio-controller; 115 #gpio-cells = <2>; 116 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 20>; 117 }; 118 119 gpioh: gpio@140 { 120 reg = <0 0x140 0 0x20>, <0 0x2c 0 0x8>; 121 reg-names = "gpio", "mux"; 122 gpio-controller; 123 #gpio-cells = <2>; 124 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_H<<8) 9>; 125 }; 126 127 gpiod: gpio@180 { 128 reg = <0 0x180 0 0x20>, <0 0x8 0 0x4>; 129 reg-names = "gpio", "mux"; 130 gpio-controller; 131 #gpio-cells = <2>; 132 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_D<<8) 7>; 133 }; 134 135 gpiof: gpio@1a0 { 136 reg = <0 0x1a0 0 0x20>, <0 0x20 0 0x4>; 137 reg-names = "gpio", "mux"; 138 gpio-controller; 139 #gpio-cells = <2>; 140 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_F<<8) 5>; 141 }; 142 143 gpioe: gpio@1c0 { 144 reg = <0 0x1c0 0 0x20>, <0 0x48 0 0x4>; 145 reg-names = "gpio", "mux"; 146 gpio-controller; 147 #gpio-cells = <2>; 148 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_E<<8) 3>; 149 }; 150 151 gpioc: gpio@200 { 152 reg = <0 0x200 0 0x20>, <0 0x24 0 0x4>; 153 reg-names = "gpio", "mux"; 154 gpio-controller; 155 #gpio-cells = <2>; 156 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_C<<8) 8>; 157 }; 158 159 gpiob: gpio@240 { 160 reg = <0 0x240 0 0x20>, <0 0x0 0 0x8>; 161 reg-names = "gpio", "mux"; 162 gpio-controller; 163 #gpio-cells = <2>; 164 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_B<<8) 14>; 165 }; 166 167 gpioa: gpio@280 { 168 reg = <0 0x280 0 0x20>, <0 0x40 0 0x8>; 169 reg-names = "gpio", "mux"; 170 gpio-controller; 171 #gpio-cells = <2>; 172 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_A<<8) 16>; 173 }; 174 175 test_n: gpio@2c0 { 176 reg = <0 0x2c0 0 0x20>; 177 reg-names = "gpio"; 178 gpio-controller; 179 #gpio-cells = <2>; 180 gpio-ranges = 181 <&periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N<<8) 1>; 182 }; 183 184 gpiocc: gpio@300 { 185 reg = <0 0x300 0 0x20>, <0 0x14 0 0x4>; 186 reg-names = "gpio", "mux"; 187 gpio-controller; 188 #gpio-cells = <2>; 189 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_CC<<8) 2>; 190 }; 191 }; 192 }; 193 }; 194}; 195